1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
227 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
229 // These instruction are deprecated so we don't want them to get selected.
230 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
235 let Inst{24-23} = 0b01; // Increment After
236 let Inst{21} = 0; // No writeback
237 let Inst{20} = L_bit;
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
242 let Inst{24-23} = 0b01; // Increment After
243 let Inst{21} = 1; // Writeback
244 let Inst{20} = L_bit;
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
249 let Inst{24-23} = 0b10; // Decrement Before
251 let Inst{20} = L_bit;
255 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
256 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
258 //===----------------------------------------------------------------------===//
259 // FP Binary Operations.
262 let TwoOperandAliasConstraint = "$Dn = $Dd" in
263 def VADDD : ADbI<0b11100, 0b11, 0, 0,
264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
268 let TwoOperandAliasConstraint = "$Sn = $Sd" in
269 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
273 // Some single precision VFP instructions may be executed on both NEON and
274 // VFP pipelines on A8.
275 let D = VFPNeonA8Domain;
278 let TwoOperandAliasConstraint = "$Dn = $Dd" in
279 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
284 let TwoOperandAliasConstraint = "$Sn = $Sd" in
285 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
289 // Some single precision VFP instructions may be executed on both NEON and
290 // VFP pipelines on A8.
291 let D = VFPNeonA8Domain;
294 let TwoOperandAliasConstraint = "$Dn = $Dd" in
295 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
300 let TwoOperandAliasConstraint = "$Sn = $Sd" in
301 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
306 let TwoOperandAliasConstraint = "$Dn = $Dd" in
307 def VMULD : ADbI<0b11100, 0b10, 0, 0,
308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
312 let TwoOperandAliasConstraint = "$Sn = $Sd" in
313 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
327 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
331 // Some single precision VFP instructions may be executed on both NEON and
332 // VFP pipelines on A8.
333 let D = VFPNeonA8Domain;
336 // Match reassociated forms only if not sign dependent rounding.
337 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
338 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
339 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
340 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
342 // These are encoded as unary instructions.
343 let Defs = [FPSCR_NZCV] in {
344 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
345 (outs), (ins DPR:$Dd, DPR:$Dm),
346 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
347 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
349 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
350 (outs), (ins SPR:$Sd, SPR:$Sm),
351 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
352 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
353 // Some single precision VFP instructions may be executed on both NEON and
354 // VFP pipelines on A8.
355 let D = VFPNeonA8Domain;
358 // FIXME: Verify encoding after integrated assembler is working.
359 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
360 (outs), (ins DPR:$Dd, DPR:$Dm),
361 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
362 [/* For disassembly only; pattern left blank */]>;
364 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
365 (outs), (ins SPR:$Sd, SPR:$Sm),
366 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
367 [/* For disassembly only; pattern left blank */]> {
368 // Some single precision VFP instructions may be executed on both NEON and
369 // VFP pipelines on A8.
370 let D = VFPNeonA8Domain;
372 } // Defs = [FPSCR_NZCV]
374 //===----------------------------------------------------------------------===//
375 // FP Unary Operations.
378 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
379 (outs DPR:$Dd), (ins DPR:$Dm),
380 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
381 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
383 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
384 (outs SPR:$Sd), (ins SPR:$Sm),
385 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
386 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
387 // Some single precision VFP instructions may be executed on both NEON and
388 // VFP pipelines on A8.
389 let D = VFPNeonA8Domain;
392 let Defs = [FPSCR_NZCV] in {
393 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
394 (outs), (ins DPR:$Dd),
395 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
396 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
397 let Inst{3-0} = 0b0000;
401 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
402 (outs), (ins SPR:$Sd),
403 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
404 [(arm_cmpfp0 SPR:$Sd)]> {
405 let Inst{3-0} = 0b0000;
408 // Some single precision VFP instructions may be executed on both NEON and
409 // VFP pipelines on A8.
410 let D = VFPNeonA8Domain;
413 // FIXME: Verify encoding after integrated assembler is working.
414 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
415 (outs), (ins DPR:$Dd),
416 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
417 [/* For disassembly only; pattern left blank */]> {
418 let Inst{3-0} = 0b0000;
422 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
423 (outs), (ins SPR:$Sd),
424 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
425 [/* For disassembly only; pattern left blank */]> {
426 let Inst{3-0} = 0b0000;
429 // Some single precision VFP instructions may be executed on both NEON and
430 // VFP pipelines on A8.
431 let D = VFPNeonA8Domain;
433 } // Defs = [FPSCR_NZCV]
435 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
436 (outs DPR:$Dd), (ins SPR:$Sm),
437 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
438 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
439 // Instruction operands.
443 // Encode instruction operands.
444 let Inst{3-0} = Sm{4-1};
446 let Inst{15-12} = Dd{3-0};
447 let Inst{22} = Dd{4};
450 // Special case encoding: bits 11-8 is 0b1011.
451 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
452 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
453 [(set SPR:$Sd, (fround DPR:$Dm))]> {
454 // Instruction operands.
458 // Encode instruction operands.
459 let Inst{3-0} = Dm{3-0};
461 let Inst{15-12} = Sd{4-1};
462 let Inst{22} = Sd{0};
464 let Inst{27-23} = 0b11101;
465 let Inst{21-16} = 0b110111;
466 let Inst{11-8} = 0b1011;
467 let Inst{7-6} = 0b11;
471 // Between half-precision and single-precision. For disassembly only.
473 // FIXME: Verify encoding after integrated assembler is working.
474 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
475 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
476 [/* For disassembly only; pattern left blank */]>;
478 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
479 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
480 [/* For disassembly only; pattern left blank */]>;
482 def : Pat<(f32_to_f16 SPR:$a),
483 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
485 def : Pat<(f16_to_f32 GPR:$a),
486 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
488 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
489 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
490 [/* For disassembly only; pattern left blank */]>;
492 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
493 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
494 [/* For disassembly only; pattern left blank */]>;
496 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
497 (outs DPR:$Dd), (ins DPR:$Dm),
498 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
499 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
501 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
502 (outs SPR:$Sd), (ins SPR:$Sm),
503 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
504 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
505 // Some single precision VFP instructions may be executed on both NEON and
506 // VFP pipelines on A8.
507 let D = VFPNeonA8Domain;
510 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
511 (outs DPR:$Dd), (ins DPR:$Dm),
512 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
513 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
515 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
516 (outs SPR:$Sd), (ins SPR:$Sm),
517 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
518 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
520 let neverHasSideEffects = 1 in {
521 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
522 (outs DPR:$Dd), (ins DPR:$Dm),
523 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
525 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
526 (outs SPR:$Sd), (ins SPR:$Sm),
527 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
528 } // neverHasSideEffects
530 //===----------------------------------------------------------------------===//
531 // FP <-> GPR Copies. Int <-> FP Conversions.
534 def VMOVRS : AVConv2I<0b11100001, 0b1010,
535 (outs GPR:$Rt), (ins SPR:$Sn),
536 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
537 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
538 // Instruction operands.
542 // Encode instruction operands.
543 let Inst{19-16} = Sn{4-1};
545 let Inst{15-12} = Rt;
547 let Inst{6-5} = 0b00;
548 let Inst{3-0} = 0b0000;
550 // Some single precision VFP instructions may be executed on both NEON and VFP
552 let D = VFPNeonDomain;
555 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
556 def VMOVSR : AVConv4I<0b11100000, 0b1010,
557 (outs SPR:$Sn), (ins GPR:$Rt),
558 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
559 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
560 Requires<[HasVFP2, UseVMOVSR]> {
561 // Instruction operands.
565 // Encode instruction operands.
566 let Inst{19-16} = Sn{4-1};
568 let Inst{15-12} = Rt;
570 let Inst{6-5} = 0b00;
571 let Inst{3-0} = 0b0000;
573 // Some single precision VFP instructions may be executed on both NEON and VFP
575 let D = VFPNeonDomain;
578 let neverHasSideEffects = 1 in {
579 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
580 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
581 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
582 [/* FIXME: Can't write pattern for multiple result instr*/]> {
583 // Instruction operands.
588 // Encode instruction operands.
589 let Inst{3-0} = Dm{3-0};
591 let Inst{15-12} = Rt;
592 let Inst{19-16} = Rt2;
594 let Inst{7-6} = 0b00;
596 // Some single precision VFP instructions may be executed on both NEON and VFP
598 let D = VFPNeonDomain;
601 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
602 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
603 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
604 [/* For disassembly only; pattern left blank */]> {
609 // Encode instruction operands.
610 let Inst{3-0} = src1{4-1};
611 let Inst{5} = src1{0};
612 let Inst{15-12} = Rt;
613 let Inst{19-16} = Rt2;
615 let Inst{7-6} = 0b00;
617 // Some single precision VFP instructions may be executed on both NEON and VFP
619 let D = VFPNeonDomain;
620 let DecoderMethod = "DecodeVMOVRRS";
622 } // neverHasSideEffects
627 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
628 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
629 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
630 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
631 // Instruction operands.
636 // Encode instruction operands.
637 let Inst{3-0} = Dm{3-0};
639 let Inst{15-12} = Rt;
640 let Inst{19-16} = Rt2;
642 let Inst{7-6} = 0b00;
644 // Some single precision VFP instructions may be executed on both NEON and VFP
646 let D = VFPNeonDomain;
649 let neverHasSideEffects = 1 in
650 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
651 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
652 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
653 [/* For disassembly only; pattern left blank */]> {
654 // Instruction operands.
659 // Encode instruction operands.
660 let Inst{3-0} = dst1{4-1};
661 let Inst{5} = dst1{0};
662 let Inst{15-12} = src1;
663 let Inst{19-16} = src2;
665 let Inst{7-6} = 0b00;
667 // Some single precision VFP instructions may be executed on both NEON and VFP
669 let D = VFPNeonDomain;
671 let DecoderMethod = "DecodeVMOVSRR";
677 // FMRX: SPR system reg -> GPR
679 // FMXR: GPR -> VFP system reg
684 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
685 bits<4> opcod4, dag oops, dag iops,
686 InstrItinClass itin, string opc, string asm,
688 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
690 // Instruction operands.
694 // Encode instruction operands.
695 let Inst{3-0} = Sm{4-1};
697 let Inst{15-12} = Dd{3-0};
698 let Inst{22} = Dd{4};
701 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
702 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
703 string opc, string asm, list<dag> pattern>
704 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
706 // Instruction operands.
710 // Encode instruction operands.
711 let Inst{3-0} = Sm{4-1};
713 let Inst{15-12} = Sd{4-1};
714 let Inst{22} = Sd{0};
717 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
718 (outs DPR:$Dd), (ins SPR:$Sm),
719 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
720 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
721 let Inst{7} = 1; // s32
724 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
725 (outs SPR:$Sd),(ins SPR:$Sm),
726 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
727 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
728 let Inst{7} = 1; // s32
730 // Some single precision VFP instructions may be executed on both NEON and
731 // VFP pipelines on A8.
732 let D = VFPNeonA8Domain;
735 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
736 (outs DPR:$Dd), (ins SPR:$Sm),
737 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
738 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
739 let Inst{7} = 0; // u32
742 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
743 (outs SPR:$Sd), (ins SPR:$Sm),
744 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
745 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
746 let Inst{7} = 0; // u32
748 // Some single precision VFP instructions may be executed on both NEON and
749 // VFP pipelines on A8.
750 let D = VFPNeonA8Domain;
755 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
756 bits<4> opcod4, dag oops, dag iops,
757 InstrItinClass itin, string opc, string asm,
759 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
761 // Instruction operands.
765 // Encode instruction operands.
766 let Inst{3-0} = Dm{3-0};
768 let Inst{15-12} = Sd{4-1};
769 let Inst{22} = Sd{0};
772 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
773 bits<4> opcod4, dag oops, dag iops,
774 InstrItinClass itin, string opc, string asm,
776 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
778 // Instruction operands.
782 // Encode instruction operands.
783 let Inst{3-0} = Sm{4-1};
785 let Inst{15-12} = Sd{4-1};
786 let Inst{22} = Sd{0};
789 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
790 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
791 (outs SPR:$Sd), (ins DPR:$Dm),
792 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
793 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
794 let Inst{7} = 1; // Z bit
797 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
798 (outs SPR:$Sd), (ins SPR:$Sm),
799 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
800 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
801 let Inst{7} = 1; // Z bit
803 // Some single precision VFP instructions may be executed on both NEON and
804 // VFP pipelines on A8.
805 let D = VFPNeonA8Domain;
808 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
809 (outs SPR:$Sd), (ins DPR:$Dm),
810 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
811 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
812 let Inst{7} = 1; // Z bit
815 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
816 (outs SPR:$Sd), (ins SPR:$Sm),
817 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
818 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
819 let Inst{7} = 1; // Z bit
821 // Some single precision VFP instructions may be executed on both NEON and
822 // VFP pipelines on A8.
823 let D = VFPNeonA8Domain;
826 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
827 let Uses = [FPSCR] in {
828 // FIXME: Verify encoding after integrated assembler is working.
829 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
830 (outs SPR:$Sd), (ins DPR:$Dm),
831 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
832 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
833 let Inst{7} = 0; // Z bit
836 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
837 (outs SPR:$Sd), (ins SPR:$Sm),
838 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
839 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
840 let Inst{7} = 0; // Z bit
843 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
844 (outs SPR:$Sd), (ins DPR:$Dm),
845 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
846 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
847 let Inst{7} = 0; // Z bit
850 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
851 (outs SPR:$Sd), (ins SPR:$Sm),
852 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
853 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
854 let Inst{7} = 0; // Z bit
858 // Convert between floating-point and fixed-point
859 // Data type for fixed-point naming convention:
860 // S16 (U=0, sx=0) -> SH
861 // U16 (U=1, sx=0) -> UH
862 // S32 (U=0, sx=1) -> SL
863 // U32 (U=1, sx=1) -> UL
865 let Constraints = "$a = $dst" in {
867 // FP to Fixed-Point:
869 // Single Precision register
870 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
871 bit op5, dag oops, dag iops, InstrItinClass itin,
872 string opc, string asm, list<dag> pattern>
873 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
874 Sched<[WriteCvtFP]> {
876 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
877 let Inst{22} = dst{0};
878 let Inst{15-12} = dst{4-1};
881 // Double Precision register
882 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
883 bit op5, dag oops, dag iops, InstrItinClass itin,
884 string opc, string asm, list<dag> pattern>
885 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
886 Sched<[WriteCvtFP]> {
888 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
889 let Inst{22} = dst{4};
890 let Inst{15-12} = dst{3-0};
893 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
894 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
895 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
896 // Some single precision VFP instructions may be executed on both NEON and
897 // VFP pipelines on A8.
898 let D = VFPNeonA8Domain;
901 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
902 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
903 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
904 // Some single precision VFP instructions may be executed on both NEON and
905 // VFP pipelines on A8.
906 let D = VFPNeonA8Domain;
909 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
910 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
911 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
912 // Some single precision VFP instructions may be executed on both NEON and
913 // VFP pipelines on A8.
914 let D = VFPNeonA8Domain;
917 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
918 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
919 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
920 // Some single precision VFP instructions may be executed on both NEON and
921 // VFP pipelines on A8.
922 let D = VFPNeonA8Domain;
925 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
926 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
927 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
929 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
930 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
931 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
933 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
934 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
935 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
937 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
938 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
939 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
941 // Fixed-Point to FP:
943 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
944 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
945 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
946 // Some single precision VFP instructions may be executed on both NEON and
947 // VFP pipelines on A8.
948 let D = VFPNeonA8Domain;
951 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
952 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
953 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
954 // Some single precision VFP instructions may be executed on both NEON and
955 // VFP pipelines on A8.
956 let D = VFPNeonA8Domain;
959 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
960 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
961 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
962 // Some single precision VFP instructions may be executed on both NEON and
963 // VFP pipelines on A8.
964 let D = VFPNeonA8Domain;
967 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
968 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
969 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
970 // Some single precision VFP instructions may be executed on both NEON and
971 // VFP pipelines on A8.
972 let D = VFPNeonA8Domain;
975 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
976 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
977 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
979 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
980 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
981 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
983 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
984 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
985 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
987 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
988 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
989 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
991 } // End of 'let Constraints = "$a = $dst" in'
993 //===----------------------------------------------------------------------===//
994 // FP Multiply-Accumulate Operations.
997 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
998 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
999 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1000 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1001 (f64 DPR:$Ddin)))]>,
1002 RegConstraint<"$Ddin = $Dd">,
1003 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1005 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1006 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1007 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1008 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1010 RegConstraint<"$Sdin = $Sd">,
1011 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1012 // Some single precision VFP instructions may be executed on both NEON and
1013 // VFP pipelines on A8.
1014 let D = VFPNeonA8Domain;
1017 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1018 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1019 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1020 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1021 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1022 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1024 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1025 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1026 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1027 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1028 (f64 DPR:$Ddin)))]>,
1029 RegConstraint<"$Ddin = $Dd">,
1030 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1032 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1033 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1034 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1035 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1037 RegConstraint<"$Sdin = $Sd">,
1038 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1039 // Some single precision VFP instructions may be executed on both NEON and
1040 // VFP pipelines on A8.
1041 let D = VFPNeonA8Domain;
1044 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1045 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1046 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1047 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1048 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1049 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1051 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1052 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1053 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1054 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1055 (f64 DPR:$Ddin)))]>,
1056 RegConstraint<"$Ddin = $Dd">,
1057 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1059 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1060 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1061 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1062 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1064 RegConstraint<"$Sdin = $Sd">,
1065 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1066 // Some single precision VFP instructions may be executed on both NEON and
1067 // VFP pipelines on A8.
1068 let D = VFPNeonA8Domain;
1071 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1072 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1073 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1074 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1075 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1076 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1078 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1079 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1080 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1081 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1082 (f64 DPR:$Ddin)))]>,
1083 RegConstraint<"$Ddin = $Dd">,
1084 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1086 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1087 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1088 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1089 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1090 RegConstraint<"$Sdin = $Sd">,
1091 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1092 // Some single precision VFP instructions may be executed on both NEON and
1093 // VFP pipelines on A8.
1094 let D = VFPNeonA8Domain;
1097 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1098 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1099 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1100 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1101 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1102 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1104 //===----------------------------------------------------------------------===//
1105 // Fused FP Multiply-Accumulate Operations.
1107 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1108 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1109 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1110 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1111 (f64 DPR:$Ddin)))]>,
1112 RegConstraint<"$Ddin = $Dd">,
1113 Requires<[HasVFP4,UseFusedMAC]>;
1115 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1116 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1117 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1118 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1120 RegConstraint<"$Sdin = $Sd">,
1121 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1122 // Some single precision VFP instructions may be executed on both NEON and
1126 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1127 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1128 Requires<[HasVFP4,UseFusedMAC]>;
1129 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1130 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1131 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1133 // Match @llvm.fma.* intrinsics
1134 // (fma x, y, z) -> (vfms z, x, y)
1135 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1136 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1137 Requires<[HasVFP4]>;
1138 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1139 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1140 Requires<[HasVFP4]>;
1142 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1143 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1144 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1145 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1146 (f64 DPR:$Ddin)))]>,
1147 RegConstraint<"$Ddin = $Dd">,
1148 Requires<[HasVFP4,UseFusedMAC]>;
1150 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1151 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1152 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1153 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1155 RegConstraint<"$Sdin = $Sd">,
1156 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1157 // Some single precision VFP instructions may be executed on both NEON and
1161 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1162 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1163 Requires<[HasVFP4,UseFusedMAC]>;
1164 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1165 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1166 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1168 // Match @llvm.fma.* intrinsics
1169 // (fma (fneg x), y, z) -> (vfms z, x, y)
1170 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1171 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1172 Requires<[HasVFP4]>;
1173 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1174 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1175 Requires<[HasVFP4]>;
1176 // (fma x, (fneg y), z) -> (vfms z, x, y)
1177 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1178 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1179 Requires<[HasVFP4]>;
1180 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1181 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1182 Requires<[HasVFP4]>;
1184 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1185 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1186 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1187 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1188 (f64 DPR:$Ddin)))]>,
1189 RegConstraint<"$Ddin = $Dd">,
1190 Requires<[HasVFP4,UseFusedMAC]>;
1192 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1193 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1194 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1195 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1197 RegConstraint<"$Sdin = $Sd">,
1198 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1199 // Some single precision VFP instructions may be executed on both NEON and
1203 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1204 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1205 Requires<[HasVFP4,UseFusedMAC]>;
1206 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1207 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1208 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1210 // Match @llvm.fma.* intrinsics
1211 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1212 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1213 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1214 Requires<[HasVFP4]>;
1215 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1216 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1217 Requires<[HasVFP4]>;
1218 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1219 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1220 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1221 Requires<[HasVFP4]>;
1222 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1223 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1224 Requires<[HasVFP4]>;
1226 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1227 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1228 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1229 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1230 (f64 DPR:$Ddin)))]>,
1231 RegConstraint<"$Ddin = $Dd">,
1232 Requires<[HasVFP4,UseFusedMAC]>;
1234 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1235 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1236 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1237 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1238 RegConstraint<"$Sdin = $Sd">,
1239 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1240 // Some single precision VFP instructions may be executed on both NEON and
1244 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1245 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1246 Requires<[HasVFP4,UseFusedMAC]>;
1247 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1248 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1249 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1251 // Match @llvm.fma.* intrinsics
1253 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1254 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1255 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1256 Requires<[HasVFP4]>;
1257 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1258 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1259 Requires<[HasVFP4]>;
1260 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1261 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1262 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1263 Requires<[HasVFP4]>;
1264 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1265 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1266 Requires<[HasVFP4]>;
1267 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1268 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1269 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1270 Requires<[HasVFP4]>;
1271 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1272 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1273 Requires<[HasVFP4]>;
1275 //===----------------------------------------------------------------------===//
1276 // FP Conditional moves.
1279 let neverHasSideEffects = 1 in {
1280 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1282 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1283 RegConstraint<"$Dn = $Dd">;
1285 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1287 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1288 RegConstraint<"$Sn = $Sd">;
1289 } // neverHasSideEffects
1291 //===----------------------------------------------------------------------===//
1292 // Move from VFP System Register to ARM core register.
1295 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1297 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1299 // Instruction operand.
1302 let Inst{27-20} = 0b11101111;
1303 let Inst{19-16} = opc19_16;
1304 let Inst{15-12} = Rt;
1305 let Inst{11-8} = 0b1010;
1307 let Inst{6-5} = 0b00;
1309 let Inst{3-0} = 0b0000;
1312 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1314 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1315 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1316 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1318 // Application level FPSCR -> GPR
1319 let hasSideEffects = 1, Uses = [FPSCR] in
1320 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1321 "vmrs", "\t$Rt, fpscr",
1322 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1324 // System level FPEXC, FPSID -> GPR
1325 let Uses = [FPSCR] in {
1326 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1327 "vmrs", "\t$Rt, fpexc", []>;
1328 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1329 "vmrs", "\t$Rt, fpsid", []>;
1330 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1331 "vmrs", "\t$Rt, mvfr0", []>;
1332 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1333 "vmrs", "\t$Rt, mvfr1", []>;
1336 //===----------------------------------------------------------------------===//
1337 // Move from ARM core register to VFP System Register.
1340 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1342 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1344 // Instruction operand.
1347 // Encode instruction operand.
1348 let Inst{15-12} = src;
1350 let Inst{27-20} = 0b11101110;
1351 let Inst{19-16} = opc19_16;
1352 let Inst{11-8} = 0b1010;
1357 let Defs = [FPSCR] in {
1358 // Application level GPR -> FPSCR
1359 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1360 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1361 // System level GPR -> FPEXC
1362 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1363 "vmsr", "\tfpexc, $src", []>;
1364 // System level GPR -> FPSID
1365 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1366 "vmsr", "\tfpsid, $src", []>;
1369 //===----------------------------------------------------------------------===//
1373 // Materialize FP immediates. VFP3 only.
1374 let isReMaterializable = 1 in {
1375 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1376 VFPMiscFrm, IIC_fpUNA64,
1377 "vmov", ".f64\t$Dd, $imm",
1378 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1382 let Inst{27-23} = 0b11101;
1383 let Inst{22} = Dd{4};
1384 let Inst{21-20} = 0b11;
1385 let Inst{19-16} = imm{7-4};
1386 let Inst{15-12} = Dd{3-0};
1387 let Inst{11-9} = 0b101;
1388 let Inst{8} = 1; // Double precision.
1389 let Inst{7-4} = 0b0000;
1390 let Inst{3-0} = imm{3-0};
1393 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1394 VFPMiscFrm, IIC_fpUNA32,
1395 "vmov", ".f32\t$Sd, $imm",
1396 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1400 let Inst{27-23} = 0b11101;
1401 let Inst{22} = Sd{0};
1402 let Inst{21-20} = 0b11;
1403 let Inst{19-16} = imm{7-4};
1404 let Inst{15-12} = Sd{4-1};
1405 let Inst{11-9} = 0b101;
1406 let Inst{8} = 0; // Single precision.
1407 let Inst{7-4} = 0b0000;
1408 let Inst{3-0} = imm{3-0};
1412 //===----------------------------------------------------------------------===//
1413 // Assembler aliases.
1415 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1416 // support them all, but supporting at least some of the basics is
1417 // good to be friendly.
1418 def : VFP2MnemonicAlias<"flds", "vldr">;
1419 def : VFP2MnemonicAlias<"fldd", "vldr">;
1420 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1421 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1422 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1423 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1424 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1425 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1426 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1427 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1428 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1429 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1430 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1431 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1432 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1433 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1434 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1435 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1436 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1437 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1438 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1439 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1440 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1441 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1442 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1443 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1444 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1445 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1446 def : VFP2MnemonicAlias<"fsts", "vstr">;
1447 def : VFP2MnemonicAlias<"fstd", "vstr">;
1448 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1449 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1450 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1451 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1452 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1453 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1454 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1455 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1456 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1457 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1459 // Be friendly and accept the old form of zero-compare
1460 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1461 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1464 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1465 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1466 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1467 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1468 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1469 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1470 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1471 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1472 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1474 // No need for the size suffix on VSQRT. It's implied by the register classes.
1475 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1476 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1478 // VLDR/VSTR accept an optional type suffix.
1479 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1480 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1481 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1482 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1483 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1484 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1485 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1486 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1488 // VMOV can accept optional 32-bit or less data type suffix suffix.
1489 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1490 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1491 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1492 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1493 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1494 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1495 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1496 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1497 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1498 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1499 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1500 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1502 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1503 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1504 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1505 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1507 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1509 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1510 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;