1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
39 let DecoderMethod = "DecodeVFPfpImm";
42 def vfp_f64imm : Operand<f64>,
43 PatLeaf<(f64 fpimm), [{
44 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
46 let PrintMethod = "printVFPf64ImmOperand";
47 let DecoderMethod = "DecodeVFPfpImm";
51 //===----------------------------------------------------------------------===//
52 // Load / store Instructions.
55 let canFoldAsLoad = 1, isReMaterializable = 1 in {
57 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
58 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
59 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
61 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
62 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
63 [(set SPR:$Sd, (load addrmode5:$addr))]> {
64 // Some single precision VFP instructions may be executed on both NEON and VFP
66 let D = VFPNeonDomain;
69 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
71 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
72 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
73 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
75 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
76 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
77 [(store SPR:$Sd, addrmode5:$addr)]> {
78 // Some single precision VFP instructions may be executed on both NEON and VFP
80 let D = VFPNeonDomain;
83 //===----------------------------------------------------------------------===//
84 // Load / store multiple Instructions.
87 multiclass vfp_ldst_mult<string asm, bit L_bit,
88 InstrItinClass itin, InstrItinClass itin_upd> {
91 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
93 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
94 let Inst{24-23} = 0b01; // Increment After
95 let Inst{21} = 0; // No writeback
99 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
101 IndexModeUpd, itin_upd,
102 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
103 let Inst{24-23} = 0b01; // Increment After
104 let Inst{21} = 1; // Writeback
105 let Inst{20} = L_bit;
108 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
110 IndexModeUpd, itin_upd,
111 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
112 let Inst{24-23} = 0b10; // Decrement Before
113 let Inst{21} = 1; // Writeback
114 let Inst{20} = L_bit;
119 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
121 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
122 let Inst{24-23} = 0b01; // Increment After
123 let Inst{21} = 0; // No writeback
124 let Inst{20} = L_bit;
126 // Some single precision VFP instructions may be executed on both NEON and
128 let D = VFPNeonDomain;
131 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
133 IndexModeUpd, itin_upd,
134 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
135 let Inst{24-23} = 0b01; // Increment After
136 let Inst{21} = 1; // Writeback
137 let Inst{20} = L_bit;
139 // Some single precision VFP instructions may be executed on both NEON and
141 let D = VFPNeonDomain;
144 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
146 IndexModeUpd, itin_upd,
147 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
148 let Inst{24-23} = 0b10; // Decrement Before
149 let Inst{21} = 1; // Writeback
150 let Inst{20} = L_bit;
152 // Some single precision VFP instructions may be executed on both NEON and
154 let D = VFPNeonDomain;
158 let neverHasSideEffects = 1 in {
160 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
161 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
163 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
164 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
166 } // neverHasSideEffects
168 def : MnemonicAlias<"vldm", "vldmia">;
169 def : MnemonicAlias<"vstm", "vstmia">;
171 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
173 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
175 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
177 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
180 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
182 //===----------------------------------------------------------------------===//
183 // FP Binary Operations.
186 def VADDD : ADbI<0b11100, 0b11, 0, 0,
187 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
188 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
189 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
191 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
192 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
193 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
194 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
195 // Some single precision VFP instructions may be executed on both NEON and
196 // VFP pipelines on A8.
197 let D = VFPNeonA8Domain;
200 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
201 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
202 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
203 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
205 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
206 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
207 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
208 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
209 // Some single precision VFP instructions may be executed on both NEON and
210 // VFP pipelines on A8.
211 let D = VFPNeonA8Domain;
214 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
215 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
216 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
217 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
219 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
220 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
221 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
222 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
224 def VMULD : ADbI<0b11100, 0b10, 0, 0,
225 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
226 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
227 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
229 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
230 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
231 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
232 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
233 // Some single precision VFP instructions may be executed on both NEON and
234 // VFP pipelines on A8.
235 let D = VFPNeonA8Domain;
238 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
239 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
240 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
241 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
243 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
244 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
245 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
246 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
247 // Some single precision VFP instructions may be executed on both NEON and
248 // VFP pipelines on A8.
249 let D = VFPNeonA8Domain;
252 // Match reassociated forms only if not sign dependent rounding.
253 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
254 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
255 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
256 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
258 // These are encoded as unary instructions.
259 let Defs = [FPSCR] in {
260 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
261 (outs), (ins DPR:$Dd, DPR:$Dm),
262 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
263 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
265 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
266 (outs), (ins SPR:$Sd, SPR:$Sm),
267 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
268 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
269 // Some single precision VFP instructions may be executed on both NEON and
270 // VFP pipelines on A8.
271 let D = VFPNeonA8Domain;
274 // FIXME: Verify encoding after integrated assembler is working.
275 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
276 (outs), (ins DPR:$Dd, DPR:$Dm),
277 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
278 [/* For disassembly only; pattern left blank */]>;
280 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
281 (outs), (ins SPR:$Sd, SPR:$Sm),
282 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
283 [/* For disassembly only; pattern left blank */]> {
284 // Some single precision VFP instructions may be executed on both NEON and
285 // VFP pipelines on A8.
286 let D = VFPNeonA8Domain;
290 //===----------------------------------------------------------------------===//
291 // FP Unary Operations.
294 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
295 (outs DPR:$Dd), (ins DPR:$Dm),
296 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
297 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
299 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
300 (outs SPR:$Sd), (ins SPR:$Sm),
301 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
302 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
303 // Some single precision VFP instructions may be executed on both NEON and
304 // VFP pipelines on A8.
305 let D = VFPNeonA8Domain;
308 let Defs = [FPSCR] in {
309 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
310 (outs), (ins DPR:$Dd),
311 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
312 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
313 let Inst{3-0} = 0b0000;
317 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
318 (outs), (ins SPR:$Sd),
319 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
320 [(arm_cmpfp0 SPR:$Sd)]> {
321 let Inst{3-0} = 0b0000;
324 // Some single precision VFP instructions may be executed on both NEON and
325 // VFP pipelines on A8.
326 let D = VFPNeonA8Domain;
329 // FIXME: Verify encoding after integrated assembler is working.
330 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
331 (outs), (ins DPR:$Dd),
332 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
333 [/* For disassembly only; pattern left blank */]> {
334 let Inst{3-0} = 0b0000;
338 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
339 (outs), (ins SPR:$Sd),
340 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
341 [/* For disassembly only; pattern left blank */]> {
342 let Inst{3-0} = 0b0000;
345 // Some single precision VFP instructions may be executed on both NEON and
346 // VFP pipelines on A8.
347 let D = VFPNeonA8Domain;
351 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
352 (outs DPR:$Dd), (ins SPR:$Sm),
353 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
354 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
355 // Instruction operands.
359 // Encode instruction operands.
360 let Inst{3-0} = Sm{4-1};
362 let Inst{15-12} = Dd{3-0};
363 let Inst{22} = Dd{4};
366 // Special case encoding: bits 11-8 is 0b1011.
367 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
368 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
369 [(set SPR:$Sd, (fround DPR:$Dm))]> {
370 // Instruction operands.
374 // Encode instruction operands.
375 let Inst{3-0} = Dm{3-0};
377 let Inst{15-12} = Sd{4-1};
378 let Inst{22} = Sd{0};
380 let Inst{27-23} = 0b11101;
381 let Inst{21-16} = 0b110111;
382 let Inst{11-8} = 0b1011;
383 let Inst{7-6} = 0b11;
387 // Between half-precision and single-precision. For disassembly only.
389 // FIXME: Verify encoding after integrated assembler is working.
390 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
391 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
392 [/* For disassembly only; pattern left blank */]>;
394 def : ARMPat<(f32_to_f16 SPR:$a),
395 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
397 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
398 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
399 [/* For disassembly only; pattern left blank */]>;
401 def : ARMPat<(f16_to_f32 GPR:$a),
402 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
404 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
405 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
406 [/* For disassembly only; pattern left blank */]>;
408 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
409 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
410 [/* For disassembly only; pattern left blank */]>;
412 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
413 (outs DPR:$Dd), (ins DPR:$Dm),
414 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
415 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
417 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
418 (outs SPR:$Sd), (ins SPR:$Sm),
419 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
420 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
421 // Some single precision VFP instructions may be executed on both NEON and
422 // VFP pipelines on A8.
423 let D = VFPNeonA8Domain;
426 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
427 (outs DPR:$Dd), (ins DPR:$Dm),
428 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
429 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
431 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
432 (outs SPR:$Sd), (ins SPR:$Sm),
433 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
434 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
436 let neverHasSideEffects = 1 in {
437 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
438 (outs DPR:$Dd), (ins DPR:$Dm),
439 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
441 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
442 (outs SPR:$Sd), (ins SPR:$Sm),
443 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
444 } // neverHasSideEffects
446 //===----------------------------------------------------------------------===//
447 // FP <-> GPR Copies. Int <-> FP Conversions.
450 def VMOVRS : AVConv2I<0b11100001, 0b1010,
451 (outs GPR:$Rt), (ins SPR:$Sn),
452 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
453 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
454 // Instruction operands.
458 // Encode instruction operands.
459 let Inst{19-16} = Sn{4-1};
461 let Inst{15-12} = Rt;
463 let Inst{6-5} = 0b00;
464 let Inst{3-0} = 0b0000;
466 // Some single precision VFP instructions may be executed on both NEON and VFP
468 let D = VFPNeonDomain;
471 def VMOVSR : AVConv4I<0b11100000, 0b1010,
472 (outs SPR:$Sn), (ins GPR:$Rt),
473 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
474 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
475 // Instruction operands.
479 // Encode instruction operands.
480 let Inst{19-16} = Sn{4-1};
482 let Inst{15-12} = Rt;
484 let Inst{6-5} = 0b00;
485 let Inst{3-0} = 0b0000;
487 // Some single precision VFP instructions may be executed on both NEON and VFP
489 let D = VFPNeonDomain;
492 let neverHasSideEffects = 1 in {
493 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
494 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
495 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
496 [/* FIXME: Can't write pattern for multiple result instr*/]> {
497 // Instruction operands.
502 // Encode instruction operands.
503 let Inst{3-0} = Dm{3-0};
505 let Inst{15-12} = Rt;
506 let Inst{19-16} = Rt2;
508 let Inst{7-6} = 0b00;
510 // Some single precision VFP instructions may be executed on both NEON and VFP
512 let D = VFPNeonDomain;
515 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
516 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
517 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
518 [/* For disassembly only; pattern left blank */]> {
523 // Encode instruction operands.
524 let Inst{3-0} = src1{3-0};
525 let Inst{5} = src1{4};
526 let Inst{15-12} = Rt;
527 let Inst{19-16} = Rt2;
529 let Inst{7-6} = 0b00;
531 // Some single precision VFP instructions may be executed on both NEON and VFP
533 let D = VFPNeonDomain;
534 let DecoderMethod = "DecodeVMOVRRS";
536 } // neverHasSideEffects
541 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
542 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
543 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
544 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
545 // Instruction operands.
550 // Encode instruction operands.
551 let Inst{3-0} = Dm{3-0};
553 let Inst{15-12} = Rt;
554 let Inst{19-16} = Rt2;
556 let Inst{7-6} = 0b00;
558 // Some single precision VFP instructions may be executed on both NEON and VFP
560 let D = VFPNeonDomain;
563 let neverHasSideEffects = 1 in
564 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
565 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
566 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
567 [/* For disassembly only; pattern left blank */]> {
568 // Instruction operands.
573 // Encode instruction operands.
574 let Inst{3-0} = dst1{3-0};
575 let Inst{5} = dst1{4};
576 let Inst{15-12} = src1;
577 let Inst{19-16} = src2;
579 let Inst{7-6} = 0b00;
581 // Some single precision VFP instructions may be executed on both NEON and VFP
583 let D = VFPNeonDomain;
585 let DecoderMethod = "DecodeVMOVSRR";
591 // FMRX: SPR system reg -> GPR
593 // FMXR: GPR -> VFP system reg
598 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
599 bits<4> opcod4, dag oops, dag iops,
600 InstrItinClass itin, string opc, string asm,
602 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
604 // Instruction operands.
608 // Encode instruction operands.
609 let Inst{3-0} = Sm{4-1};
611 let Inst{15-12} = Dd{3-0};
612 let Inst{22} = Dd{4};
615 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
616 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
617 string opc, string asm, list<dag> pattern>
618 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
620 // Instruction operands.
624 // Encode instruction operands.
625 let Inst{3-0} = Sm{4-1};
627 let Inst{15-12} = Sd{4-1};
628 let Inst{22} = Sd{0};
631 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
632 (outs DPR:$Dd), (ins SPR:$Sm),
633 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
634 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
635 let Inst{7} = 1; // s32
638 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
639 (outs SPR:$Sd),(ins SPR:$Sm),
640 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
641 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
642 let Inst{7} = 1; // s32
644 // Some single precision VFP instructions may be executed on both NEON and
645 // VFP pipelines on A8.
646 let D = VFPNeonA8Domain;
649 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
650 (outs DPR:$Dd), (ins SPR:$Sm),
651 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
652 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
653 let Inst{7} = 0; // u32
656 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
657 (outs SPR:$Sd), (ins SPR:$Sm),
658 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
659 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
660 let Inst{7} = 0; // u32
662 // Some single precision VFP instructions may be executed on both NEON and
663 // VFP pipelines on A8.
664 let D = VFPNeonA8Domain;
669 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
670 bits<4> opcod4, dag oops, dag iops,
671 InstrItinClass itin, string opc, string asm,
673 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
675 // Instruction operands.
679 // Encode instruction operands.
680 let Inst{3-0} = Dm{3-0};
682 let Inst{15-12} = Sd{4-1};
683 let Inst{22} = Sd{0};
686 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
687 bits<4> opcod4, dag oops, dag iops,
688 InstrItinClass itin, string opc, string asm,
690 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
692 // Instruction operands.
696 // Encode instruction operands.
697 let Inst{3-0} = Sm{4-1};
699 let Inst{15-12} = Sd{4-1};
700 let Inst{22} = Sd{0};
703 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
704 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
705 (outs SPR:$Sd), (ins DPR:$Dm),
706 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
707 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
708 let Inst{7} = 1; // Z bit
711 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
712 (outs SPR:$Sd), (ins SPR:$Sm),
713 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
714 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
715 let Inst{7} = 1; // Z bit
717 // Some single precision VFP instructions may be executed on both NEON and
718 // VFP pipelines on A8.
719 let D = VFPNeonA8Domain;
722 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
723 (outs SPR:$Sd), (ins DPR:$Dm),
724 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
725 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
726 let Inst{7} = 1; // Z bit
729 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
730 (outs SPR:$Sd), (ins SPR:$Sm),
731 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
732 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
733 let Inst{7} = 1; // Z bit
735 // Some single precision VFP instructions may be executed on both NEON and
736 // VFP pipelines on A8.
737 let D = VFPNeonA8Domain;
740 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
741 let Uses = [FPSCR] in {
742 // FIXME: Verify encoding after integrated assembler is working.
743 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
744 (outs SPR:$Sd), (ins DPR:$Dm),
745 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
746 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
747 let Inst{7} = 0; // Z bit
750 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
751 (outs SPR:$Sd), (ins SPR:$Sm),
752 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
753 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
754 let Inst{7} = 0; // Z bit
757 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
758 (outs SPR:$Sd), (ins DPR:$Dm),
759 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
760 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
761 let Inst{7} = 0; // Z bit
764 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
765 (outs SPR:$Sd), (ins SPR:$Sm),
766 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
767 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
768 let Inst{7} = 0; // Z bit
772 // Convert between floating-point and fixed-point
773 // Data type for fixed-point naming convention:
774 // S16 (U=0, sx=0) -> SH
775 // U16 (U=1, sx=0) -> UH
776 // S32 (U=0, sx=1) -> SL
777 // U32 (U=1, sx=1) -> UL
779 // FIXME: Marking these as codegen only seems wrong. They are real
781 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
783 // FP to Fixed-Point:
785 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
786 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
787 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
788 [/* For disassembly only; pattern left blank */]> {
789 // Some single precision VFP instructions may be executed on both NEON and
790 // VFP pipelines on A8.
791 let D = VFPNeonA8Domain;
794 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
795 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
796 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
797 [/* For disassembly only; pattern left blank */]> {
798 // Some single precision VFP instructions may be executed on both NEON and
799 // VFP pipelines on A8.
800 let D = VFPNeonA8Domain;
803 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
804 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
805 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
806 [/* For disassembly only; pattern left blank */]> {
807 // Some single precision VFP instructions may be executed on both NEON and
808 // VFP pipelines on A8.
809 let D = VFPNeonA8Domain;
812 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
813 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
814 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
815 [/* For disassembly only; pattern left blank */]> {
816 // Some single precision VFP instructions may be executed on both NEON and
817 // VFP pipelines on A8.
818 let D = VFPNeonA8Domain;
821 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
822 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
823 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
824 [/* For disassembly only; pattern left blank */]>;
826 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
827 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
828 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
829 [/* For disassembly only; pattern left blank */]>;
831 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
832 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
833 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
834 [/* For disassembly only; pattern left blank */]>;
836 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
837 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
838 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
839 [/* For disassembly only; pattern left blank */]>;
841 // Fixed-Point to FP:
843 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
844 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
845 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
846 [/* For disassembly only; pattern left blank */]> {
847 // Some single precision VFP instructions may be executed on both NEON and
848 // VFP pipelines on A8.
849 let D = VFPNeonA8Domain;
852 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
853 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
854 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
855 [/* For disassembly only; pattern left blank */]> {
856 // Some single precision VFP instructions may be executed on both NEON and
857 // VFP pipelines on A8.
858 let D = VFPNeonA8Domain;
861 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
862 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
863 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
864 [/* For disassembly only; pattern left blank */]> {
865 // Some single precision VFP instructions may be executed on both NEON and
866 // VFP pipelines on A8.
867 let D = VFPNeonA8Domain;
870 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
871 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
872 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
873 [/* For disassembly only; pattern left blank */]> {
874 // Some single precision VFP instructions may be executed on both NEON and
875 // VFP pipelines on A8.
876 let D = VFPNeonA8Domain;
879 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
880 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
881 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
882 [/* For disassembly only; pattern left blank */]>;
884 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
885 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
886 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
887 [/* For disassembly only; pattern left blank */]>;
889 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
890 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
891 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
892 [/* For disassembly only; pattern left blank */]>;
894 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
895 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
896 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
897 [/* For disassembly only; pattern left blank */]>;
899 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
901 //===----------------------------------------------------------------------===//
902 // FP Multiply-Accumulate Operations.
905 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
906 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
907 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
908 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
910 RegConstraint<"$Ddin = $Dd">,
911 Requires<[HasVFP2,UseFPVMLx]>;
913 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
914 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
915 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
916 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
918 RegConstraint<"$Sdin = $Sd">,
919 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
920 // Some single precision VFP instructions may be executed on both NEON and
921 // VFP pipelines on A8.
922 let D = VFPNeonA8Domain;
925 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
926 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
927 Requires<[HasVFP2,UseFPVMLx]>;
928 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
929 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
930 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>;
932 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
933 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
934 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
935 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
937 RegConstraint<"$Ddin = $Dd">,
938 Requires<[HasVFP2,UseFPVMLx]>;
940 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
941 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
942 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
943 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
945 RegConstraint<"$Sdin = $Sd">,
946 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
947 // Some single precision VFP instructions may be executed on both NEON and
948 // VFP pipelines on A8.
949 let D = VFPNeonA8Domain;
952 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
953 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
954 Requires<[HasVFP2,UseFPVMLx]>;
955 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
956 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
957 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
959 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
960 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
961 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
962 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
964 RegConstraint<"$Ddin = $Dd">,
965 Requires<[HasVFP2,UseFPVMLx]>;
967 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
968 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
969 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
970 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
972 RegConstraint<"$Sdin = $Sd">,
973 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
974 // Some single precision VFP instructions may be executed on both NEON and
975 // VFP pipelines on A8.
976 let D = VFPNeonA8Domain;
979 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
980 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
981 Requires<[HasVFP2,UseFPVMLx]>;
982 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
983 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
984 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
986 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
987 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
988 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
989 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
991 RegConstraint<"$Ddin = $Dd">,
992 Requires<[HasVFP2,UseFPVMLx]>;
994 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
995 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
996 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
997 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
998 RegConstraint<"$Sdin = $Sd">,
999 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
1000 // Some single precision VFP instructions may be executed on both NEON and
1001 // VFP pipelines on A8.
1002 let D = VFPNeonA8Domain;
1005 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1006 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1007 Requires<[HasVFP2,UseFPVMLx]>;
1008 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1009 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1010 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
1013 //===----------------------------------------------------------------------===//
1014 // FP Conditional moves.
1017 let neverHasSideEffects = 1 in {
1018 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1020 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1021 RegConstraint<"$Dn = $Dd">;
1023 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1025 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1026 RegConstraint<"$Sn = $Sd">;
1027 } // neverHasSideEffects
1029 //===----------------------------------------------------------------------===//
1030 // Move from VFP System Register to ARM core register.
1033 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1035 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1037 // Instruction operand.
1040 let Inst{27-20} = 0b11101111;
1041 let Inst{19-16} = opc19_16;
1042 let Inst{15-12} = Rt;
1043 let Inst{11-8} = 0b1010;
1045 let Inst{6-5} = 0b00;
1047 let Inst{3-0} = 0b0000;
1050 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1052 let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
1053 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1054 "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
1056 // Application level FPSCR -> GPR
1057 let hasSideEffects = 1, Uses = [FPSCR] in
1058 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1059 "vmrs", "\t$Rt, fpscr",
1060 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1062 // System level FPEXC, FPSID -> GPR
1063 let Uses = [FPSCR] in {
1064 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1065 "vmrs", "\t$Rt, fpexc", []>;
1066 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1067 "vmrs", "\t$Rt, fpsid", []>;
1070 //===----------------------------------------------------------------------===//
1071 // Move from ARM core register to VFP System Register.
1074 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1076 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1078 // Instruction operand.
1081 // Encode instruction operand.
1082 let Inst{15-12} = src;
1084 let Inst{27-20} = 0b11101110;
1085 let Inst{19-16} = opc19_16;
1086 let Inst{11-8} = 0b1010;
1091 let Defs = [FPSCR] in {
1092 // Application level GPR -> FPSCR
1093 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1094 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1095 // System level GPR -> FPEXC
1096 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1097 "vmsr", "\tfpexc, $src", []>;
1098 // System level GPR -> FPSID
1099 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1100 "vmsr", "\tfpsid, $src", []>;
1103 //===----------------------------------------------------------------------===//
1107 // Materialize FP immediates. VFP3 only.
1108 let isReMaterializable = 1 in {
1109 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1110 VFPMiscFrm, IIC_fpUNA64,
1111 "vmov", ".f64\t$Dd, $imm",
1112 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1113 // Instruction operands.
1117 // Encode instruction operands.
1118 let Inst{15-12} = Dd{3-0};
1119 let Inst{22} = Dd{4};
1120 let Inst{19} = imm{31}; // The immediate is handled as a float.
1121 let Inst{18-16} = imm{25-23};
1122 let Inst{3-0} = imm{22-19};
1124 // Encode remaining instruction bits.
1125 let Inst{27-23} = 0b11101;
1126 let Inst{21-20} = 0b11;
1127 let Inst{11-9} = 0b101;
1128 let Inst{8} = 1; // Double precision.
1129 let Inst{7-4} = 0b0000;
1132 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1133 VFPMiscFrm, IIC_fpUNA32,
1134 "vmov", ".f32\t$Sd, $imm",
1135 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1136 // Instruction operands.
1140 // Encode instruction operands.
1141 let Inst{15-12} = Sd{4-1};
1142 let Inst{22} = Sd{0};
1143 let Inst{19} = imm{31}; // The immediate is handled as a float.
1144 let Inst{18-16} = imm{25-23};
1145 let Inst{3-0} = imm{22-19};
1147 // Encode remaining instruction bits.
1148 let Inst{27-23} = 0b11101;
1149 let Inst{21-20} = 0b11;
1150 let Inst{11-9} = 0b101;
1151 let Inst{8} = 0; // Single precision.
1152 let Inst{7-4} = 0b0000;