1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
33 //===----------------------------------------------------------------------===//
34 // Operand Definitions.
38 def vfp_f32imm : Operand<f32>,
39 PatLeaf<(f32 fpimm), [{
40 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
42 let PrintMethod = "printVFPf32ImmOperand";
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
49 let PrintMethod = "printVFPf64ImmOperand";
53 //===----------------------------------------------------------------------===//
54 // Load / store Instructions.
57 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
58 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
60 [(set DPR:$dst, (load addrmode5:$addr))]>;
62 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
63 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
64 [(set SPR:$dst, (load addrmode5:$addr))]>;
67 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
68 IIC_fpStore64, "vstr", ".64\t$src, $addr",
69 [(store DPR:$src, addrmode5:$addr)]>;
71 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
72 IIC_fpStore32, "vstr", ".32\t$src, $addr",
73 [(store SPR:$src, addrmode5:$addr)]>;
75 //===----------------------------------------------------------------------===//
76 // Load / store multiple Instructions.
79 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
80 def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
81 variable_ops), IIC_fpLoadm,
82 "vldm${addr:submode}${p}\t${addr:base}, $wb",
87 def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
88 variable_ops), IIC_fpLoadm,
89 "vldm${addr:submode}${p}\t${addr:base}, $wb",
93 } // mayLoad, hasExtraDefRegAllocReq
95 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
96 def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
97 variable_ops), IIC_fpStorem,
98 "vstm${addr:submode}${p}\t${addr:base}, $wb",
103 def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
104 variable_ops), IIC_fpStorem,
105 "vstm${addr:submode}${p}\t${addr:base}, $wb",
109 } // mayStore, hasExtraSrcRegAllocReq
111 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
113 //===----------------------------------------------------------------------===//
114 // FP Binary Operations.
117 def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
118 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
119 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
121 def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
122 IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
123 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
125 // These are encoded as unary instructions.
126 let Defs = [FPSCR] in {
127 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$a, DPR:$b),
128 IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
129 [(arm_cmpfp DPR:$a, DPR:$b)]>;
131 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
132 IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
133 [/* For disassembly only; pattern left blank */]>;
135 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins SPR:$a, SPR:$b),
136 IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
137 [(arm_cmpfp SPR:$a, SPR:$b)]>;
139 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
140 IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
141 [/* For disassembly only; pattern left blank */]>;
144 def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
145 IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
146 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
148 def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
149 IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
150 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
152 def VMULD : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
153 IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
154 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
156 def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
157 IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
158 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
160 def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
161 IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
162 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
164 def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
165 IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
166 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
168 // Match reassociated forms only if not sign dependent rounding.
169 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
170 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
171 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
172 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
175 def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
176 IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
177 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
179 def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
180 IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
181 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
183 //===----------------------------------------------------------------------===//
184 // FP Unary Operations.
187 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
188 IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
189 [(set DPR:$dst, (fabs DPR:$a))]>;
191 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
192 IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
193 [(set SPR:$dst, (fabs SPR:$a))]>;
195 let Defs = [FPSCR] in {
196 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a),
197 IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
198 [(arm_cmpfp0 DPR:$a)]>;
200 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
201 IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
202 [/* For disassembly only; pattern left blank */]>;
204 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins SPR:$a),
205 IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
206 [(arm_cmpfp0 SPR:$a)]>;
208 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
209 IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
210 [/* For disassembly only; pattern left blank */]>;
213 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, (outs DPR:$dst), (ins SPR:$a),
214 IIC_fpCVTDS, "vcvt", ".f64.f32\t$dst, $a",
215 [(set DPR:$dst, (fextend SPR:$a))]>;
217 // Special case encoding: bits 11-8 is 0b1011.
218 def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
219 IIC_fpCVTSD, "vcvt", ".f32.f64\t$dst, $a",
220 [(set SPR:$dst, (fround DPR:$a))]> {
221 let Inst{27-23} = 0b11101;
222 let Inst{21-16} = 0b110111;
223 let Inst{11-8} = 0b1011;
224 let Inst{7-6} = 0b11;
228 // Between half-precision and single-precision. For disassembly only.
230 def VCVTBSH : ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
231 /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f32.f16\t$dst, $a",
232 [/* For disassembly only; pattern left blank */]>;
234 def VCVTBHS : ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
235 /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f16.f32\t$dst, $a",
236 [/* For disassembly only; pattern left blank */]>;
238 def VCVTTSH : ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
239 /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f32.f16\t$dst, $a",
240 [/* For disassembly only; pattern left blank */]>;
242 def VCVTTHS : ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
243 /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f16.f32\t$dst, $a",
244 [/* For disassembly only; pattern left blank */]>;
246 let neverHasSideEffects = 1 in {
247 def VMOVD: ADuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
248 IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
250 def VMOVS: ASuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
251 IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
252 } // neverHasSideEffects
254 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
255 IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
256 [(set DPR:$dst, (fneg DPR:$a))]>;
258 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
259 IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
260 [(set SPR:$dst, (fneg SPR:$a))]>;
262 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
263 IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
264 [(set DPR:$dst, (fsqrt DPR:$a))]>;
266 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
267 IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
268 [(set SPR:$dst, (fsqrt SPR:$a))]>;
270 //===----------------------------------------------------------------------===//
271 // FP <-> GPR Copies. Int <-> FP Conversions.
274 def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
275 IIC_VMOVSI, "vmov", "\t$dst, $src",
276 [(set GPR:$dst, (bitconvert SPR:$src))]>;
278 def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
279 IIC_VMOVIS, "vmov", "\t$dst, $src",
280 [(set SPR:$dst, (bitconvert GPR:$src))]>;
282 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
283 (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
284 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src",
285 [/* FIXME: Can't write pattern for multiple result instr*/]> {
286 let Inst{7-6} = 0b00;
289 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
290 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
291 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
292 [/* For disassembly only; pattern left blank */]> {
293 let Inst{7-6} = 0b00;
299 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
300 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
301 IIC_VMOVID, "vmov", "\t$dst, $src1, $src2",
302 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
303 let Inst{7-6} = 0b00;
306 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
307 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
308 IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
309 [/* For disassembly only; pattern left blank */]> {
310 let Inst{7-6} = 0b00;
316 // FMRX : SPR system reg -> GPR
320 // FMXR: GPR -> VFP Sstem reg
325 def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
326 (outs DPR:$dst), (ins SPR:$a),
327 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
328 [(set DPR:$dst, (arm_sitof SPR:$a))]> {
329 let Inst{7} = 1; // s32
332 def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
333 (outs SPR:$dst),(ins SPR:$a),
334 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
335 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
336 let Inst{7} = 1; // s32
339 def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
340 (outs DPR:$dst), (ins SPR:$a),
341 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
342 [(set DPR:$dst, (arm_uitof SPR:$a))]> {
343 let Inst{7} = 0; // u32
346 def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
347 (outs SPR:$dst), (ins SPR:$a),
348 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
349 [(set SPR:$dst, (arm_uitof SPR:$a))]> {
350 let Inst{7} = 0; // u32
354 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
356 def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
357 (outs SPR:$dst), (ins DPR:$a),
358 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
359 [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
360 let Inst{7} = 1; // Z bit
363 def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
364 (outs SPR:$dst), (ins SPR:$a),
365 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
366 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
367 let Inst{7} = 1; // Z bit
370 def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
371 (outs SPR:$dst), (ins DPR:$a),
372 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
373 [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
374 let Inst{7} = 1; // Z bit
377 def VTOUIZS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
378 (outs SPR:$dst), (ins SPR:$a),
379 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
380 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
381 let Inst{7} = 1; // Z bit
384 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
385 // For disassembly only.
387 def VTOSIRD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
388 (outs SPR:$dst), (ins DPR:$a),
389 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$dst, $a",
390 [/* For disassembly only; pattern left blank */]> {
391 let Inst{7} = 0; // Z bit
394 def VTOSIRS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
395 (outs SPR:$dst), (ins SPR:$a),
396 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$dst, $a",
397 [/* For disassembly only; pattern left blank */]> {
398 let Inst{7} = 0; // Z bit
401 def VTOUIRD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
402 (outs SPR:$dst), (ins DPR:$a),
403 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$dst, $a",
404 [/* For disassembly only; pattern left blank */]> {
405 let Inst{7} = 0; // Z bit
408 def VTOUIRS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
409 (outs SPR:$dst), (ins SPR:$a),
410 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$dst, $a",
411 [/* For disassembly only; pattern left blank */]> {
412 let Inst{7} = 0; // Z bit
415 // Convert between floating-point and fixed-point
416 // Data type for fixed-point naming convention:
417 // S16 (U=0, sx=0) -> SH
418 // U16 (U=1, sx=0) -> UH
419 // S32 (U=0, sx=1) -> SL
420 // U32 (U=1, sx=1) -> UL
422 let Constraints = "$a = $dst" in {
424 // FP to Fixed-Point:
426 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
427 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
428 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
429 [/* For disassembly only; pattern left blank */]>;
431 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
432 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
433 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
434 [/* For disassembly only; pattern left blank */]>;
436 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
437 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
438 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
439 [/* For disassembly only; pattern left blank */]>;
441 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
442 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
443 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
444 [/* For disassembly only; pattern left blank */]>;
446 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
447 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
448 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
449 [/* For disassembly only; pattern left blank */]>;
451 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
452 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
453 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
454 [/* For disassembly only; pattern left blank */]>;
456 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
457 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
458 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
459 [/* For disassembly only; pattern left blank */]>;
461 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
462 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
463 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
464 [/* For disassembly only; pattern left blank */]>;
466 // Fixed-Point to FP:
468 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
469 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
470 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
471 [/* For disassembly only; pattern left blank */]>;
473 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
474 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
475 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
476 [/* For disassembly only; pattern left blank */]>;
478 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
479 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
480 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
481 [/* For disassembly only; pattern left blank */]>;
483 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
484 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
485 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
486 [/* For disassembly only; pattern left blank */]>;
488 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
489 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
490 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
491 [/* For disassembly only; pattern left blank */]>;
493 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
494 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
495 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
496 [/* For disassembly only; pattern left blank */]>;
498 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
499 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
500 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
501 [/* For disassembly only; pattern left blank */]>;
503 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
504 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
505 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
506 [/* For disassembly only; pattern left blank */]>;
508 } // End of 'let Constraints = "$src = $dst" in'
510 //===----------------------------------------------------------------------===//
511 // FP FMA Operations.
514 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
515 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
516 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
517 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
518 RegConstraint<"$dstin = $dst">;
520 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
521 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
522 IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
523 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
524 RegConstraint<"$dstin = $dst">;
526 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
527 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
528 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
529 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
530 RegConstraint<"$dstin = $dst">;
532 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
533 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
534 IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
535 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
536 RegConstraint<"$dstin = $dst">;
538 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
539 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
540 IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
541 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
542 RegConstraint<"$dstin = $dst">;
544 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
545 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
546 IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
547 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
548 RegConstraint<"$dstin = $dst">;
550 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
551 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
552 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
553 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
555 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
556 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
557 IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
558 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
559 RegConstraint<"$dstin = $dst">;
561 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
562 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
563 IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
564 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
565 RegConstraint<"$dstin = $dst">;
567 //===----------------------------------------------------------------------===//
568 // FP Conditional moves.
571 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
572 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
573 IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
574 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
575 RegConstraint<"$false = $dst">;
577 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
578 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
579 IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
580 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
581 RegConstraint<"$false = $dst">;
583 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
584 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
585 IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
586 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
587 RegConstraint<"$false = $dst">;
589 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
590 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
591 IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
592 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
593 RegConstraint<"$false = $dst">;
596 //===----------------------------------------------------------------------===//
600 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
602 let Defs = [CPSR], Uses = [FPSCR] in
603 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
604 "\tapsr_nzcv, fpscr",
606 let Inst{27-20} = 0b11101111;
607 let Inst{19-16} = 0b0001;
608 let Inst{15-12} = 0b1111;
609 let Inst{11-8} = 0b1010;
614 // FPSCR <-> GPR (for disassembly only)
616 let Uses = [FPSCR] in {
617 def VMRS : VFPAI<(outs GPR:$dst), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
619 [/* For disassembly only; pattern left blank */]> {
620 let Inst{27-20} = 0b11101111;
621 let Inst{19-16} = 0b0001;
622 let Inst{11-8} = 0b1010;
628 let Defs = [FPSCR] in {
629 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT, "vmsr",
631 [/* For disassembly only; pattern left blank */]> {
632 let Inst{27-20} = 0b11101110;
633 let Inst{19-16} = 0b0001;
634 let Inst{11-8} = 0b1010;
640 // Materialize FP immediates. VFP3 only.
641 let isReMaterializable = 1 in {
642 def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
643 VFPMiscFrm, IIC_VMOVImm,
644 "vmov", ".f64\t$dst, $imm",
645 [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
646 let Inst{27-23} = 0b11101;
647 let Inst{21-20} = 0b11;
648 let Inst{11-9} = 0b101;
650 let Inst{7-4} = 0b0000;
653 def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
654 VFPMiscFrm, IIC_VMOVImm,
655 "vmov", ".f32\t$dst, $imm",
656 [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
657 let Inst{27-23} = 0b11101;
658 let Inst{21-20} = 0b11;
659 let Inst{11-9} = 0b101;
661 let Inst{7-4} = 0b0000;