1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
227 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
229 // These instruction are deprecated so we don't want them to get selected.
230 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
235 let Inst{24-23} = 0b01; // Increment After
236 let Inst{21} = 0; // No writeback
237 let Inst{20} = L_bit;
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
242 let Inst{24-23} = 0b01; // Increment After
243 let Inst{21} = 1; // Writeback
244 let Inst{20} = L_bit;
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
249 let Inst{24-23} = 0b10; // Decrement Before
251 let Inst{20} = L_bit;
255 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
256 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
258 //===----------------------------------------------------------------------===//
259 // FP Binary Operations.
262 let TwoOperandAliasConstraint = "$Dn = $Dd" in
263 def VADDD : ADbI<0b11100, 0b11, 0, 0,
264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
268 let TwoOperandAliasConstraint = "$Sn = $Sd" in
269 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
273 // Some single precision VFP instructions may be executed on both NEON and
274 // VFP pipelines on A8.
275 let D = VFPNeonA8Domain;
278 let TwoOperandAliasConstraint = "$Dn = $Dd" in
279 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
284 let TwoOperandAliasConstraint = "$Sn = $Sd" in
285 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
289 // Some single precision VFP instructions may be executed on both NEON and
290 // VFP pipelines on A8.
291 let D = VFPNeonA8Domain;
294 let TwoOperandAliasConstraint = "$Dn = $Dd" in
295 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
300 let TwoOperandAliasConstraint = "$Sn = $Sd" in
301 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
306 let TwoOperandAliasConstraint = "$Dn = $Dd" in
307 def VMULD : ADbI<0b11100, 0b10, 0, 0,
308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
312 let TwoOperandAliasConstraint = "$Sn = $Sd" in
313 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
327 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
331 // Some single precision VFP instructions may be executed on both NEON and
332 // VFP pipelines on A8.
333 let D = VFPNeonA8Domain;
336 multiclass vsel_inst<string op, bits<2> opc, int CC> {
337 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
338 Uses = [CPSR], AddedComplexity = 4 in {
339 def S : ASbInp<0b11100, opc, 0,
340 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
341 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
342 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
343 Requires<[HasFPARMv8]>;
345 def D : ADbInp<0b11100, opc, 0,
346 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
347 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
348 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
349 Requires<[HasFPARMv8]>;
353 // The CC constants here match ARMCC::CondCodes.
354 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
355 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
356 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
357 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
359 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
360 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
361 def S : ASbInp<0b11101, 0b00, opc,
362 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
363 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
364 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
365 Requires<[HasFPARMv8]>;
367 def D : ADbInp<0b11101, 0b00, opc,
368 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
369 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
370 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
371 Requires<[HasFPARMv8]>;
375 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
376 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
378 // Match reassociated forms only if not sign dependent rounding.
379 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
380 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
381 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
382 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
384 // These are encoded as unary instructions.
385 let Defs = [FPSCR_NZCV] in {
386 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
387 (outs), (ins DPR:$Dd, DPR:$Dm),
388 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
389 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
391 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
392 (outs), (ins SPR:$Sd, SPR:$Sm),
393 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
394 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
395 // Some single precision VFP instructions may be executed on both NEON and
396 // VFP pipelines on A8.
397 let D = VFPNeonA8Domain;
400 // FIXME: Verify encoding after integrated assembler is working.
401 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
402 (outs), (ins DPR:$Dd, DPR:$Dm),
403 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
404 [/* For disassembly only; pattern left blank */]>;
406 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
407 (outs), (ins SPR:$Sd, SPR:$Sm),
408 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
409 [/* For disassembly only; pattern left blank */]> {
410 // Some single precision VFP instructions may be executed on both NEON and
411 // VFP pipelines on A8.
412 let D = VFPNeonA8Domain;
414 } // Defs = [FPSCR_NZCV]
416 //===----------------------------------------------------------------------===//
417 // FP Unary Operations.
420 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
421 (outs DPR:$Dd), (ins DPR:$Dm),
422 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
423 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
425 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
426 (outs SPR:$Sd), (ins SPR:$Sm),
427 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
428 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
429 // Some single precision VFP instructions may be executed on both NEON and
430 // VFP pipelines on A8.
431 let D = VFPNeonA8Domain;
434 let Defs = [FPSCR_NZCV] in {
435 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
436 (outs), (ins DPR:$Dd),
437 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
438 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
439 let Inst{3-0} = 0b0000;
443 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
444 (outs), (ins SPR:$Sd),
445 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
446 [(arm_cmpfp0 SPR:$Sd)]> {
447 let Inst{3-0} = 0b0000;
450 // Some single precision VFP instructions may be executed on both NEON and
451 // VFP pipelines on A8.
452 let D = VFPNeonA8Domain;
455 // FIXME: Verify encoding after integrated assembler is working.
456 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
457 (outs), (ins DPR:$Dd),
458 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
459 [/* For disassembly only; pattern left blank */]> {
460 let Inst{3-0} = 0b0000;
464 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
465 (outs), (ins SPR:$Sd),
466 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
467 [/* For disassembly only; pattern left blank */]> {
468 let Inst{3-0} = 0b0000;
471 // Some single precision VFP instructions may be executed on both NEON and
472 // VFP pipelines on A8.
473 let D = VFPNeonA8Domain;
475 } // Defs = [FPSCR_NZCV]
477 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
478 (outs DPR:$Dd), (ins SPR:$Sm),
479 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
480 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
481 // Instruction operands.
485 // Encode instruction operands.
486 let Inst{3-0} = Sm{4-1};
488 let Inst{15-12} = Dd{3-0};
489 let Inst{22} = Dd{4};
492 // Special case encoding: bits 11-8 is 0b1011.
493 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
494 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
495 [(set SPR:$Sd, (fround DPR:$Dm))]> {
496 // Instruction operands.
500 // Encode instruction operands.
501 let Inst{3-0} = Dm{3-0};
503 let Inst{15-12} = Sd{4-1};
504 let Inst{22} = Sd{0};
506 let Inst{27-23} = 0b11101;
507 let Inst{21-16} = 0b110111;
508 let Inst{11-8} = 0b1011;
509 let Inst{7-6} = 0b11;
513 // Between half, single and double-precision. For disassembly only.
515 // FIXME: Verify encoding after integrated assembler is working.
516 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
517 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
518 [/* For disassembly only; pattern left blank */]>;
520 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
521 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
522 [/* For disassembly only; pattern left blank */]>;
524 def : Pat<(f32_to_f16 SPR:$a),
525 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
527 def : Pat<(f16_to_f32 GPR:$a),
528 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
530 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
531 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
532 [/* For disassembly only; pattern left blank */]>;
534 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
535 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
536 [/* For disassembly only; pattern left blank */]>;
538 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
539 (outs DPR:$Dd), (ins SPR:$Sm),
540 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
541 []>, Requires<[HasFPARMv8]> {
542 // Instruction operands.
545 // Encode instruction operands.
546 let Inst{3-0} = Sm{4-1};
550 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
551 (outs SPR:$Sd), (ins DPR:$Dm),
552 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
553 []>, Requires<[HasFPARMv8]> {
554 // Instruction operands.
558 // Encode instruction operands.
559 let Inst{3-0} = Dm{3-0};
561 let Inst{15-12} = Sd{4-1};
562 let Inst{22} = Sd{0};
565 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
566 (outs DPR:$Dd), (ins SPR:$Sm),
567 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
568 []>, Requires<[HasFPARMv8]> {
569 // Instruction operands.
572 // Encode instruction operands.
573 let Inst{3-0} = Sm{4-1};
577 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
578 (outs SPR:$Sd), (ins DPR:$Dm),
579 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
580 []>, Requires<[HasFPARMv8]> {
581 // Instruction operands.
585 // Encode instruction operands.
586 let Inst{15-12} = Sd{4-1};
587 let Inst{22} = Sd{0};
588 let Inst{3-0} = Dm{3-0};
592 multiclass vcvt_inst<string opc, bits<2> rm> {
593 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
594 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
595 (outs SPR:$Sd), (ins SPR:$Sm),
596 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
597 []>, Requires<[HasFPARMv8]> {
598 let Inst{17-16} = rm;
601 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
602 (outs SPR:$Sd), (ins SPR:$Sm),
603 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
604 []>, Requires<[HasFPARMv8]> {
605 let Inst{17-16} = rm;
608 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
609 (outs SPR:$Sd), (ins DPR:$Dm),
610 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
611 []>, Requires<[HasFPARMv8]> {
614 let Inst{17-16} = rm;
616 // Encode instruction operands
617 let Inst{3-0} = Dm{3-0};
622 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
623 (outs SPR:$Sd), (ins DPR:$Dm),
624 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
625 []>, Requires<[HasFPARMv8]> {
628 let Inst{17-16} = rm;
630 // Encode instruction operands
631 let Inst{3-0} = Dm{3-0};
638 defm VCVTA : vcvt_inst<"a", 0b00>;
639 defm VCVTN : vcvt_inst<"n", 0b01>;
640 defm VCVTP : vcvt_inst<"p", 0b10>;
641 defm VCVTM : vcvt_inst<"m", 0b11>;
643 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
644 (outs DPR:$Dd), (ins DPR:$Dm),
645 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
646 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
648 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
649 (outs SPR:$Sd), (ins SPR:$Sm),
650 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
651 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
652 // Some single precision VFP instructions may be executed on both NEON and
653 // VFP pipelines on A8.
654 let D = VFPNeonA8Domain;
657 multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
658 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
659 (outs SPR:$Sd), (ins SPR:$Sm),
660 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
661 []>, Requires<[HasFPARMv8]> {
665 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
666 (outs DPR:$Dd), (ins DPR:$Dm),
667 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
668 []>, Requires<[HasFPARMv8]> {
673 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
674 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>;
675 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
676 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>;
679 defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
680 defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
681 defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
683 multiclass vrint_inst_anpm<string opc, bits<2> rm> {
684 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
685 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
686 (outs SPR:$Sd), (ins SPR:$Sm),
687 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
688 []>, Requires<[HasFPARMv8]> {
689 let Inst{17-16} = rm;
691 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
692 (outs DPR:$Dd), (ins DPR:$Dm),
693 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
694 []>, Requires<[HasFPARMv8]> {
695 let Inst{17-16} = rm;
699 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
700 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>;
701 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
702 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
705 defm VRINTA : vrint_inst_anpm<"a", 0b00>;
706 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
707 defm VRINTP : vrint_inst_anpm<"p", 0b10>;
708 defm VRINTM : vrint_inst_anpm<"m", 0b11>;
710 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
711 (outs DPR:$Dd), (ins DPR:$Dm),
712 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
713 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
715 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
716 (outs SPR:$Sd), (ins SPR:$Sm),
717 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
718 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
720 let neverHasSideEffects = 1 in {
721 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
722 (outs DPR:$Dd), (ins DPR:$Dm),
723 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
725 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
726 (outs SPR:$Sd), (ins SPR:$Sm),
727 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
728 } // neverHasSideEffects
730 //===----------------------------------------------------------------------===//
731 // FP <-> GPR Copies. Int <-> FP Conversions.
734 def VMOVRS : AVConv2I<0b11100001, 0b1010,
735 (outs GPR:$Rt), (ins SPR:$Sn),
736 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
737 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
738 // Instruction operands.
742 // Encode instruction operands.
743 let Inst{19-16} = Sn{4-1};
745 let Inst{15-12} = Rt;
747 let Inst{6-5} = 0b00;
748 let Inst{3-0} = 0b0000;
750 // Some single precision VFP instructions may be executed on both NEON and VFP
752 let D = VFPNeonDomain;
755 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
756 def VMOVSR : AVConv4I<0b11100000, 0b1010,
757 (outs SPR:$Sn), (ins GPR:$Rt),
758 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
759 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
760 Requires<[HasVFP2, UseVMOVSR]> {
761 // Instruction operands.
765 // Encode instruction operands.
766 let Inst{19-16} = Sn{4-1};
768 let Inst{15-12} = Rt;
770 let Inst{6-5} = 0b00;
771 let Inst{3-0} = 0b0000;
773 // Some single precision VFP instructions may be executed on both NEON and VFP
775 let D = VFPNeonDomain;
778 let neverHasSideEffects = 1 in {
779 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
780 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
781 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
782 [/* FIXME: Can't write pattern for multiple result instr*/]> {
783 // Instruction operands.
788 // Encode instruction operands.
789 let Inst{3-0} = Dm{3-0};
791 let Inst{15-12} = Rt;
792 let Inst{19-16} = Rt2;
794 let Inst{7-6} = 0b00;
796 // Some single precision VFP instructions may be executed on both NEON and VFP
798 let D = VFPNeonDomain;
801 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
802 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
803 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
804 [/* For disassembly only; pattern left blank */]> {
809 // Encode instruction operands.
810 let Inst{3-0} = src1{4-1};
811 let Inst{5} = src1{0};
812 let Inst{15-12} = Rt;
813 let Inst{19-16} = Rt2;
815 let Inst{7-6} = 0b00;
817 // Some single precision VFP instructions may be executed on both NEON and VFP
819 let D = VFPNeonDomain;
820 let DecoderMethod = "DecodeVMOVRRS";
822 } // neverHasSideEffects
827 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
828 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
829 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
830 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
831 // Instruction operands.
836 // Encode instruction operands.
837 let Inst{3-0} = Dm{3-0};
839 let Inst{15-12} = Rt;
840 let Inst{19-16} = Rt2;
842 let Inst{7-6} = 0b00;
844 // Some single precision VFP instructions may be executed on both NEON and VFP
846 let D = VFPNeonDomain;
849 let neverHasSideEffects = 1 in
850 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
851 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
852 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
853 [/* For disassembly only; pattern left blank */]> {
854 // Instruction operands.
859 // Encode instruction operands.
860 let Inst{3-0} = dst1{4-1};
861 let Inst{5} = dst1{0};
862 let Inst{15-12} = src1;
863 let Inst{19-16} = src2;
865 let Inst{7-6} = 0b00;
867 // Some single precision VFP instructions may be executed on both NEON and VFP
869 let D = VFPNeonDomain;
871 let DecoderMethod = "DecodeVMOVSRR";
877 // FMRX: SPR system reg -> GPR
879 // FMXR: GPR -> VFP system reg
884 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
885 bits<4> opcod4, dag oops, dag iops,
886 InstrItinClass itin, string opc, string asm,
888 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
890 // Instruction operands.
894 // Encode instruction operands.
895 let Inst{3-0} = Sm{4-1};
897 let Inst{15-12} = Dd{3-0};
898 let Inst{22} = Dd{4};
901 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
902 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
903 string opc, string asm, list<dag> pattern>
904 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
906 // Instruction operands.
910 // Encode instruction operands.
911 let Inst{3-0} = Sm{4-1};
913 let Inst{15-12} = Sd{4-1};
914 let Inst{22} = Sd{0};
917 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
918 (outs DPR:$Dd), (ins SPR:$Sm),
919 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
920 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
921 let Inst{7} = 1; // s32
924 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
925 (outs SPR:$Sd),(ins SPR:$Sm),
926 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
927 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
928 let Inst{7} = 1; // s32
930 // Some single precision VFP instructions may be executed on both NEON and
931 // VFP pipelines on A8.
932 let D = VFPNeonA8Domain;
935 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
936 (outs DPR:$Dd), (ins SPR:$Sm),
937 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
938 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
939 let Inst{7} = 0; // u32
942 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
943 (outs SPR:$Sd), (ins SPR:$Sm),
944 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
945 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
946 let Inst{7} = 0; // u32
948 // Some single precision VFP instructions may be executed on both NEON and
949 // VFP pipelines on A8.
950 let D = VFPNeonA8Domain;
955 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
956 bits<4> opcod4, dag oops, dag iops,
957 InstrItinClass itin, string opc, string asm,
959 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
961 // Instruction operands.
965 // Encode instruction operands.
966 let Inst{3-0} = Dm{3-0};
968 let Inst{15-12} = Sd{4-1};
969 let Inst{22} = Sd{0};
972 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
973 bits<4> opcod4, dag oops, dag iops,
974 InstrItinClass itin, string opc, string asm,
976 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
978 // Instruction operands.
982 // Encode instruction operands.
983 let Inst{3-0} = Sm{4-1};
985 let Inst{15-12} = Sd{4-1};
986 let Inst{22} = Sd{0};
989 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
990 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
991 (outs SPR:$Sd), (ins DPR:$Dm),
992 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
993 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
994 let Inst{7} = 1; // Z bit
997 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
998 (outs SPR:$Sd), (ins SPR:$Sm),
999 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1000 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
1001 let Inst{7} = 1; // Z bit
1003 // Some single precision VFP instructions may be executed on both NEON and
1004 // VFP pipelines on A8.
1005 let D = VFPNeonA8Domain;
1008 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1009 (outs SPR:$Sd), (ins DPR:$Dm),
1010 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1011 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
1012 let Inst{7} = 1; // Z bit
1015 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1016 (outs SPR:$Sd), (ins SPR:$Sm),
1017 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1018 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
1019 let Inst{7} = 1; // Z bit
1021 // Some single precision VFP instructions may be executed on both NEON and
1022 // VFP pipelines on A8.
1023 let D = VFPNeonA8Domain;
1026 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1027 let Uses = [FPSCR] in {
1028 // FIXME: Verify encoding after integrated assembler is working.
1029 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1030 (outs SPR:$Sd), (ins DPR:$Dm),
1031 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1032 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1033 let Inst{7} = 0; // Z bit
1036 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1037 (outs SPR:$Sd), (ins SPR:$Sm),
1038 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1039 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1040 let Inst{7} = 0; // Z bit
1043 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1044 (outs SPR:$Sd), (ins DPR:$Dm),
1045 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1046 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1047 let Inst{7} = 0; // Z bit
1050 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1051 (outs SPR:$Sd), (ins SPR:$Sm),
1052 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1053 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1054 let Inst{7} = 0; // Z bit
1058 // Convert between floating-point and fixed-point
1059 // Data type for fixed-point naming convention:
1060 // S16 (U=0, sx=0) -> SH
1061 // U16 (U=1, sx=0) -> UH
1062 // S32 (U=0, sx=1) -> SL
1063 // U32 (U=1, sx=1) -> UL
1065 let Constraints = "$a = $dst" in {
1067 // FP to Fixed-Point:
1069 // Single Precision register
1070 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1071 bit op5, dag oops, dag iops, InstrItinClass itin,
1072 string opc, string asm, list<dag> pattern>
1073 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1074 Sched<[WriteCvtFP]> {
1076 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1077 let Inst{22} = dst{0};
1078 let Inst{15-12} = dst{4-1};
1081 // Double Precision register
1082 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1083 bit op5, dag oops, dag iops, InstrItinClass itin,
1084 string opc, string asm, list<dag> pattern>
1085 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1086 Sched<[WriteCvtFP]> {
1088 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1089 let Inst{22} = dst{4};
1090 let Inst{15-12} = dst{3-0};
1093 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1094 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1095 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1096 // Some single precision VFP instructions may be executed on both NEON and
1097 // VFP pipelines on A8.
1098 let D = VFPNeonA8Domain;
1101 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1102 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1103 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1104 // Some single precision VFP instructions may be executed on both NEON and
1105 // VFP pipelines on A8.
1106 let D = VFPNeonA8Domain;
1109 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1110 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1111 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1112 // Some single precision VFP instructions may be executed on both NEON and
1113 // VFP pipelines on A8.
1114 let D = VFPNeonA8Domain;
1117 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1118 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1119 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1120 // Some single precision VFP instructions may be executed on both NEON and
1121 // VFP pipelines on A8.
1122 let D = VFPNeonA8Domain;
1125 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1126 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1127 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1129 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1130 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1131 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1133 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1134 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1135 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1137 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1138 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1139 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1141 // Fixed-Point to FP:
1143 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1144 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1145 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1146 // Some single precision VFP instructions may be executed on both NEON and
1147 // VFP pipelines on A8.
1148 let D = VFPNeonA8Domain;
1151 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1152 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1153 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1154 // Some single precision VFP instructions may be executed on both NEON and
1155 // VFP pipelines on A8.
1156 let D = VFPNeonA8Domain;
1159 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1160 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1161 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1162 // Some single precision VFP instructions may be executed on both NEON and
1163 // VFP pipelines on A8.
1164 let D = VFPNeonA8Domain;
1167 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1168 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1169 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1170 // Some single precision VFP instructions may be executed on both NEON and
1171 // VFP pipelines on A8.
1172 let D = VFPNeonA8Domain;
1175 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1176 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1177 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1179 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1180 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1181 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1183 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1184 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1185 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1187 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1188 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1189 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1191 } // End of 'let Constraints = "$a = $dst" in'
1193 //===----------------------------------------------------------------------===//
1194 // FP Multiply-Accumulate Operations.
1197 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1198 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1199 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1200 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1201 (f64 DPR:$Ddin)))]>,
1202 RegConstraint<"$Ddin = $Dd">,
1203 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1205 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1206 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1207 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1208 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1210 RegConstraint<"$Sdin = $Sd">,
1211 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1212 // Some single precision VFP instructions may be executed on both NEON and
1213 // VFP pipelines on A8.
1214 let D = VFPNeonA8Domain;
1217 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1218 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1219 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1220 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1221 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1222 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1224 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1225 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1226 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1227 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1228 (f64 DPR:$Ddin)))]>,
1229 RegConstraint<"$Ddin = $Dd">,
1230 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1232 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1233 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1234 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1235 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1237 RegConstraint<"$Sdin = $Sd">,
1238 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1239 // Some single precision VFP instructions may be executed on both NEON and
1240 // VFP pipelines on A8.
1241 let D = VFPNeonA8Domain;
1244 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1245 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1246 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1247 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1248 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1249 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1251 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1252 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1253 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1254 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1255 (f64 DPR:$Ddin)))]>,
1256 RegConstraint<"$Ddin = $Dd">,
1257 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1259 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1260 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1261 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1262 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1264 RegConstraint<"$Sdin = $Sd">,
1265 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1266 // Some single precision VFP instructions may be executed on both NEON and
1267 // VFP pipelines on A8.
1268 let D = VFPNeonA8Domain;
1271 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1272 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1273 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1274 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1275 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1276 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1278 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1279 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1280 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1281 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1282 (f64 DPR:$Ddin)))]>,
1283 RegConstraint<"$Ddin = $Dd">,
1284 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1286 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1287 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1288 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1289 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1290 RegConstraint<"$Sdin = $Sd">,
1291 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1292 // Some single precision VFP instructions may be executed on both NEON and
1293 // VFP pipelines on A8.
1294 let D = VFPNeonA8Domain;
1297 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1298 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1299 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1300 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1301 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1302 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1304 //===----------------------------------------------------------------------===//
1305 // Fused FP Multiply-Accumulate Operations.
1307 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1308 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1309 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1310 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1311 (f64 DPR:$Ddin)))]>,
1312 RegConstraint<"$Ddin = $Dd">,
1313 Requires<[HasVFP4,UseFusedMAC]>;
1315 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1316 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1317 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1318 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1320 RegConstraint<"$Sdin = $Sd">,
1321 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1322 // Some single precision VFP instructions may be executed on both NEON and
1326 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1327 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1328 Requires<[HasVFP4,UseFusedMAC]>;
1329 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1330 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1331 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1333 // Match @llvm.fma.* intrinsics
1334 // (fma x, y, z) -> (vfms z, x, y)
1335 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1336 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1337 Requires<[HasVFP4]>;
1338 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1339 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1340 Requires<[HasVFP4]>;
1342 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1343 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1344 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1345 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1346 (f64 DPR:$Ddin)))]>,
1347 RegConstraint<"$Ddin = $Dd">,
1348 Requires<[HasVFP4,UseFusedMAC]>;
1350 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1351 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1352 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1353 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1355 RegConstraint<"$Sdin = $Sd">,
1356 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1357 // Some single precision VFP instructions may be executed on both NEON and
1361 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1362 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1363 Requires<[HasVFP4,UseFusedMAC]>;
1364 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1365 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1366 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1368 // Match @llvm.fma.* intrinsics
1369 // (fma (fneg x), y, z) -> (vfms z, x, y)
1370 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1371 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1372 Requires<[HasVFP4]>;
1373 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1374 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1375 Requires<[HasVFP4]>;
1376 // (fma x, (fneg y), z) -> (vfms z, x, y)
1377 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1378 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1379 Requires<[HasVFP4]>;
1380 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1381 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1382 Requires<[HasVFP4]>;
1384 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1385 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1386 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1387 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1388 (f64 DPR:$Ddin)))]>,
1389 RegConstraint<"$Ddin = $Dd">,
1390 Requires<[HasVFP4,UseFusedMAC]>;
1392 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1393 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1394 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1395 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1397 RegConstraint<"$Sdin = $Sd">,
1398 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1399 // Some single precision VFP instructions may be executed on both NEON and
1403 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1404 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1405 Requires<[HasVFP4,UseFusedMAC]>;
1406 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1407 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1408 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1410 // Match @llvm.fma.* intrinsics
1411 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1412 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1413 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1414 Requires<[HasVFP4]>;
1415 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1416 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1417 Requires<[HasVFP4]>;
1418 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1419 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1420 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1421 Requires<[HasVFP4]>;
1422 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1423 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1424 Requires<[HasVFP4]>;
1426 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1427 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1428 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1429 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1430 (f64 DPR:$Ddin)))]>,
1431 RegConstraint<"$Ddin = $Dd">,
1432 Requires<[HasVFP4,UseFusedMAC]>;
1434 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1435 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1436 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1437 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1438 RegConstraint<"$Sdin = $Sd">,
1439 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1440 // Some single precision VFP instructions may be executed on both NEON and
1444 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1445 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1446 Requires<[HasVFP4,UseFusedMAC]>;
1447 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1448 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1449 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1451 // Match @llvm.fma.* intrinsics
1453 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1454 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1455 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1456 Requires<[HasVFP4]>;
1457 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1458 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1459 Requires<[HasVFP4]>;
1460 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1461 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1462 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1463 Requires<[HasVFP4]>;
1464 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1465 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1466 Requires<[HasVFP4]>;
1467 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1468 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1469 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1470 Requires<[HasVFP4]>;
1471 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1472 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1473 Requires<[HasVFP4]>;
1475 //===----------------------------------------------------------------------===//
1476 // FP Conditional moves.
1479 let neverHasSideEffects = 1 in {
1480 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1482 [(set (f64 DPR:$Dd),
1483 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1484 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2]>;
1486 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1488 [(set (f32 SPR:$Sd),
1489 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1490 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1491 } // neverHasSideEffects
1493 //===----------------------------------------------------------------------===//
1494 // Move from VFP System Register to ARM core register.
1497 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1499 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1501 // Instruction operand.
1504 let Inst{27-20} = 0b11101111;
1505 let Inst{19-16} = opc19_16;
1506 let Inst{15-12} = Rt;
1507 let Inst{11-8} = 0b1010;
1509 let Inst{6-5} = 0b00;
1511 let Inst{3-0} = 0b0000;
1514 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1516 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1517 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1518 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1520 // Application level FPSCR -> GPR
1521 let hasSideEffects = 1, Uses = [FPSCR] in
1522 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1523 "vmrs", "\t$Rt, fpscr",
1524 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1526 // System level FPEXC, FPSID -> GPR
1527 let Uses = [FPSCR] in {
1528 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1529 "vmrs", "\t$Rt, fpexc", []>;
1530 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1531 "vmrs", "\t$Rt, fpsid", []>;
1532 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1533 "vmrs", "\t$Rt, mvfr0", []>;
1534 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1535 "vmrs", "\t$Rt, mvfr1", []>;
1536 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1537 "vmrs", "\t$Rt, fpinst", []>;
1538 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1539 "vmrs", "\t$Rt, fpinst2", []>;
1542 //===----------------------------------------------------------------------===//
1543 // Move from ARM core register to VFP System Register.
1546 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1548 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1550 // Instruction operand.
1553 // Encode instruction operand.
1554 let Inst{15-12} = src;
1556 let Inst{27-20} = 0b11101110;
1557 let Inst{19-16} = opc19_16;
1558 let Inst{11-8} = 0b1010;
1563 let Defs = [FPSCR] in {
1564 // Application level GPR -> FPSCR
1565 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1566 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1567 // System level GPR -> FPEXC
1568 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1569 "vmsr", "\tfpexc, $src", []>;
1570 // System level GPR -> FPSID
1571 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1572 "vmsr", "\tfpsid, $src", []>;
1574 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1575 "vmsr", "\tfpinst, $src", []>;
1576 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1577 "vmsr", "\tfpinst2, $src", []>;
1580 //===----------------------------------------------------------------------===//
1584 // Materialize FP immediates. VFP3 only.
1585 let isReMaterializable = 1 in {
1586 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1587 VFPMiscFrm, IIC_fpUNA64,
1588 "vmov", ".f64\t$Dd, $imm",
1589 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1593 let Inst{27-23} = 0b11101;
1594 let Inst{22} = Dd{4};
1595 let Inst{21-20} = 0b11;
1596 let Inst{19-16} = imm{7-4};
1597 let Inst{15-12} = Dd{3-0};
1598 let Inst{11-9} = 0b101;
1599 let Inst{8} = 1; // Double precision.
1600 let Inst{7-4} = 0b0000;
1601 let Inst{3-0} = imm{3-0};
1604 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1605 VFPMiscFrm, IIC_fpUNA32,
1606 "vmov", ".f32\t$Sd, $imm",
1607 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1611 let Inst{27-23} = 0b11101;
1612 let Inst{22} = Sd{0};
1613 let Inst{21-20} = 0b11;
1614 let Inst{19-16} = imm{7-4};
1615 let Inst{15-12} = Sd{4-1};
1616 let Inst{11-9} = 0b101;
1617 let Inst{8} = 0; // Single precision.
1618 let Inst{7-4} = 0b0000;
1619 let Inst{3-0} = imm{3-0};
1623 //===----------------------------------------------------------------------===//
1624 // Assembler aliases.
1626 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1627 // support them all, but supporting at least some of the basics is
1628 // good to be friendly.
1629 def : VFP2MnemonicAlias<"flds", "vldr">;
1630 def : VFP2MnemonicAlias<"fldd", "vldr">;
1631 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1632 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1633 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1634 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1635 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1636 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1637 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1638 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1639 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1640 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1641 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1642 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1643 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1644 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1645 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1646 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1647 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1648 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1649 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1650 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1651 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1652 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1653 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1654 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1655 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1656 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1657 def : VFP2MnemonicAlias<"fsts", "vstr">;
1658 def : VFP2MnemonicAlias<"fstd", "vstr">;
1659 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1660 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1661 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1662 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1663 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1664 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1665 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1666 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1667 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1668 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1670 // Be friendly and accept the old form of zero-compare
1671 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1672 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1675 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1676 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1677 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1678 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1679 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1680 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1681 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1682 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1683 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1685 // No need for the size suffix on VSQRT. It's implied by the register classes.
1686 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1687 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1689 // VLDR/VSTR accept an optional type suffix.
1690 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1691 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1692 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1693 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1694 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1695 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1696 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1697 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1699 // VMOV can accept optional 32-bit or less data type suffix suffix.
1700 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1701 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1702 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1703 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1704 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1705 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1706 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1707 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1708 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1709 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1710 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1711 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1713 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1714 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1715 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1716 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1718 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1720 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1721 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;