1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
65 //===----------------------------------------------------------------------===//
66 // Load / store Instructions.
69 let canFoldAsLoad = 1, isReMaterializable = 1 in {
71 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
72 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
73 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
75 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
76 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
77 [(set SPR:$Sd, (load addrmode5:$addr))]> {
78 // Some single precision VFP instructions may be executed on both NEON and VFP
80 let D = VFPNeonDomain;
83 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
85 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
86 IIC_fpStore64, "vstr", "\t$Dd, $addr",
87 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
89 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
90 IIC_fpStore32, "vstr", "\t$Sd, $addr",
91 [(store SPR:$Sd, addrmode5:$addr)]> {
92 // Some single precision VFP instructions may be executed on both NEON and VFP
94 let D = VFPNeonDomain;
97 //===----------------------------------------------------------------------===//
98 // Load / store multiple Instructions.
101 multiclass vfp_ldst_mult<string asm, bit L_bit,
102 InstrItinClass itin, InstrItinClass itin_upd> {
105 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
107 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
108 let Inst{24-23} = 0b01; // Increment After
109 let Inst{21} = 0; // No writeback
110 let Inst{20} = L_bit;
113 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
115 IndexModeUpd, itin_upd,
116 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
117 let Inst{24-23} = 0b01; // Increment After
118 let Inst{21} = 1; // Writeback
119 let Inst{20} = L_bit;
122 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
124 IndexModeUpd, itin_upd,
125 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
126 let Inst{24-23} = 0b10; // Decrement Before
127 let Inst{21} = 1; // Writeback
128 let Inst{20} = L_bit;
133 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
135 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
136 let Inst{24-23} = 0b01; // Increment After
137 let Inst{21} = 0; // No writeback
138 let Inst{20} = L_bit;
140 // Some single precision VFP instructions may be executed on both NEON and
142 let D = VFPNeonDomain;
145 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
147 IndexModeUpd, itin_upd,
148 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
149 let Inst{24-23} = 0b01; // Increment After
150 let Inst{21} = 1; // Writeback
151 let Inst{20} = L_bit;
153 // Some single precision VFP instructions may be executed on both NEON and
155 let D = VFPNeonDomain;
158 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
160 IndexModeUpd, itin_upd,
161 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
162 let Inst{24-23} = 0b10; // Decrement Before
163 let Inst{21} = 1; // Writeback
164 let Inst{20} = L_bit;
166 // Some single precision VFP instructions may be executed on both NEON and
168 let D = VFPNeonDomain;
172 let neverHasSideEffects = 1 in {
174 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
175 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
177 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
178 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
180 } // neverHasSideEffects
182 def : MnemonicAlias<"vldm", "vldmia">;
183 def : MnemonicAlias<"vstm", "vstmia">;
185 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
187 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
189 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
191 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
194 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
196 //===----------------------------------------------------------------------===//
197 // FP Binary Operations.
200 def VADDD : ADbI<0b11100, 0b11, 0, 0,
201 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
202 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
203 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
205 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
206 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
207 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
208 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
209 // Some single precision VFP instructions may be executed on both NEON and
210 // VFP pipelines on A8.
211 let D = VFPNeonA8Domain;
214 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
215 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
216 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
217 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
219 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
220 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
221 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
222 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
223 // Some single precision VFP instructions may be executed on both NEON and
224 // VFP pipelines on A8.
225 let D = VFPNeonA8Domain;
228 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
229 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
230 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
231 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
233 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
234 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
235 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
236 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
238 def VMULD : ADbI<0b11100, 0b10, 0, 0,
239 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
240 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
241 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
243 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
244 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
245 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
246 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
247 // Some single precision VFP instructions may be executed on both NEON and
248 // VFP pipelines on A8.
249 let D = VFPNeonA8Domain;
252 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
253 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
254 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
255 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
257 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
258 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
259 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
260 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
261 // Some single precision VFP instructions may be executed on both NEON and
262 // VFP pipelines on A8.
263 let D = VFPNeonA8Domain;
266 // Match reassociated forms only if not sign dependent rounding.
267 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
268 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
269 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
270 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
272 // These are encoded as unary instructions.
273 let Defs = [FPSCR] in {
274 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
275 (outs), (ins DPR:$Dd, DPR:$Dm),
276 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
277 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
279 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
280 (outs), (ins SPR:$Sd, SPR:$Sm),
281 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
282 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
283 // Some single precision VFP instructions may be executed on both NEON and
284 // VFP pipelines on A8.
285 let D = VFPNeonA8Domain;
288 // FIXME: Verify encoding after integrated assembler is working.
289 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
290 (outs), (ins DPR:$Dd, DPR:$Dm),
291 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
292 [/* For disassembly only; pattern left blank */]>;
294 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
295 (outs), (ins SPR:$Sd, SPR:$Sm),
296 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
297 [/* For disassembly only; pattern left blank */]> {
298 // Some single precision VFP instructions may be executed on both NEON and
299 // VFP pipelines on A8.
300 let D = VFPNeonA8Domain;
304 //===----------------------------------------------------------------------===//
305 // FP Unary Operations.
308 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
309 (outs DPR:$Dd), (ins DPR:$Dm),
310 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
311 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
313 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
314 (outs SPR:$Sd), (ins SPR:$Sm),
315 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
316 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 let Defs = [FPSCR] in {
323 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
324 (outs), (ins DPR:$Dd),
325 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
326 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
327 let Inst{3-0} = 0b0000;
331 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
332 (outs), (ins SPR:$Sd),
333 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
334 [(arm_cmpfp0 SPR:$Sd)]> {
335 let Inst{3-0} = 0b0000;
338 // Some single precision VFP instructions may be executed on both NEON and
339 // VFP pipelines on A8.
340 let D = VFPNeonA8Domain;
343 // FIXME: Verify encoding after integrated assembler is working.
344 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
345 (outs), (ins DPR:$Dd),
346 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
347 [/* For disassembly only; pattern left blank */]> {
348 let Inst{3-0} = 0b0000;
352 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
353 (outs), (ins SPR:$Sd),
354 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
355 [/* For disassembly only; pattern left blank */]> {
356 let Inst{3-0} = 0b0000;
359 // Some single precision VFP instructions may be executed on both NEON and
360 // VFP pipelines on A8.
361 let D = VFPNeonA8Domain;
365 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
366 (outs DPR:$Dd), (ins SPR:$Sm),
367 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
368 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
369 // Instruction operands.
373 // Encode instruction operands.
374 let Inst{3-0} = Sm{4-1};
376 let Inst{15-12} = Dd{3-0};
377 let Inst{22} = Dd{4};
380 // Special case encoding: bits 11-8 is 0b1011.
381 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
382 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
383 [(set SPR:$Sd, (fround DPR:$Dm))]> {
384 // Instruction operands.
388 // Encode instruction operands.
389 let Inst{3-0} = Dm{3-0};
391 let Inst{15-12} = Sd{4-1};
392 let Inst{22} = Sd{0};
394 let Inst{27-23} = 0b11101;
395 let Inst{21-16} = 0b110111;
396 let Inst{11-8} = 0b1011;
397 let Inst{7-6} = 0b11;
401 // Between half-precision and single-precision. For disassembly only.
403 // FIXME: Verify encoding after integrated assembler is working.
404 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
405 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
406 [/* For disassembly only; pattern left blank */]>;
408 def : ARMPat<(f32_to_f16 SPR:$a),
409 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
411 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
412 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
413 [/* For disassembly only; pattern left blank */]>;
415 def : ARMPat<(f16_to_f32 GPR:$a),
416 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
418 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
419 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
420 [/* For disassembly only; pattern left blank */]>;
422 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
423 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
424 [/* For disassembly only; pattern left blank */]>;
426 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
427 (outs DPR:$Dd), (ins DPR:$Dm),
428 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
429 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
431 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
432 (outs SPR:$Sd), (ins SPR:$Sm),
433 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
434 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
435 // Some single precision VFP instructions may be executed on both NEON and
436 // VFP pipelines on A8.
437 let D = VFPNeonA8Domain;
440 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
441 (outs DPR:$Dd), (ins DPR:$Dm),
442 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
443 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
445 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
446 (outs SPR:$Sd), (ins SPR:$Sm),
447 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
448 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
450 let neverHasSideEffects = 1 in {
451 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
452 (outs DPR:$Dd), (ins DPR:$Dm),
453 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
455 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
456 (outs SPR:$Sd), (ins SPR:$Sm),
457 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
458 } // neverHasSideEffects
460 //===----------------------------------------------------------------------===//
461 // FP <-> GPR Copies. Int <-> FP Conversions.
464 def VMOVRS : AVConv2I<0b11100001, 0b1010,
465 (outs GPR:$Rt), (ins SPR:$Sn),
466 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
467 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
468 // Instruction operands.
472 // Encode instruction operands.
473 let Inst{19-16} = Sn{4-1};
475 let Inst{15-12} = Rt;
477 let Inst{6-5} = 0b00;
478 let Inst{3-0} = 0b0000;
480 // Some single precision VFP instructions may be executed on both NEON and VFP
482 let D = VFPNeonDomain;
485 def VMOVSR : AVConv4I<0b11100000, 0b1010,
486 (outs SPR:$Sn), (ins GPR:$Rt),
487 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
488 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
489 // Instruction operands.
493 // Encode instruction operands.
494 let Inst{19-16} = Sn{4-1};
496 let Inst{15-12} = Rt;
498 let Inst{6-5} = 0b00;
499 let Inst{3-0} = 0b0000;
501 // Some single precision VFP instructions may be executed on both NEON and VFP
503 let D = VFPNeonDomain;
506 let neverHasSideEffects = 1 in {
507 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
508 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
509 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
510 [/* FIXME: Can't write pattern for multiple result instr*/]> {
511 // Instruction operands.
516 // Encode instruction operands.
517 let Inst{3-0} = Dm{3-0};
519 let Inst{15-12} = Rt;
520 let Inst{19-16} = Rt2;
522 let Inst{7-6} = 0b00;
524 // Some single precision VFP instructions may be executed on both NEON and VFP
526 let D = VFPNeonDomain;
529 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
530 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
531 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
532 [/* For disassembly only; pattern left blank */]> {
537 // Encode instruction operands.
538 let Inst{3-0} = src1{3-0};
539 let Inst{5} = src1{4};
540 let Inst{15-12} = Rt;
541 let Inst{19-16} = Rt2;
543 let Inst{7-6} = 0b00;
545 // Some single precision VFP instructions may be executed on both NEON and VFP
547 let D = VFPNeonDomain;
548 let DecoderMethod = "DecodeVMOVRRS";
550 } // neverHasSideEffects
555 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
556 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
557 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
558 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
559 // Instruction operands.
564 // Encode instruction operands.
565 let Inst{3-0} = Dm{3-0};
567 let Inst{15-12} = Rt;
568 let Inst{19-16} = Rt2;
570 let Inst{7-6} = 0b00;
572 // Some single precision VFP instructions may be executed on both NEON and VFP
574 let D = VFPNeonDomain;
577 let neverHasSideEffects = 1 in
578 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
579 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
580 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
581 [/* For disassembly only; pattern left blank */]> {
582 // Instruction operands.
587 // Encode instruction operands.
588 let Inst{3-0} = dst1{3-0};
589 let Inst{5} = dst1{4};
590 let Inst{15-12} = src1;
591 let Inst{19-16} = src2;
593 let Inst{7-6} = 0b00;
595 // Some single precision VFP instructions may be executed on both NEON and VFP
597 let D = VFPNeonDomain;
599 let DecoderMethod = "DecodeVMOVSRR";
605 // FMRX: SPR system reg -> GPR
607 // FMXR: GPR -> VFP system reg
612 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
613 bits<4> opcod4, dag oops, dag iops,
614 InstrItinClass itin, string opc, string asm,
616 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
618 // Instruction operands.
622 // Encode instruction operands.
623 let Inst{3-0} = Sm{4-1};
625 let Inst{15-12} = Dd{3-0};
626 let Inst{22} = Dd{4};
629 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
630 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
631 string opc, string asm, list<dag> pattern>
632 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
634 // Instruction operands.
638 // Encode instruction operands.
639 let Inst{3-0} = Sm{4-1};
641 let Inst{15-12} = Sd{4-1};
642 let Inst{22} = Sd{0};
645 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
646 (outs DPR:$Dd), (ins SPR:$Sm),
647 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
648 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
649 let Inst{7} = 1; // s32
652 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
653 (outs SPR:$Sd),(ins SPR:$Sm),
654 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
655 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
656 let Inst{7} = 1; // s32
658 // Some single precision VFP instructions may be executed on both NEON and
659 // VFP pipelines on A8.
660 let D = VFPNeonA8Domain;
663 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
664 (outs DPR:$Dd), (ins SPR:$Sm),
665 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
666 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
667 let Inst{7} = 0; // u32
670 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
671 (outs SPR:$Sd), (ins SPR:$Sm),
672 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
673 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
674 let Inst{7} = 0; // u32
676 // Some single precision VFP instructions may be executed on both NEON and
677 // VFP pipelines on A8.
678 let D = VFPNeonA8Domain;
683 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
684 bits<4> opcod4, dag oops, dag iops,
685 InstrItinClass itin, string opc, string asm,
687 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
689 // Instruction operands.
693 // Encode instruction operands.
694 let Inst{3-0} = Dm{3-0};
696 let Inst{15-12} = Sd{4-1};
697 let Inst{22} = Sd{0};
700 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
701 bits<4> opcod4, dag oops, dag iops,
702 InstrItinClass itin, string opc, string asm,
704 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
706 // Instruction operands.
710 // Encode instruction operands.
711 let Inst{3-0} = Sm{4-1};
713 let Inst{15-12} = Sd{4-1};
714 let Inst{22} = Sd{0};
717 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
718 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
719 (outs SPR:$Sd), (ins DPR:$Dm),
720 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
721 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
722 let Inst{7} = 1; // Z bit
725 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
726 (outs SPR:$Sd), (ins SPR:$Sm),
727 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
728 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
729 let Inst{7} = 1; // Z bit
731 // Some single precision VFP instructions may be executed on both NEON and
732 // VFP pipelines on A8.
733 let D = VFPNeonA8Domain;
736 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
737 (outs SPR:$Sd), (ins DPR:$Dm),
738 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
739 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
740 let Inst{7} = 1; // Z bit
743 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
744 (outs SPR:$Sd), (ins SPR:$Sm),
745 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
746 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
747 let Inst{7} = 1; // Z bit
749 // Some single precision VFP instructions may be executed on both NEON and
750 // VFP pipelines on A8.
751 let D = VFPNeonA8Domain;
754 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
755 let Uses = [FPSCR] in {
756 // FIXME: Verify encoding after integrated assembler is working.
757 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
758 (outs SPR:$Sd), (ins DPR:$Dm),
759 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
760 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
761 let Inst{7} = 0; // Z bit
764 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
765 (outs SPR:$Sd), (ins SPR:$Sm),
766 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
767 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
768 let Inst{7} = 0; // Z bit
771 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
772 (outs SPR:$Sd), (ins DPR:$Dm),
773 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
774 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
775 let Inst{7} = 0; // Z bit
778 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
779 (outs SPR:$Sd), (ins SPR:$Sm),
780 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
781 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
782 let Inst{7} = 0; // Z bit
786 // Convert between floating-point and fixed-point
787 // Data type for fixed-point naming convention:
788 // S16 (U=0, sx=0) -> SH
789 // U16 (U=1, sx=0) -> UH
790 // S32 (U=0, sx=1) -> SL
791 // U32 (U=1, sx=1) -> UL
793 // FIXME: Marking these as codegen only seems wrong. They are real
795 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
797 // FP to Fixed-Point:
799 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
800 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
801 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
802 [/* For disassembly only; pattern left blank */]> {
803 // Some single precision VFP instructions may be executed on both NEON and
804 // VFP pipelines on A8.
805 let D = VFPNeonA8Domain;
808 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
809 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
810 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
811 [/* For disassembly only; pattern left blank */]> {
812 // Some single precision VFP instructions may be executed on both NEON and
813 // VFP pipelines on A8.
814 let D = VFPNeonA8Domain;
817 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
818 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
819 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
820 [/* For disassembly only; pattern left blank */]> {
821 // Some single precision VFP instructions may be executed on both NEON and
822 // VFP pipelines on A8.
823 let D = VFPNeonA8Domain;
826 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
827 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
828 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
829 [/* For disassembly only; pattern left blank */]> {
830 // Some single precision VFP instructions may be executed on both NEON and
831 // VFP pipelines on A8.
832 let D = VFPNeonA8Domain;
835 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
836 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
837 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
838 [/* For disassembly only; pattern left blank */]>;
840 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
841 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
842 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
843 [/* For disassembly only; pattern left blank */]>;
845 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
846 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
847 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
848 [/* For disassembly only; pattern left blank */]>;
850 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
851 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
852 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
853 [/* For disassembly only; pattern left blank */]>;
855 // Fixed-Point to FP:
857 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
858 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
859 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
860 [/* For disassembly only; pattern left blank */]> {
861 // Some single precision VFP instructions may be executed on both NEON and
862 // VFP pipelines on A8.
863 let D = VFPNeonA8Domain;
866 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
867 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
868 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
869 [/* For disassembly only; pattern left blank */]> {
870 // Some single precision VFP instructions may be executed on both NEON and
871 // VFP pipelines on A8.
872 let D = VFPNeonA8Domain;
875 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
876 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
877 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
878 [/* For disassembly only; pattern left blank */]> {
879 // Some single precision VFP instructions may be executed on both NEON and
880 // VFP pipelines on A8.
881 let D = VFPNeonA8Domain;
884 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
885 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
886 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
887 [/* For disassembly only; pattern left blank */]> {
888 // Some single precision VFP instructions may be executed on both NEON and
889 // VFP pipelines on A8.
890 let D = VFPNeonA8Domain;
893 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
894 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
895 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
896 [/* For disassembly only; pattern left blank */]>;
898 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
899 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
900 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
901 [/* For disassembly only; pattern left blank */]>;
903 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
904 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
905 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
906 [/* For disassembly only; pattern left blank */]>;
908 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
909 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
910 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
911 [/* For disassembly only; pattern left blank */]>;
913 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
915 //===----------------------------------------------------------------------===//
916 // FP Multiply-Accumulate Operations.
919 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
920 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
921 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
922 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
924 RegConstraint<"$Ddin = $Dd">,
925 Requires<[HasVFP2,UseFPVMLx]>;
927 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
928 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
929 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
930 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
932 RegConstraint<"$Sdin = $Sd">,
933 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
934 // Some single precision VFP instructions may be executed on both NEON and
935 // VFP pipelines on A8.
936 let D = VFPNeonA8Domain;
939 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
940 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
941 Requires<[HasVFP2,UseFPVMLx]>;
942 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
943 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
944 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>;
946 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
947 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
948 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
949 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
951 RegConstraint<"$Ddin = $Dd">,
952 Requires<[HasVFP2,UseFPVMLx]>;
954 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
955 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
956 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
957 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
959 RegConstraint<"$Sdin = $Sd">,
960 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
961 // Some single precision VFP instructions may be executed on both NEON and
962 // VFP pipelines on A8.
963 let D = VFPNeonA8Domain;
966 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
967 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
968 Requires<[HasVFP2,UseFPVMLx]>;
969 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
970 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
971 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
973 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
974 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
975 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
976 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
978 RegConstraint<"$Ddin = $Dd">,
979 Requires<[HasVFP2,UseFPVMLx]>;
981 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
982 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
983 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
984 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
986 RegConstraint<"$Sdin = $Sd">,
987 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
988 // Some single precision VFP instructions may be executed on both NEON and
989 // VFP pipelines on A8.
990 let D = VFPNeonA8Domain;
993 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
994 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
995 Requires<[HasVFP2,UseFPVMLx]>;
996 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
997 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
998 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
1000 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1001 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1002 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1003 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1004 (f64 DPR:$Ddin)))]>,
1005 RegConstraint<"$Ddin = $Dd">,
1006 Requires<[HasVFP2,UseFPVMLx]>;
1008 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1009 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1010 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1011 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1012 RegConstraint<"$Sdin = $Sd">,
1013 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]> {
1014 // Some single precision VFP instructions may be executed on both NEON and
1015 // VFP pipelines on A8.
1016 let D = VFPNeonA8Domain;
1019 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1020 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1021 Requires<[HasVFP2,UseFPVMLx]>;
1022 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1023 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1024 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>;
1027 //===----------------------------------------------------------------------===//
1028 // FP Conditional moves.
1031 let neverHasSideEffects = 1 in {
1032 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1034 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1035 RegConstraint<"$Dn = $Dd">;
1037 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1039 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1040 RegConstraint<"$Sn = $Sd">;
1041 } // neverHasSideEffects
1043 //===----------------------------------------------------------------------===//
1044 // Move from VFP System Register to ARM core register.
1047 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1049 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1051 // Instruction operand.
1054 let Inst{27-20} = 0b11101111;
1055 let Inst{19-16} = opc19_16;
1056 let Inst{15-12} = Rt;
1057 let Inst{11-8} = 0b1010;
1059 let Inst{6-5} = 0b00;
1061 let Inst{3-0} = 0b0000;
1064 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1066 let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
1067 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1068 "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
1070 // Application level FPSCR -> GPR
1071 let hasSideEffects = 1, Uses = [FPSCR] in
1072 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1073 "vmrs", "\t$Rt, fpscr",
1074 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1076 // System level FPEXC, FPSID -> GPR
1077 let Uses = [FPSCR] in {
1078 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1079 "vmrs", "\t$Rt, fpexc", []>;
1080 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1081 "vmrs", "\t$Rt, fpsid", []>;
1084 //===----------------------------------------------------------------------===//
1085 // Move from ARM core register to VFP System Register.
1088 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1090 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1092 // Instruction operand.
1095 // Encode instruction operand.
1096 let Inst{15-12} = src;
1098 let Inst{27-20} = 0b11101110;
1099 let Inst{19-16} = opc19_16;
1100 let Inst{11-8} = 0b1010;
1105 let Defs = [FPSCR] in {
1106 // Application level GPR -> FPSCR
1107 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1108 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1109 // System level GPR -> FPEXC
1110 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1111 "vmsr", "\tfpexc, $src", []>;
1112 // System level GPR -> FPSID
1113 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1114 "vmsr", "\tfpsid, $src", []>;
1117 //===----------------------------------------------------------------------===//
1121 // Materialize FP immediates. VFP3 only.
1122 let isReMaterializable = 1 in {
1123 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1124 VFPMiscFrm, IIC_fpUNA64,
1125 "vmov", ".f64\t$Dd, $imm",
1126 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1130 let Inst{27-23} = 0b11101;
1131 let Inst{22} = Dd{4};
1132 let Inst{21-20} = 0b11;
1133 let Inst{19-16} = imm{7-4};
1134 let Inst{15-12} = Dd{3-0};
1135 let Inst{11-9} = 0b101;
1136 let Inst{8} = 1; // Double precision.
1137 let Inst{7-4} = 0b0000;
1138 let Inst{3-0} = imm{3-0};
1141 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1142 VFPMiscFrm, IIC_fpUNA32,
1143 "vmov", ".f32\t$Sd, $imm",
1144 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1148 let Inst{27-23} = 0b11101;
1149 let Inst{22} = Sd{0};
1150 let Inst{21-20} = 0b11;
1151 let Inst{19-16} = imm{7-4};
1152 let Inst{15-12} = Sd{4-1};
1153 let Inst{11-9} = 0b101;
1154 let Inst{8} = 0; // Single precision.
1155 let Inst{7-4} = 0b0000;
1156 let Inst{3-0} = imm{3-0};
1160 //===----------------------------------------------------------------------===//
1161 // Assembler aliases.
1163 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1164 // support them all, but supporting at least some of the basics is
1165 // good to be friendly.
1166 def : VFP2MnemonicAlias<"flds", "vldr">;
1167 def : VFP2MnemonicAlias<"fldd", "vldr">;
1168 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1169 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1170 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1171 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1172 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1173 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1174 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1175 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1176 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1177 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1178 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1179 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1180 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1181 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1182 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1183 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1184 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1185 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1186 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1187 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1188 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1189 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1190 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1191 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1192 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1194 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1195 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1196 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1197 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1198 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1199 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1200 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1201 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1202 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1204 // No need for the size suffix on VSQRT. It's implied by the register classes.
1205 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1206 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1208 // VLDR/VSTR accept an optional type suffix.
1209 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1210 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1211 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1212 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1213 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1214 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1215 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1216 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1218 // VMUL has a two-operand form (implied destination operand)
1219 def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
1220 (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
1221 def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
1222 (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
1223 // VADD has a two-operand form (implied destination operand)
1224 def : VFP2InstAlias<"vadd${p}.f64 $Dn, $Dm",
1225 (VADDD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
1226 def : VFP2InstAlias<"vadd${p}.f32 $Sn, $Sm",
1227 (VADDS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
1228 // VSUB has a two-operand form (implied destination operand)
1229 def : VFP2InstAlias<"vsub${p}.f64 $Dn, $Dm",
1230 (VSUBD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
1231 def : VFP2InstAlias<"vsub${p}.f32 $Sn, $Sm",
1232 (VSUBS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
1234 // VMOV can accept optional .f32/.f64 suffix.
1235 def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn",
1236 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1237 def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt",
1238 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1240 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1241 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1242 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1243 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1245 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1247 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1248 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;