1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag, SDNPOutFlag]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
41 def vfp_f64imm : Operand<f64>,
42 PatLeaf<(f64 fpimm), [{
43 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
45 let PrintMethod = "printVFPf64ImmOperand";
49 //===----------------------------------------------------------------------===//
50 // Load / store Instructions.
53 let canFoldAsLoad = 1, isReMaterializable = 1 in {
54 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
55 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
56 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
58 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
60 [(set SPR:$dst, (load addrmode5:$addr))]>;
63 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
64 IIC_fpStore64, "vstr", ".64\t$src, $addr",
65 [(store (f64 DPR:$src), addrmode5:$addr)]>;
67 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
68 IIC_fpStore32, "vstr", ".32\t$src, $addr",
69 [(store SPR:$src, addrmode5:$addr)]>;
71 //===----------------------------------------------------------------------===//
72 // Load / store multiple Instructions.
75 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
76 isCodeGenOnly = 1 in {
77 def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
78 variable_ops), IndexModeNone, IIC_fpLoad_m,
79 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
83 def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
84 variable_ops), IndexModeNone, IIC_fpLoad_m,
85 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
89 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
90 reglist:$dsts, variable_ops),
91 IndexModeUpd, IIC_fpLoad_mu,
92 "vldm${addr:submode}${p}\t$addr!, $dsts",
93 "$addr.addr = $wb", []> {
97 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
98 reglist:$dsts, variable_ops),
99 IndexModeUpd, IIC_fpLoad_mu,
100 "vldm${addr:submode}${p}\t$addr!, $dsts",
101 "$addr.addr = $wb", []> {
104 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
106 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
107 isCodeGenOnly = 1 in {
108 def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
109 variable_ops), IndexModeNone, IIC_fpStore_m,
110 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
114 def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
115 variable_ops), IndexModeNone, IIC_fpStore_m,
116 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
120 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
121 reglist:$srcs, variable_ops),
122 IndexModeUpd, IIC_fpStore_mu,
123 "vstm${addr:submode}${p}\t$addr!, $srcs",
124 "$addr.addr = $wb", []> {
128 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
129 reglist:$srcs, variable_ops),
130 IndexModeUpd, IIC_fpStore_mu,
131 "vstm${addr:submode}${p}\t$addr!, $srcs",
132 "$addr.addr = $wb", []> {
135 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
137 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
139 //===----------------------------------------------------------------------===//
140 // FP Binary Operations.
143 def VADDD : ADbI<0b11100, 0b11, 0, 0,
144 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
145 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
146 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
148 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
149 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
150 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
151 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
153 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
154 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
155 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
156 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
158 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
159 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
160 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
161 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
163 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
164 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
165 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
166 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
168 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
169 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
170 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
171 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
173 def VMULD : ADbI<0b11100, 0b10, 0, 0,
174 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
175 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
176 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
178 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
179 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
180 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
181 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
183 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
184 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
185 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
186 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
188 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
189 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
190 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
191 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
193 // Match reassociated forms only if not sign dependent rounding.
194 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
195 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
196 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
197 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
199 // These are encoded as unary instructions.
200 let Defs = [FPSCR] in {
201 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
202 (outs), (ins DPR:$Dd, DPR:$Dm),
203 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
204 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
206 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
207 (outs), (ins SPR:$Sd, SPR:$Sm),
208 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
209 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
211 // FIXME: Verify encoding after integrated assembler is working.
212 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
213 (outs), (ins DPR:$Dd, DPR:$Dm),
214 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
215 [/* For disassembly only; pattern left blank */]>;
217 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
218 (outs), (ins SPR:$Sd, SPR:$Sm),
219 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
220 [/* For disassembly only; pattern left blank */]>;
223 //===----------------------------------------------------------------------===//
224 // FP Unary Operations.
227 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
228 (outs DPR:$Dd), (ins DPR:$Dm),
229 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
230 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
232 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
233 (outs SPR:$Sd), (ins SPR:$Sm),
234 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
235 [(set SPR:$Sd, (fabs SPR:$Sm))]>;
237 let Defs = [FPSCR] in {
238 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
239 (outs), (ins DPR:$Dd),
240 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
241 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
242 let Inst{3-0} = 0b0000;
246 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
247 (outs), (ins SPR:$Sd),
248 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
249 [(arm_cmpfp0 SPR:$Sd)]> {
250 let Inst{3-0} = 0b0000;
254 // FIXME: Verify encoding after integrated assembler is working.
255 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
256 (outs), (ins DPR:$Dd),
257 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
258 [/* For disassembly only; pattern left blank */]> {
259 let Inst{3-0} = 0b0000;
263 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
264 (outs), (ins SPR:$Sd),
265 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
266 [/* For disassembly only; pattern left blank */]> {
267 let Inst{3-0} = 0b0000;
272 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
273 (outs DPR:$Dd), (ins SPR:$Sm),
274 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
275 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
276 // Instruction operands.
280 // Encode instruction operands.
281 let Inst{3-0} = Sm{4-1};
283 let Inst{15-12} = Dd{3-0};
284 let Inst{22} = Dd{4};
287 // Special case encoding: bits 11-8 is 0b1011.
288 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
289 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
290 [(set SPR:$Sd, (fround DPR:$Dm))]> {
291 // Instruction operands.
295 // Encode instruction operands.
296 let Inst{3-0} = Dm{3-0};
298 let Inst{15-12} = Sd{4-1};
299 let Inst{22} = Sd{0};
301 let Inst{27-23} = 0b11101;
302 let Inst{21-16} = 0b110111;
303 let Inst{11-8} = 0b1011;
304 let Inst{7-6} = 0b11;
308 // Between half-precision and single-precision. For disassembly only.
310 // FIXME: Verify encoding after integrated assembler is working.
311 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
312 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
313 [/* For disassembly only; pattern left blank */]>;
315 def : ARMPat<(f32_to_f16 SPR:$a),
316 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
318 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
319 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
320 [/* For disassembly only; pattern left blank */]>;
322 def : ARMPat<(f16_to_f32 GPR:$a),
323 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
325 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
326 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
327 [/* For disassembly only; pattern left blank */]>;
329 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
330 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
331 [/* For disassembly only; pattern left blank */]>;
333 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
334 (outs DPR:$Dd), (ins DPR:$Dm),
335 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
336 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
338 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
339 (outs SPR:$Sd), (ins SPR:$Sm),
340 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
341 [(set SPR:$Sd, (fneg SPR:$Sm))]>;
343 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
344 (outs DPR:$Dd), (ins DPR:$Dm),
345 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
346 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
348 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
349 (outs SPR:$Sd), (ins SPR:$Sm),
350 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
351 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
353 let neverHasSideEffects = 1 in {
354 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
355 (outs DPR:$Dd), (ins DPR:$Dm),
356 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
358 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
359 (outs SPR:$Sd), (ins SPR:$Sm),
360 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
361 } // neverHasSideEffects
363 //===----------------------------------------------------------------------===//
364 // FP <-> GPR Copies. Int <-> FP Conversions.
367 def VMOVRS : AVConv2I<0b11100001, 0b1010,
368 (outs GPR:$Rt), (ins SPR:$Sn),
369 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
370 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
371 // Instruction operands.
375 // Encode instruction operands.
376 let Inst{19-16} = Sn{4-1};
378 let Inst{15-12} = Rt;
380 let Inst{6-5} = 0b00;
381 let Inst{3-0} = 0b0000;
384 def VMOVSR : AVConv4I<0b11100000, 0b1010,
385 (outs SPR:$Sn), (ins GPR:$Rt),
386 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
387 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
388 // Instruction operands.
392 // Encode instruction operands.
393 let Inst{19-16} = Sn{4-1};
395 let Inst{15-12} = Rt;
397 let Inst{6-5} = 0b00;
398 let Inst{3-0} = 0b0000;
401 let neverHasSideEffects = 1 in {
402 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
403 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
404 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
405 [/* FIXME: Can't write pattern for multiple result instr*/]> {
406 // Instruction operands.
411 // Encode instruction operands.
412 let Inst{3-0} = Dm{3-0};
414 let Inst{15-12} = Rt;
415 let Inst{19-16} = Rt2;
417 let Inst{7-6} = 0b00;
420 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
421 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
422 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
423 [/* For disassembly only; pattern left blank */]> {
424 let Inst{7-6} = 0b00;
426 } // neverHasSideEffects
431 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
432 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
433 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
434 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
435 // Instruction operands.
440 // Encode instruction operands.
441 let Inst{3-0} = Dm{3-0};
443 let Inst{15-12} = Rt;
444 let Inst{19-16} = Rt2;
446 let Inst{7-6} = 0b00;
449 let neverHasSideEffects = 1 in
450 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
451 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
452 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
453 [/* For disassembly only; pattern left blank */]> {
454 let Inst{7-6} = 0b00;
460 // FMRX: SPR system reg -> GPR
462 // FMXR: GPR -> VFP system reg
467 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
468 bits<4> opcod4, dag oops, dag iops,
469 InstrItinClass itin, string opc, string asm,
471 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
473 // Instruction operands.
477 // Encode instruction operands.
478 let Inst{3-0} = Sm{4-1};
480 let Inst{15-12} = Dd{3-0};
481 let Inst{22} = Dd{4};
484 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
485 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
486 string opc, string asm, list<dag> pattern>
487 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
489 // Instruction operands.
493 // Encode instruction operands.
494 let Inst{3-0} = Sm{4-1};
496 let Inst{15-12} = Sd{4-1};
497 let Inst{22} = Sd{0};
500 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
501 (outs DPR:$Dd), (ins SPR:$Sm),
502 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
503 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
504 let Inst{7} = 1; // s32
507 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
508 (outs SPR:$Sd),(ins SPR:$Sm),
509 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
510 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
511 let Inst{7} = 1; // s32
514 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
515 (outs DPR:$Dd), (ins SPR:$Sm),
516 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
517 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
518 let Inst{7} = 0; // u32
521 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
522 (outs SPR:$Sd), (ins SPR:$Sm),
523 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
524 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
525 let Inst{7} = 0; // u32
530 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
531 bits<4> opcod4, dag oops, dag iops,
532 InstrItinClass itin, string opc, string asm,
534 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
536 // Instruction operands.
540 // Encode instruction operands.
541 let Inst{3-0} = Dm{3-0};
543 let Inst{15-12} = Sd{4-1};
544 let Inst{22} = Sd{0};
547 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
548 bits<4> opcod4, dag oops, dag iops,
549 InstrItinClass itin, string opc, string asm,
551 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
553 // Instruction operands.
557 // Encode instruction operands.
558 let Inst{3-0} = Sm{4-1};
560 let Inst{15-12} = Sd{4-1};
561 let Inst{22} = Sd{0};
564 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
565 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
566 (outs SPR:$Sd), (ins DPR:$Dm),
567 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
568 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
569 let Inst{7} = 1; // Z bit
572 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
573 (outs SPR:$Sd), (ins SPR:$Sm),
574 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
575 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
576 let Inst{7} = 1; // Z bit
579 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
580 (outs SPR:$Sd), (ins DPR:$Dm),
581 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
582 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
583 let Inst{7} = 1; // Z bit
586 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
587 (outs SPR:$Sd), (ins SPR:$Sm),
588 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
589 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
590 let Inst{7} = 1; // Z bit
593 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
594 // For disassembly only.
595 let Uses = [FPSCR] in {
596 // FIXME: Verify encoding after integrated assembler is working.
597 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
598 (outs SPR:$Sd), (ins DPR:$Dm),
599 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
600 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
601 let Inst{7} = 0; // Z bit
604 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
605 (outs SPR:$Sd), (ins SPR:$Sm),
606 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
607 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
608 let Inst{7} = 0; // Z bit
611 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
612 (outs SPR:$Sd), (ins DPR:$Dm),
613 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
614 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
615 let Inst{7} = 0; // Z bit
618 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
619 (outs SPR:$Sd), (ins SPR:$Sm),
620 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
621 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
622 let Inst{7} = 0; // Z bit
626 // Convert between floating-point and fixed-point
627 // Data type for fixed-point naming convention:
628 // S16 (U=0, sx=0) -> SH
629 // U16 (U=1, sx=0) -> UH
630 // S32 (U=0, sx=1) -> SL
631 // U32 (U=1, sx=1) -> UL
633 // FIXME: Marking these as codegen only seems wrong. They are real
635 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
637 // FP to Fixed-Point:
639 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
640 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
641 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
642 [/* For disassembly only; pattern left blank */]>;
644 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
645 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
646 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
647 [/* For disassembly only; pattern left blank */]>;
649 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
650 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
651 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
652 [/* For disassembly only; pattern left blank */]>;
654 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
655 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
656 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
657 [/* For disassembly only; pattern left blank */]>;
659 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
660 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
661 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
662 [/* For disassembly only; pattern left blank */]>;
664 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
665 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
666 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
667 [/* For disassembly only; pattern left blank */]>;
669 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
670 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
671 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
672 [/* For disassembly only; pattern left blank */]>;
674 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
675 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
676 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
677 [/* For disassembly only; pattern left blank */]>;
679 // Fixed-Point to FP:
681 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
682 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
683 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
684 [/* For disassembly only; pattern left blank */]>;
686 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
687 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
688 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
689 [/* For disassembly only; pattern left blank */]>;
691 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
692 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
693 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
694 [/* For disassembly only; pattern left blank */]>;
696 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
697 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
698 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
699 [/* For disassembly only; pattern left blank */]>;
701 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
702 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
703 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
704 [/* For disassembly only; pattern left blank */]>;
706 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
707 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
708 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
709 [/* For disassembly only; pattern left blank */]>;
711 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
712 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
713 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
714 [/* For disassembly only; pattern left blank */]>;
716 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
717 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
718 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
719 [/* For disassembly only; pattern left blank */]>;
721 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
723 //===----------------------------------------------------------------------===//
724 // FP FMA Operations.
727 def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
728 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
729 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
730 [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
732 RegConstraint<"$Ddin = $Dd">;
734 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
735 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
736 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
737 [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
739 RegConstraint<"$Sdin = $Sd">;
741 def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
742 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
743 def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
744 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
746 def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
747 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
748 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
749 [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
751 RegConstraint<"$Ddin = $Dd">;
753 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
754 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
755 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
756 [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
758 RegConstraint<"$Sdin = $Sd">;
760 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
761 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
762 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
763 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
765 def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
766 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
767 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
768 [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
770 RegConstraint<"$Ddin = $Dd">;
772 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
773 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
774 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
775 [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
777 RegConstraint<"$Sdin = $Sd">;
779 def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
780 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
781 def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
782 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
784 def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
785 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
786 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
787 [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
789 RegConstraint<"$Ddin = $Dd">;
791 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
792 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
793 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
794 [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
795 RegConstraint<"$Sdin = $Sd">;
797 def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
798 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
799 def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
800 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
803 //===----------------------------------------------------------------------===//
804 // FP Conditional moves.
807 let neverHasSideEffects = 1 in {
808 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
809 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
810 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
811 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
812 RegConstraint<"$Dn = $Dd">;
814 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
815 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
816 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
817 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
818 RegConstraint<"$Sn = $Sd">;
820 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
821 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
822 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
823 [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
824 RegConstraint<"$Dn = $Dd">;
826 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
827 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
828 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
829 [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
830 RegConstraint<"$Sn = $Sd">;
831 } // neverHasSideEffects
833 //===----------------------------------------------------------------------===//
837 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
839 let Defs = [CPSR], Uses = [FPSCR] in
840 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT,
841 "vmrs", "\tapsr_nzcv, fpscr",
843 let Inst{27-20} = 0b11101111;
844 let Inst{19-16} = 0b0001;
845 let Inst{15-12} = 0b1111;
846 let Inst{11-8} = 0b1010;
848 let Inst{6-5} = 0b00;
850 let Inst{3-0} = 0b0000;
854 let hasSideEffects = 1, Uses = [FPSCR] in
855 def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
856 "vmrs", "\t$Rt, fpscr",
857 [(set GPR:$Rt, (int_arm_get_fpscr))]> {
858 // Instruction operand.
861 // Encode instruction operand.
862 let Inst{15-12} = Rt;
864 let Inst{27-20} = 0b11101111;
865 let Inst{19-16} = 0b0001;
866 let Inst{11-8} = 0b1010;
868 let Inst{6-5} = 0b00;
870 let Inst{3-0} = 0b0000;
873 let Defs = [FPSCR] in
874 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
875 "vmsr", "\tfpscr, $src",
876 [(int_arm_set_fpscr GPR:$src)]> {
877 // Instruction operand.
880 // Encode instruction operand.
881 let Inst{15-12} = src;
883 let Inst{27-20} = 0b11101110;
884 let Inst{19-16} = 0b0001;
885 let Inst{11-8} = 0b1010;
890 // Materialize FP immediates. VFP3 only.
891 let isReMaterializable = 1 in {
892 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
893 VFPMiscFrm, IIC_fpUNA64,
894 "vmov", ".f64\t$Dd, $imm",
895 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
896 // Instruction operands.
900 // Encode instruction operands.
901 let Inst{15-12} = Dd{3-0};
902 let Inst{22} = Dd{4};
903 let Inst{19} = imm{31};
904 let Inst{18-16} = imm{22-20};
905 let Inst{3-0} = imm{19-16};
907 // Encode remaining instruction bits.
908 let Inst{27-23} = 0b11101;
909 let Inst{21-20} = 0b11;
910 let Inst{11-9} = 0b101;
911 let Inst{8} = 1; // Double precision.
912 let Inst{7-4} = 0b0000;
915 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
916 VFPMiscFrm, IIC_fpUNA32,
917 "vmov", ".f32\t$Sd, $imm",
918 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
919 // Instruction operands.
923 // Encode instruction operands.
924 let Inst{15-12} = Sd{4-1};
925 let Inst{22} = Sd{0};
926 let Inst{19} = imm{31}; // The immediate is handled as a double.
927 let Inst{18-16} = imm{22-20};
928 let Inst{3-0} = imm{19-16};
930 // Encode remaining instruction bits.
931 let Inst{27-23} = 0b11101;
932 let Inst{21-20} = 0b11;
933 let Inst{11-9} = 0b101;
934 let Inst{8} = 0; // Single precision.
935 let Inst{7-4} = 0b0000;