1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VP instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM VFP Instruction templates.
18 // ARM Float Instruction
19 class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
20 : AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
21 // TODO: Mark the instructions with the appropriate subtarget info.
24 class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
25 : I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
26 VFPFrm, opc, asm, "", pattern> {
27 // TODO: Mark the instructions with the appropriate subtarget info.
30 // ARM Double Instruction
31 class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
32 : AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> {
33 // TODO: Mark the instructions with the appropriate subtarget info.
36 class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
37 : I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
38 VFPFrm, opc, asm, "", pattern> {
39 // TODO: Mark the instructions with the appropriate subtarget info.
43 class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
44 : XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
45 VFPFrm, asm, "", pattern> {
46 // TODO: Mark the instructions with the appropriate subtarget info.
49 class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
50 : XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
51 VFPFrm, asm, "", pattern> {
52 // TODO: Mark the instructions with the appropriate subtarget info.
55 class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
56 : XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
57 VFPFrm, asm, "", pattern> {
58 // TODO: Mark the instructions with the appropriate subtarget info.
61 class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
62 : XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
63 VFPFrm, asm, "", pattern> {
64 // TODO: Mark the instructions with the appropriate subtarget info.
69 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
71 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
73 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
75 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
78 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
79 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
80 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
81 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
82 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
83 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
84 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
85 def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
87 //===----------------------------------------------------------------------===//
88 // Load / store Instructions.
91 let isSimpleLoad = 1 in {
92 def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
93 "fldd", " $dst, $addr",
94 [(set DPR:$dst, (load addrmode5:$addr))]>;
96 def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr),
97 "flds", " $dst, $addr",
98 [(set SPR:$dst, (load addrmode5:$addr))]>;
101 def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
102 "fstd", " $src, $addr",
103 [(store DPR:$src, addrmode5:$addr)]>;
105 def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
106 "fsts", " $src, $addr",
107 [(store SPR:$src, addrmode5:$addr)]>;
109 //===----------------------------------------------------------------------===//
110 // Load / store multiple Instructions.
113 def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
115 "fldm${addr:submode}d${p} ${addr:base}, $dst1",
118 def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
120 "fldm${addr:submode}s${p} ${addr:base}, $dst1",
123 let mayStore = 1 in {
124 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
126 "fstm${addr:submode}d${p} ${addr:base}, $src1",
129 def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
131 "fstm${addr:submode}s${p} ${addr:base}, $src1",
135 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
137 //===----------------------------------------------------------------------===//
138 // FP Binary Operations.
141 def FADDD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
142 "faddd", " $dst, $a, $b",
143 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
145 def FADDS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
146 "fadds", " $dst, $a, $b",
147 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
149 def FCMPED : ADI<(outs), (ins DPR:$a, DPR:$b),
151 [(arm_cmpfp DPR:$a, DPR:$b)]>;
153 def FCMPES : ASI<(outs), (ins SPR:$a, SPR:$b),
155 [(arm_cmpfp SPR:$a, SPR:$b)]>;
157 def FDIVD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
158 "fdivd", " $dst, $a, $b",
159 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
161 def FDIVS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
162 "fdivs", " $dst, $a, $b",
163 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
165 def FMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
166 "fmuld", " $dst, $a, $b",
167 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
169 def FMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
170 "fmuls", " $dst, $a, $b",
171 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
173 def FNMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
174 "fnmuld", " $dst, $a, $b",
175 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
177 def FNMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
178 "fnmuls", " $dst, $a, $b",
179 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
181 // Match reassociated forms only if not sign dependent rounding.
182 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
183 (FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
184 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
185 (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
188 def FSUBD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
189 "fsubd", " $dst, $a, $b",
190 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
192 def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
193 "fsubs", " $dst, $a, $b",
194 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
196 //===----------------------------------------------------------------------===//
197 // FP Unary Operations.
200 def FABSD : ADI<(outs DPR:$dst), (ins DPR:$a),
201 "fabsd", " $dst, $a",
202 [(set DPR:$dst, (fabs DPR:$a))]>;
204 def FABSS : ASI<(outs SPR:$dst), (ins SPR:$a),
205 "fabss", " $dst, $a",
206 [(set SPR:$dst, (fabs SPR:$a))]>;
208 def FCMPEZD : ADI<(outs), (ins DPR:$a),
210 [(arm_cmpfp0 DPR:$a)]>;
212 def FCMPEZS : ASI<(outs), (ins SPR:$a),
214 [(arm_cmpfp0 SPR:$a)]>;
216 def FCVTDS : ADI<(outs DPR:$dst), (ins SPR:$a),
217 "fcvtds", " $dst, $a",
218 [(set DPR:$dst, (fextend SPR:$a))]>;
220 def FCVTSD : ADI<(outs SPR:$dst), (ins DPR:$a),
221 "fcvtsd", " $dst, $a",
222 [(set SPR:$dst, (fround DPR:$a))]>;
224 def FCPYD : ADI<(outs DPR:$dst), (ins DPR:$a),
225 "fcpyd", " $dst, $a", []>;
227 def FCPYS : ASI<(outs SPR:$dst), (ins SPR:$a),
228 "fcpys", " $dst, $a", []>;
230 def FNEGD : ADI<(outs DPR:$dst), (ins DPR:$a),
231 "fnegd", " $dst, $a",
232 [(set DPR:$dst, (fneg DPR:$a))]>;
234 def FNEGS : ASI<(outs SPR:$dst), (ins SPR:$a),
235 "fnegs", " $dst, $a",
236 [(set SPR:$dst, (fneg SPR:$a))]>;
238 def FSQRTD : ADI<(outs DPR:$dst), (ins DPR:$a),
239 "fsqrtd", " $dst, $a",
240 [(set DPR:$dst, (fsqrt DPR:$a))]>;
242 def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a),
243 "fsqrts", " $dst, $a",
244 [(set SPR:$dst, (fsqrt SPR:$a))]>;
246 //===----------------------------------------------------------------------===//
247 // FP <-> GPR Copies. Int <-> FP Conversions.
250 let isImplicitDef = 1 in {
251 def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
252 "@ IMPLICIT_DEF_SPR $rD",
253 [(set SPR:$rD, (undef))]>;
254 def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
255 "@ IMPLICIT_DEF_DPR $rD",
256 [(set DPR:$rD, (undef))]>;
259 def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src),
260 "fmrs", " $dst, $src",
261 [(set GPR:$dst, (bitconvert SPR:$src))]>;
263 def FMSR : ASI<(outs SPR:$dst), (ins GPR:$src),
264 "fmsr", " $dst, $src",
265 [(set SPR:$dst, (bitconvert GPR:$src))]>;
268 def FMRRD : ADI<(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
269 "fmrrd", " $dst1, $dst2, $src",
270 [/* FIXME: Can't write pattern for multiple result instr*/]>;
275 def FMDRR : ADI<(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
276 "fmdrr", " $dst, $src1, $src2",
277 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
282 // FMRX : SPR system reg -> GPR
287 def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>;
289 // FMXR: GPR -> VFP Sstem reg
294 def FSITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
295 "fsitod", " $dst, $a",
296 [(set DPR:$dst, (arm_sitof SPR:$a))]>;
298 def FSITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
299 "fsitos", " $dst, $a",
300 [(set SPR:$dst, (arm_sitof SPR:$a))]>;
302 def FUITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
303 "fuitod", " $dst, $a",
304 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
306 def FUITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
307 "fuitos", " $dst, $a",
308 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
311 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
313 def FTOSIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
314 "ftosizd", " $dst, $a",
315 [(set SPR:$dst, (arm_ftosi DPR:$a))]>;
317 def FTOSIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
318 "ftosizs", " $dst, $a",
319 [(set SPR:$dst, (arm_ftosi SPR:$a))]>;
321 def FTOUIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
322 "ftouizd", " $dst, $a",
323 [(set SPR:$dst, (arm_ftoui DPR:$a))]>;
325 def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
326 "ftouizs", " $dst, $a",
327 [(set SPR:$dst, (arm_ftoui SPR:$a))]>;
329 //===----------------------------------------------------------------------===//
330 // FP FMA Operations.
333 def FMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
334 "fmacd", " $dst, $a, $b",
335 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
336 RegConstraint<"$dstin = $dst">;
338 def FMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
339 "fmacs", " $dst, $a, $b",
340 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
341 RegConstraint<"$dstin = $dst">;
343 def FMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
344 "fmscd", " $dst, $a, $b",
345 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
346 RegConstraint<"$dstin = $dst">;
348 def FMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
349 "fmscs", " $dst, $a, $b",
350 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
351 RegConstraint<"$dstin = $dst">;
353 def FNMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
354 "fnmacd", " $dst, $a, $b",
355 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
356 RegConstraint<"$dstin = $dst">;
358 def FNMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
359 "fnmacs", " $dst, $a, $b",
360 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
361 RegConstraint<"$dstin = $dst">;
363 def FNMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
364 "fnmscd", " $dst, $a, $b",
365 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
366 RegConstraint<"$dstin = $dst">;
368 def FNMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
369 "fnmscs", " $dst, $a, $b",
370 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
371 RegConstraint<"$dstin = $dst">;
373 //===----------------------------------------------------------------------===//
374 // FP Conditional moves.
377 def FCPYDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
378 "fcpyd", " $dst, $true",
379 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
380 RegConstraint<"$false = $dst">;
382 def FCPYScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
383 "fcpys", " $dst, $true",
384 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
385 RegConstraint<"$false = $dst">;
387 def FNEGDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
388 "fnegd", " $dst, $true",
389 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
390 RegConstraint<"$false = $dst">;
392 def FNEGScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
393 "fnegs", " $dst, $true",
394 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
395 RegConstraint<"$false = $dst">;