1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
33 //===----------------------------------------------------------------------===//
34 // Operand Definitions.
38 def vfp_f32imm : Operand<f32>,
39 PatLeaf<(f32 fpimm), [{
40 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
42 let PrintMethod = "printVFPf32ImmOperand";
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
49 let PrintMethod = "printVFPf64ImmOperand";
53 //===----------------------------------------------------------------------===//
54 // Load / store Instructions.
57 let canFoldAsLoad = 1, isReMaterializable = 1 in {
58 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
60 [(set DPR:$dst, (f64 (load addrmode5:$addr)))]>;
62 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
63 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
64 [(set SPR:$dst, (load addrmode5:$addr))]>;
67 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
68 IIC_fpStore64, "vstr", ".64\t$src, $addr",
69 [(store (f64 DPR:$src), addrmode5:$addr)]>;
71 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
72 IIC_fpStore32, "vstr", ".32\t$src, $addr",
73 [(store SPR:$src, addrmode5:$addr)]>;
75 //===----------------------------------------------------------------------===//
76 // Load / store multiple Instructions.
79 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
80 def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
81 variable_ops), IndexModeNone, IIC_fpLoad_m,
82 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
86 def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
87 variable_ops), IndexModeNone, IIC_fpLoad_m,
88 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
92 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
93 reglist:$dsts, variable_ops),
94 IndexModeUpd, IIC_fpLoad_mu,
95 "vldm${addr:submode}${p}\t$addr!, $dsts",
96 "$addr.addr = $wb", []> {
100 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
101 reglist:$dsts, variable_ops),
102 IndexModeUpd, IIC_fpLoad_mu,
103 "vldm${addr:submode}${p}\t$addr!, $dsts",
104 "$addr.addr = $wb", []> {
107 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
109 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
110 def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
111 variable_ops), IndexModeNone, IIC_fpStore_m,
112 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
116 def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
117 variable_ops), IndexModeNone, IIC_fpStore_m,
118 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
122 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
123 reglist:$srcs, variable_ops),
124 IndexModeUpd, IIC_fpStore_mu,
125 "vstm${addr:submode}${p}\t$addr!, $srcs",
126 "$addr.addr = $wb", []> {
130 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
131 reglist:$srcs, variable_ops),
132 IndexModeUpd, IIC_fpStore_mu,
133 "vstm${addr:submode}${p}\t$addr!, $srcs",
134 "$addr.addr = $wb", []> {
137 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
139 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
142 // FIXME: Can these be placed into the base class?
143 class ADbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
144 dag iops, InstrItinClass itin, string opc, string asm,
146 : ADbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
147 // Instruction operands.
152 // Encode instruction operands.
153 let Inst{3-0} = Dm{3-0};
155 let Inst{19-16} = Dn{3-0};
157 let Inst{15-12} = Dd{3-0};
158 let Inst{22} = Dd{4};
161 class ADuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
162 bits<2> opcod4, bit opcod5, dag oops, dag iops,
163 InstrItinClass itin, string opc, string asm,
165 : ADuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
167 // Instruction operands.
171 // Encode instruction operands.
172 let Inst{3-0} = Dm{3-0};
174 let Inst{15-12} = Dd{3-0};
175 let Inst{22} = Dd{4};
178 class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
179 dag iops, InstrItinClass itin, string opc, string asm,
181 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
182 // Instruction operands.
187 // Encode instruction operands.
188 let Inst{3-0} = Sm{4-1};
190 let Inst{19-16} = Sn{4-1};
192 let Inst{15-12} = Sd{4-1};
193 let Inst{22} = Sd{0};
196 class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
197 dag iops, InstrItinClass itin, string opc, string asm,
199 : ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
200 // Instruction operands.
205 // Encode instruction operands.
206 let Inst{3-0} = Sm{4-1};
208 let Inst{19-16} = Sn{4-1};
210 let Inst{15-12} = Sd{4-1};
211 let Inst{22} = Sd{0};
214 class ASuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
215 bits<2> opcod4, bit opcod5, dag oops, dag iops,
216 InstrItinClass itin, string opc, string asm,
218 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
220 // Instruction operands.
224 // Encode instruction operands.
225 let Inst{3-0} = Sm{4-1};
227 let Inst{15-12} = Sd{4-1};
228 let Inst{22} = Sd{0};
231 class ASuIn_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
232 bits<2> opcod4, bit opcod5, dag oops, dag iops,
233 InstrItinClass itin, string opc, string asm,
235 : ASuIn<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
237 // Instruction operands.
241 // Encode instruction operands.
242 let Inst{3-0} = Sm{4-1};
244 let Inst{15-12} = Sd{4-1};
245 let Inst{22} = Sd{0};
248 //===----------------------------------------------------------------------===//
249 // FP Binary Operations.
252 def VADDD : ADbI_Encode<0b11100, 0b11, 0, 0,
253 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
254 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
255 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
257 def VADDS : ASbIn_Encode<0b11100, 0b11, 0, 0,
258 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
259 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
260 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
262 def VSUBD : ADbI_Encode<0b11100, 0b11, 1, 0,
263 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
264 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
265 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
267 def VSUBS : ASbIn_Encode<0b11100, 0b11, 1, 0,
268 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
269 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
270 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
272 def VDIVD : ADbI_Encode<0b11101, 0b00, 0, 0,
273 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
274 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
275 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
277 def VDIVS : ASbI_Encode<0b11101, 0b00, 0, 0,
278 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
279 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
280 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
282 def VMULD : ADbI_Encode<0b11100, 0b10, 0, 0,
283 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
284 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
285 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
287 def VMULS : ASbIn_Encode<0b11100, 0b10, 0, 0,
288 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
289 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
290 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
292 def VNMULD : ADbI_Encode<0b11100, 0b10, 1, 0,
293 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
294 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
295 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
297 def VNMULS : ASbI_Encode<0b11100, 0b10, 1, 0,
298 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
299 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
300 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
302 // Match reassociated forms only if not sign dependent rounding.
303 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
304 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
305 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
306 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
308 // These are encoded as unary instructions.
309 let Defs = [FPSCR] in {
310 def VCMPED : ADuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
311 (outs), (ins DPR:$Dd, DPR:$Dm),
312 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
313 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
315 def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
316 (outs), (ins SPR:$Sd, SPR:$Sm),
317 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
318 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
320 // FIXME: Verify encoding after integrated assembler is working.
321 def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
322 (outs), (ins DPR:$Dd, DPR:$Dm),
323 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
324 [/* For disassembly only; pattern left blank */]>;
326 def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
327 (outs), (ins SPR:$Sd, SPR:$Sm),
328 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
329 [/* For disassembly only; pattern left blank */]>;
332 //===----------------------------------------------------------------------===//
333 // FP Unary Operations.
336 def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
337 (outs DPR:$Dd), (ins DPR:$Dm),
338 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
339 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
341 def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
342 (outs SPR:$Sd), (ins SPR:$Sm),
343 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
344 [(set SPR:$Sd, (fabs SPR:$Sm))]>;
346 let Defs = [FPSCR] in {
347 def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
348 (outs), (ins DPR:$Dd),
349 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
350 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
351 let Inst{3-0} = 0b0000;
355 def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
356 (outs), (ins SPR:$Sd),
357 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
358 [(arm_cmpfp0 SPR:$Sd)]> {
359 let Inst{3-0} = 0b0000;
363 // FIXME: Verify encoding after integrated assembler is working.
364 def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
365 (outs), (ins DPR:$Dd),
366 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
367 [/* For disassembly only; pattern left blank */]> {
368 let Inst{3-0} = 0b0000;
372 def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
373 (outs), (ins SPR:$Sd),
374 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
375 [/* For disassembly only; pattern left blank */]> {
376 let Inst{3-0} = 0b0000;
381 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
382 (outs DPR:$Dd), (ins SPR:$Sm),
383 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
384 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
385 // Instruction operands.
389 // Encode instruction operands.
390 let Inst{3-0} = Sm{4-1};
392 let Inst{15-12} = Dd{3-0};
393 let Inst{22} = Dd{4};
396 // Special case encoding: bits 11-8 is 0b1011.
397 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
398 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
399 [(set SPR:$Sd, (fround DPR:$Dm))]> {
400 // Instruction operands.
404 // Encode instruction operands.
405 let Inst{3-0} = Dm{3-0};
407 let Inst{15-12} = Sd{4-1};
408 let Inst{22} = Sd{0};
410 let Inst{27-23} = 0b11101;
411 let Inst{21-16} = 0b110111;
412 let Inst{11-8} = 0b1011;
413 let Inst{7-6} = 0b11;
417 // Between half-precision and single-precision. For disassembly only.
419 // FIXME: Verify encoding after integrated assembler is working.
420 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
421 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
422 [/* For disassembly only; pattern left blank */]>;
424 def : ARMPat<(f32_to_f16 SPR:$a),
425 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
427 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
428 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
429 [/* For disassembly only; pattern left blank */]>;
431 def : ARMPat<(f16_to_f32 GPR:$a),
432 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
434 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
435 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
436 [/* For disassembly only; pattern left blank */]>;
438 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
439 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
440 [/* For disassembly only; pattern left blank */]>;
442 def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
443 (outs DPR:$Dd), (ins DPR:$Dm),
444 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
445 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
447 def VNEGS : ASuIn_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
448 (outs SPR:$Sd), (ins SPR:$Sm),
449 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
450 [(set SPR:$Sd, (fneg SPR:$Sm))]>;
452 def VSQRTD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
453 (outs DPR:$Dd), (ins DPR:$Dm),
454 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
455 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
457 def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
458 (outs SPR:$Sd), (ins SPR:$Sm),
459 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
460 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
462 let neverHasSideEffects = 1 in {
463 def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
464 (outs DPR:$Dd), (ins DPR:$Dm),
465 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
467 def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
468 (outs SPR:$Sd), (ins SPR:$Sm),
469 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
470 } // neverHasSideEffects
472 //===----------------------------------------------------------------------===//
473 // FP <-> GPR Copies. Int <-> FP Conversions.
476 def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
477 IIC_fpMOVSI, "vmov", "\t$dst, $src",
478 [(set GPR:$dst, (bitconvert SPR:$src))]>;
480 def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
481 IIC_fpMOVIS, "vmov", "\t$dst, $src",
482 [(set SPR:$dst, (bitconvert GPR:$src))]>;
484 let neverHasSideEffects = 1 in {
485 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
486 (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
487 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src",
488 [/* FIXME: Can't write pattern for multiple result instr*/]> {
489 let Inst{7-6} = 0b00;
492 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
493 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
494 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
495 [/* For disassembly only; pattern left blank */]> {
496 let Inst{7-6} = 0b00;
498 } // neverHasSideEffects
503 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
504 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
505 IIC_fpMOVID, "vmov", "\t$dst, $src1, $src2",
506 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
507 let Inst{7-6} = 0b00;
510 let neverHasSideEffects = 1 in
511 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
512 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
513 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
514 [/* For disassembly only; pattern left blank */]> {
515 let Inst{7-6} = 0b00;
521 // FMRX: SPR system reg -> GPR
523 // FMXR: GPR -> VFP system reg
528 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
529 bits<4> opcod4, dag oops, dag iops,
530 InstrItinClass itin, string opc, string asm,
532 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
534 // Instruction operands.
538 // Encode instruction operands.
539 let Inst{3-0} = Sm{4-1};
541 let Inst{15-12} = Dd{3-0};
542 let Inst{22} = Dd{4};
545 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
546 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
547 string opc, string asm, list<dag> pattern>
548 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
550 // Instruction operands.
554 // Encode instruction operands.
555 let Inst{3-0} = Sm{4-1};
557 let Inst{15-12} = Sd{4-1};
558 let Inst{22} = Sd{0};
561 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
562 (outs DPR:$Dd), (ins SPR:$Sm),
563 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
564 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
565 let Inst{7} = 1; // s32
568 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
569 (outs SPR:$Sd),(ins SPR:$Sm),
570 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
571 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
572 let Inst{7} = 1; // s32
575 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
576 (outs DPR:$Dd), (ins SPR:$Sm),
577 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
578 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
579 let Inst{7} = 0; // u32
582 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
583 (outs SPR:$Sd), (ins SPR:$Sm),
584 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
585 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
586 let Inst{7} = 0; // u32
591 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
592 bits<4> opcod4, dag oops, dag iops,
593 InstrItinClass itin, string opc, string asm,
595 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
597 // Instruction operands.
601 // Encode instruction operands.
602 let Inst{3-0} = Dm{3-0};
604 let Inst{15-12} = Sd{4-1};
605 let Inst{22} = Sd{0};
608 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
609 bits<4> opcod4, dag oops, dag iops,
610 InstrItinClass itin, string opc, string asm,
612 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
614 // Instruction operands.
618 // Encode instruction operands.
619 let Inst{3-0} = Sm{4-1};
621 let Inst{15-12} = Sd{4-1};
622 let Inst{22} = Sd{0};
625 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
626 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
627 (outs SPR:$Sd), (ins DPR:$Dm),
628 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
629 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
630 let Inst{7} = 1; // Z bit
633 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
634 (outs SPR:$Sd), (ins SPR:$Sm),
635 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
636 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
637 let Inst{7} = 1; // Z bit
640 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
641 (outs SPR:$Sd), (ins DPR:$Dm),
642 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
643 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
644 let Inst{7} = 1; // Z bit
647 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
648 (outs SPR:$Sd), (ins SPR:$Sm),
649 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
650 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
651 let Inst{7} = 1; // Z bit
654 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
655 // For disassembly only.
656 let Uses = [FPSCR] in {
657 // FIXME: Verify encoding after integrated assembler is working.
658 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
659 (outs SPR:$Sd), (ins DPR:$Dm),
660 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
661 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
662 let Inst{7} = 0; // Z bit
665 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
666 (outs SPR:$Sd), (ins SPR:$Sm),
667 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
668 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
669 let Inst{7} = 0; // Z bit
672 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
673 (outs SPR:$Sd), (ins DPR:$Dm),
674 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
675 [(set SPR:$Sd, (int_arm_vcvtru (f64 DPR:$Dm)))]> {
676 let Inst{7} = 0; // Z bit
679 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
680 (outs SPR:$Sd), (ins SPR:$Sm),
681 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
682 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
683 let Inst{7} = 0; // Z bit
687 // Convert between floating-point and fixed-point
688 // Data type for fixed-point naming convention:
689 // S16 (U=0, sx=0) -> SH
690 // U16 (U=1, sx=0) -> UH
691 // S32 (U=0, sx=1) -> SL
692 // U32 (U=1, sx=1) -> UL
694 let Constraints = "$a = $dst" in {
696 // FP to Fixed-Point:
698 let isCodeGenOnly = 1 in {
699 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
700 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
701 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
702 [/* For disassembly only; pattern left blank */]>;
704 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
705 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
706 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
707 [/* For disassembly only; pattern left blank */]>;
709 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
710 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
711 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
712 [/* For disassembly only; pattern left blank */]>;
714 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
715 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
716 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
717 [/* For disassembly only; pattern left blank */]>;
719 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
720 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
721 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
722 [/* For disassembly only; pattern left blank */]>;
724 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
725 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
726 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
727 [/* For disassembly only; pattern left blank */]>;
729 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
730 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
731 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
732 [/* For disassembly only; pattern left blank */]>;
734 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
735 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
736 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
737 [/* For disassembly only; pattern left blank */]>;
740 // Fixed-Point to FP:
742 let isCodeGenOnly = 1 in {
743 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
744 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
745 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
746 [/* For disassembly only; pattern left blank */]>;
748 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
749 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
750 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
751 [/* For disassembly only; pattern left blank */]>;
753 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
754 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
755 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
756 [/* For disassembly only; pattern left blank */]>;
758 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
759 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
760 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
761 [/* For disassembly only; pattern left blank */]>;
763 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
764 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
765 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
766 [/* For disassembly only; pattern left blank */]>;
768 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
769 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
770 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
771 [/* For disassembly only; pattern left blank */]>;
773 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
774 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
775 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
776 [/* For disassembly only; pattern left blank */]>;
778 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
779 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
780 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
781 [/* For disassembly only; pattern left blank */]>;
784 } // End of 'let Constraints = "$src = $dst" in'
786 //===----------------------------------------------------------------------===//
787 // FP FMA Operations.
790 def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
791 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
792 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
793 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
794 (f64 DPR:$dstin)))]>,
795 RegConstraint<"$dstin = $dst">;
797 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
798 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
799 IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
800 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
801 RegConstraint<"$dstin = $dst">;
803 def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
804 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
805 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
806 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
807 (f64 DPR:$dstin)))]>,
808 RegConstraint<"$dstin = $dst">;
810 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
811 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
812 IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
813 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
814 RegConstraint<"$dstin = $dst">;
816 def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
817 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
818 IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
819 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
820 (f64 DPR:$dstin)))]>,
821 RegConstraint<"$dstin = $dst">;
823 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
824 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
825 IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
826 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
827 RegConstraint<"$dstin = $dst">;
829 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
830 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
831 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
832 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
834 def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
835 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
836 IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
837 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),
838 (f64 DPR:$dstin)))]>,
839 RegConstraint<"$dstin = $dst">;
841 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
842 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
843 IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
844 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
845 RegConstraint<"$dstin = $dst">;
847 //===----------------------------------------------------------------------===//
848 // FP Conditional moves.
851 let neverHasSideEffects = 1 in {
852 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
853 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
854 IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
855 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
856 RegConstraint<"$false = $dst">;
858 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
859 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
860 IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
861 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
862 RegConstraint<"$false = $dst">;
864 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
865 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
866 IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
867 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
868 RegConstraint<"$false = $dst">;
870 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
871 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
872 IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
873 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
874 RegConstraint<"$false = $dst">;
875 } // neverHasSideEffects
877 //===----------------------------------------------------------------------===//
881 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
883 let Defs = [CPSR], Uses = [FPSCR] in
884 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
885 "\tapsr_nzcv, fpscr",
887 let Inst{27-20} = 0b11101111;
888 let Inst{19-16} = 0b0001;
889 let Inst{15-12} = 0b1111;
890 let Inst{11-8} = 0b1010;
895 // FPSCR <-> GPR (for disassembly only)
896 let hasSideEffects = 1, Uses = [FPSCR] in
897 def VMRS : VFPAI<(outs GPR:$dst), (ins), VFPMiscFrm, IIC_fpSTAT,
898 "vmrs", "\t$dst, fpscr",
899 [(set GPR:$dst, (int_arm_get_fpscr))]> {
900 let Inst{27-20} = 0b11101111;
901 let Inst{19-16} = 0b0001;
902 let Inst{11-8} = 0b1010;
907 let Defs = [FPSCR] in
908 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
909 "vmsr", "\tfpscr, $src",
910 [(int_arm_set_fpscr GPR:$src)]> {
911 let Inst{27-20} = 0b11101110;
912 let Inst{19-16} = 0b0001;
913 let Inst{11-8} = 0b1010;
918 // Materialize FP immediates. VFP3 only.
919 let isReMaterializable = 1 in {
920 def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
921 VFPMiscFrm, IIC_fpUNA64,
922 "vmov", ".f64\t$dst, $imm",
923 [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
924 let Inst{27-23} = 0b11101;
925 let Inst{21-20} = 0b11;
926 let Inst{11-9} = 0b101;
928 let Inst{7-4} = 0b0000;
931 def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
932 VFPMiscFrm, IIC_fpUNA32,
933 "vmov", ".f32\t$dst, $imm",
934 [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
935 let Inst{27-23} = 0b11101;
936 let Inst{21-20} = 0b11;
937 let Inst{11-9} = 0b101;
939 let Inst{7-4} = 0b0000;