1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VP instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM VFP Instruction templates.
18 // ARM Float Instruction
19 class ASI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
20 // TODO: Mark the instructions with the appropriate subtarget info.
23 class ASI5<dag ops, string asm, list<dag> pattern>
24 : I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
25 // TODO: Mark the instructions with the appropriate subtarget info.
28 // ARM Double Instruction
29 class ADI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
30 // TODO: Mark the instructions with the appropriate subtarget info.
33 class ADI5<dag ops, string asm, list<dag> pattern>
34 : I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
35 // TODO: Mark the instructions with the appropriate subtarget info.
39 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
41 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
43 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
45 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
48 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
49 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
50 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
51 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
52 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
53 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
54 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
55 def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
57 //===----------------------------------------------------------------------===//
58 // Load / store Instructions.
62 def FLDD : ADI5<(ops DPR:$dst, addrmode5:$addr),
64 [(set DPR:$dst, (load addrmode5:$addr))]>;
66 def FLDS : ASI5<(ops SPR:$dst, addrmode5:$addr),
68 [(set SPR:$dst, (load addrmode5:$addr))]>;
72 def FSTD : ADI5<(ops DPR:$src, addrmode5:$addr),
74 [(store DPR:$src, addrmode5:$addr)]>;
76 def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr),
78 [(store SPR:$src, addrmode5:$addr)]>;
81 //===----------------------------------------------------------------------===//
82 // Load / store multiple Instructions.
86 def FLDMD : ADI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
87 "fldm${addr:submode}d ${addr:base}, $dst1",
90 def FLDMS : ASI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
91 "fldm${addr:submode}s ${addr:base}, $dst1",
96 def FSTMD : ADI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
97 "fstm${addr:submode}d ${addr:base}, $src1",
100 def FSTMS : ASI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
101 "fstm${addr:submode}s ${addr:base}, $src1",
105 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
107 //===----------------------------------------------------------------------===//
108 // FP Binary Operations.
111 def FADDD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
112 "faddd $dst, $a, $b",
113 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
115 def FADDS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
116 "fadds $dst, $a, $b",
117 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
119 def FCMPED : ADI<(ops DPR:$a, DPR:$b),
121 [(arm_cmpfp DPR:$a, DPR:$b)]>;
123 def FCMPES : ASI<(ops SPR:$a, SPR:$b),
125 [(arm_cmpfp SPR:$a, SPR:$b)]>;
127 def FDIVD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
128 "fdivd $dst, $a, $b",
129 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
131 def FDIVS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
132 "fdivs $dst, $a, $b",
133 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
135 def FMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
136 "fmuld $dst, $a, $b",
137 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
139 def FMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
140 "fmuls $dst, $a, $b",
141 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
144 def FNMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
145 "fnmuld $dst, $a, $b",
146 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
148 def FNMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
149 "fnmuls $dst, $a, $b",
150 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
152 def FSUBD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
153 "fsubd $dst, $a, $b",
154 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
156 def FSUBS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
157 "fsubs $dst, $a, $b",
158 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
160 //===----------------------------------------------------------------------===//
161 // FP Unary Operations.
164 def FABSD : ADI<(ops DPR:$dst, DPR:$a),
166 [(set DPR:$dst, (fabs DPR:$a))]>;
168 def FABSS : ASI<(ops SPR:$dst, SPR:$a),
170 [(set SPR:$dst, (fabs SPR:$a))]>;
172 def FCMPEZD : ADI<(ops DPR:$a),
174 [(arm_cmpfp0 DPR:$a)]>;
176 def FCMPEZS : ASI<(ops SPR:$a),
178 [(arm_cmpfp0 SPR:$a)]>;
180 def FCVTDS : ADI<(ops DPR:$dst, SPR:$a),
182 [(set DPR:$dst, (fextend SPR:$a))]>;
184 def FCVTSD : ADI<(ops SPR:$dst, DPR:$a),
186 [(set SPR:$dst, (fround DPR:$a))]>;
188 def FCPYD : ADI<(ops DPR:$dst, DPR:$a),
190 [/*(set DPR:$dst, DPR:$a)*/]>;
192 def FCPYS : ASI<(ops SPR:$dst, SPR:$a),
194 [/*(set SPR:$dst, SPR:$a)*/]>;
196 def FNEGD : ADI<(ops DPR:$dst, DPR:$a),
198 [(set DPR:$dst, (fneg DPR:$a))]>;
200 def FNEGS : ASI<(ops SPR:$dst, SPR:$a),
202 [(set SPR:$dst, (fneg SPR:$a))]>;
204 def FSQRTD : ADI<(ops DPR:$dst, DPR:$a),
206 [(set DPR:$dst, (fsqrt DPR:$a))]>;
208 def FSQRTS : ASI<(ops SPR:$dst, SPR:$a),
210 [(set SPR:$dst, (fsqrt SPR:$a))]>;
212 //===----------------------------------------------------------------------===//
213 // FP <-> GPR Copies. Int <-> FP Conversions.
216 def IMPLICIT_DEF_SPR : PseudoInst<(ops SPR:$rD),
217 "@ IMPLICIT_DEF_SPR $rD",
218 [(set SPR:$rD, (undef))]>;
219 def IMPLICIT_DEF_DPR : PseudoInst<(ops DPR:$rD),
220 "@ IMPLICIT_DEF_DPR $rD",
221 [(set DPR:$rD, (undef))]>;
223 def FMRS : ASI<(ops GPR:$dst, SPR:$src),
225 [(set GPR:$dst, (bitconvert SPR:$src))]>;
227 def FMSR : ASI<(ops SPR:$dst, GPR:$src),
229 [(set SPR:$dst, (bitconvert GPR:$src))]>;
232 def FMRRD : ADI<(ops GPR:$dst1, GPR:$dst2, DPR:$src),
233 "fmrrd $dst1, $dst2, $src",
234 [/* FIXME: Can't write pattern for multiple result instr*/]>;
239 def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
240 "fmdrr $dst, $src1, $src2",
241 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
246 // FMRX : SPR system reg -> GPR
251 def FMSTAT : ASI<(ops), "fmstat", [(arm_fmstat)]>;
253 // FMXR: GPR -> VFP Sstem reg
258 def FSITOD : ADI<(ops DPR:$dst, SPR:$a),
260 [(set DPR:$dst, (arm_sitof SPR:$a))]>;
262 def FSITOS : ASI<(ops SPR:$dst, SPR:$a),
264 [(set SPR:$dst, (arm_sitof SPR:$a))]>;
266 def FUITOD : ADI<(ops DPR:$dst, SPR:$a),
268 [(set DPR:$dst, (arm_uitof SPR:$a))]>;
270 def FUITOS : ASI<(ops SPR:$dst, SPR:$a),
272 [(set SPR:$dst, (arm_uitof SPR:$a))]>;
275 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
277 def FTOSIZD : ADI<(ops SPR:$dst, DPR:$a),
279 [(set SPR:$dst, (arm_ftosi DPR:$a))]>;
281 def FTOSIZS : ASI<(ops SPR:$dst, SPR:$a),
283 [(set SPR:$dst, (arm_ftosi SPR:$a))]>;
285 def FTOUIZD : ADI<(ops SPR:$dst, DPR:$a),
287 [(set SPR:$dst, (arm_ftoui DPR:$a))]>;
289 def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a),
291 [(set SPR:$dst, (arm_ftoui SPR:$a))]>;
293 //===----------------------------------------------------------------------===//
294 // FP FMA Operations.
297 def FMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
298 "fmacd $dst, $a, $b",
299 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
300 RegConstraint<"$dstin = $dst">;
302 def FMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
303 "fmacs $dst, $a, $b",
304 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
305 RegConstraint<"$dstin = $dst">;
307 def FMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
308 "fmscd $dst, $a, $b",
309 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
310 RegConstraint<"$dstin = $dst">;
312 def FMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
313 "fmscs $dst, $a, $b",
314 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
315 RegConstraint<"$dstin = $dst">;
317 def FNMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
318 "fnmacd $dst, $a, $b",
319 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
320 RegConstraint<"$dstin = $dst">;
322 def FNMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
323 "fnmacs $dst, $a, $b",
324 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
325 RegConstraint<"$dstin = $dst">;
327 def FNMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
328 "fnmscd $dst, $a, $b",
329 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
330 RegConstraint<"$dstin = $dst">;
332 def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
333 "fnmscs $dst, $a, $b",
334 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
335 RegConstraint<"$dstin = $dst">;
337 //===----------------------------------------------------------------------===//
338 // FP Conditional moves.
341 def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
342 "fcpyd$cc $dst, $true",
343 [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
344 RegConstraint<"$false = $dst">;
346 def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
347 "fcpys$cc $dst, $true",
348 [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
349 RegConstraint<"$false = $dst">;
351 def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
352 "fnegd$cc $dst, $true",
353 [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
354 RegConstraint<"$false = $dst">;
356 def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
357 "fnegs$cc $dst, $true",
358 [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
359 RegConstraint<"$false = $dst">;