1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
33 //===----------------------------------------------------------------------===//
34 // Operand Definitions.
38 def vfp_f32imm : Operand<f32>,
39 PatLeaf<(f32 fpimm), [{
40 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
42 let PrintMethod = "printVFPf32ImmOperand";
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
49 let PrintMethod = "printVFPf64ImmOperand";
53 //===----------------------------------------------------------------------===//
54 // Load / store Instructions.
57 let canFoldAsLoad = 1, isReMaterializable = 1 in {
58 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
60 [(set DPR:$dst, (f64 (load addrmode5:$addr)))]>;
62 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
63 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
64 [(set SPR:$dst, (load addrmode5:$addr))]>;
67 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
68 IIC_fpStore64, "vstr", ".64\t$src, $addr",
69 [(store (f64 DPR:$src), addrmode5:$addr)]>;
71 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
72 IIC_fpStore32, "vstr", ".32\t$src, $addr",
73 [(store SPR:$src, addrmode5:$addr)]>;
75 //===----------------------------------------------------------------------===//
76 // Load / store multiple Instructions.
79 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
80 def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
81 variable_ops), IndexModeNone, IIC_fpLoadm,
82 "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> {
86 def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
87 variable_ops), IndexModeNone, IIC_fpLoadm,
88 "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> {
92 def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
93 reglist:$dsts, variable_ops),
94 IndexModeUpd, IIC_fpLoadm,
95 "vldm${addr:submode}${p}\t${addr:base}, $dsts",
96 "$addr.base = $wb", []> {
100 def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
101 reglist:$dsts, variable_ops),
102 IndexModeUpd, IIC_fpLoadm,
103 "vldm${addr:submode}${p}\t${addr:base}, $dsts",
104 "$addr.base = $wb", []> {
107 } // mayLoad, hasExtraDefRegAllocReq
109 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
110 def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
111 variable_ops), IndexModeNone, IIC_fpStorem,
112 "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> {
116 def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
117 variable_ops), IndexModeNone, IIC_fpStorem,
118 "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> {
122 def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
123 reglist:$srcs, variable_ops),
124 IndexModeUpd, IIC_fpStorem,
125 "vstm${addr:submode}${p}\t${addr:base}, $srcs",
126 "$addr.base = $wb", []> {
130 def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
131 reglist:$srcs, variable_ops),
132 IndexModeUpd, IIC_fpStorem,
133 "vstm${addr:submode}${p}\t${addr:base}, $srcs",
134 "$addr.base = $wb", []> {
137 } // mayStore, hasExtraSrcRegAllocReq
139 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
141 //===----------------------------------------------------------------------===//
142 // FP Binary Operations.
145 def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
146 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
147 [(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
149 def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
150 IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
151 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
153 // These are encoded as unary instructions.
154 let Defs = [FPSCR] in {
155 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$a, DPR:$b),
156 IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
157 [(arm_cmpfp DPR:$a, (f64 DPR:$b))]>;
159 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
160 IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
161 [/* For disassembly only; pattern left blank */]>;
163 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins SPR:$a, SPR:$b),
164 IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
165 [(arm_cmpfp SPR:$a, SPR:$b)]>;
167 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
168 IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
169 [/* For disassembly only; pattern left blank */]>;
172 def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
173 IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
174 [(set DPR:$dst, (fdiv DPR:$a, (f64 DPR:$b)))]>;
176 def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
177 IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
178 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
180 def VMULD : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
181 IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
182 [(set DPR:$dst, (fmul DPR:$a, (f64 DPR:$b)))]>;
184 def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
185 IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
186 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
188 def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
189 IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
190 [(set DPR:$dst, (fneg (fmul DPR:$a, (f64 DPR:$b))))]>;
192 def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
193 IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
194 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
196 // Match reassociated forms only if not sign dependent rounding.
197 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
198 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
199 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
200 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
203 def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
204 IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
205 [(set DPR:$dst, (fsub DPR:$a, (f64 DPR:$b)))]>;
207 def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
208 IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
209 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
211 //===----------------------------------------------------------------------===//
212 // FP Unary Operations.
215 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
216 IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
217 [(set DPR:$dst, (fabs (f64 DPR:$a)))]>;
219 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
220 IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
221 [(set SPR:$dst, (fabs SPR:$a))]>;
223 let Defs = [FPSCR] in {
224 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a),
225 IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
226 [(arm_cmpfp0 (f64 DPR:$a))]>;
228 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
229 IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
230 [/* For disassembly only; pattern left blank */]>;
232 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins SPR:$a),
233 IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
234 [(arm_cmpfp0 SPR:$a)]>;
236 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
237 IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
238 [/* For disassembly only; pattern left blank */]>;
241 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, (outs DPR:$dst), (ins SPR:$a),
242 IIC_fpCVTDS, "vcvt", ".f64.f32\t$dst, $a",
243 [(set DPR:$dst, (fextend SPR:$a))]>;
245 // Special case encoding: bits 11-8 is 0b1011.
246 def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
247 IIC_fpCVTSD, "vcvt", ".f32.f64\t$dst, $a",
248 [(set SPR:$dst, (fround DPR:$a))]> {
249 let Inst{27-23} = 0b11101;
250 let Inst{21-16} = 0b110111;
251 let Inst{11-8} = 0b1011;
252 let Inst{7-6} = 0b11;
256 // Between half-precision and single-precision. For disassembly only.
258 def VCVTBSH : ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
259 /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f32.f16\t$dst, $a",
260 [/* For disassembly only; pattern left blank */]>;
262 def VCVTBHS : ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
263 /* FIXME */ IIC_fpCVTDS, "vcvtb", ".f16.f32\t$dst, $a",
264 [/* For disassembly only; pattern left blank */]>;
266 def VCVTTSH : ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
267 /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f32.f16\t$dst, $a",
268 [/* For disassembly only; pattern left blank */]>;
270 def VCVTTHS : ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
271 /* FIXME */ IIC_fpCVTDS, "vcvtt", ".f16.f32\t$dst, $a",
272 [/* For disassembly only; pattern left blank */]>;
274 let neverHasSideEffects = 1 in {
275 def VMOVD: ADuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
276 IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
278 def VMOVS: ASuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
279 IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
280 } // neverHasSideEffects
282 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
283 IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
284 [(set DPR:$dst, (fneg (f64 DPR:$a)))]>;
286 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
287 IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
288 [(set SPR:$dst, (fneg SPR:$a))]>;
290 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
291 IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
292 [(set DPR:$dst, (fsqrt (f64 DPR:$a)))]>;
294 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
295 IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
296 [(set SPR:$dst, (fsqrt SPR:$a))]>;
298 //===----------------------------------------------------------------------===//
299 // FP <-> GPR Copies. Int <-> FP Conversions.
302 def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
303 IIC_VMOVSI, "vmov", "\t$dst, $src",
304 [(set GPR:$dst, (bitconvert SPR:$src))]>;
306 def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
307 IIC_VMOVIS, "vmov", "\t$dst, $src",
308 [(set SPR:$dst, (bitconvert GPR:$src))]>;
310 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
311 (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
312 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src",
313 [/* FIXME: Can't write pattern for multiple result instr*/]> {
314 let Inst{7-6} = 0b00;
317 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
318 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
319 IIC_VMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
320 [/* For disassembly only; pattern left blank */]> {
321 let Inst{7-6} = 0b00;
327 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
328 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
329 IIC_VMOVID, "vmov", "\t$dst, $src1, $src2",
330 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
331 let Inst{7-6} = 0b00;
334 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
335 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
336 IIC_VMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
337 [/* For disassembly only; pattern left blank */]> {
338 let Inst{7-6} = 0b00;
344 // FMRX : SPR system reg -> GPR
348 // FMXR: GPR -> VFP Sstem reg
353 def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
354 (outs DPR:$dst), (ins SPR:$a),
355 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
356 [(set DPR:$dst, (f64 (arm_sitof SPR:$a)))]> {
357 let Inst{7} = 1; // s32
360 def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
361 (outs SPR:$dst),(ins SPR:$a),
362 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
363 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
364 let Inst{7} = 1; // s32
367 def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
368 (outs DPR:$dst), (ins SPR:$a),
369 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
370 [(set DPR:$dst, (f64 (arm_uitof SPR:$a)))]> {
371 let Inst{7} = 0; // u32
374 def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
375 (outs SPR:$dst), (ins SPR:$a),
376 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
377 [(set SPR:$dst, (arm_uitof SPR:$a))]> {
378 let Inst{7} = 0; // u32
382 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
384 def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
385 (outs SPR:$dst), (ins DPR:$a),
386 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
387 [(set SPR:$dst, (arm_ftosi (f64 DPR:$a)))]> {
388 let Inst{7} = 1; // Z bit
391 def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
392 (outs SPR:$dst), (ins SPR:$a),
393 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
394 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
395 let Inst{7} = 1; // Z bit
398 def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
399 (outs SPR:$dst), (ins DPR:$a),
400 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
401 [(set SPR:$dst, (arm_ftoui (f64 DPR:$a)))]> {
402 let Inst{7} = 1; // Z bit
405 def VTOUIZS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
406 (outs SPR:$dst), (ins SPR:$a),
407 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
408 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
409 let Inst{7} = 1; // Z bit
412 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
413 // For disassembly only.
415 def VTOSIRD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
416 (outs SPR:$dst), (ins DPR:$a),
417 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$dst, $a",
418 [/* For disassembly only; pattern left blank */]> {
419 let Inst{7} = 0; // Z bit
422 def VTOSIRS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
423 (outs SPR:$dst), (ins SPR:$a),
424 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$dst, $a",
425 [/* For disassembly only; pattern left blank */]> {
426 let Inst{7} = 0; // Z bit
429 def VTOUIRD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
430 (outs SPR:$dst), (ins DPR:$a),
431 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$dst, $a",
432 [/* For disassembly only; pattern left blank */]> {
433 let Inst{7} = 0; // Z bit
436 def VTOUIRS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
437 (outs SPR:$dst), (ins SPR:$a),
438 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$dst, $a",
439 [/* For disassembly only; pattern left blank */]> {
440 let Inst{7} = 0; // Z bit
443 // Convert between floating-point and fixed-point
444 // Data type for fixed-point naming convention:
445 // S16 (U=0, sx=0) -> SH
446 // U16 (U=1, sx=0) -> UH
447 // S32 (U=0, sx=1) -> SL
448 // U32 (U=1, sx=1) -> UL
450 let Constraints = "$a = $dst" in {
452 // FP to Fixed-Point:
454 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
455 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
456 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
457 [/* For disassembly only; pattern left blank */]>;
459 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
460 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
461 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
462 [/* For disassembly only; pattern left blank */]>;
464 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
465 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
466 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
467 [/* For disassembly only; pattern left blank */]>;
469 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
470 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
471 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
472 [/* For disassembly only; pattern left blank */]>;
474 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
475 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
476 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
477 [/* For disassembly only; pattern left blank */]>;
479 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
480 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
481 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
482 [/* For disassembly only; pattern left blank */]>;
484 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
485 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
486 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
487 [/* For disassembly only; pattern left blank */]>;
489 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
490 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
491 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
492 [/* For disassembly only; pattern left blank */]>;
494 // Fixed-Point to FP:
496 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
497 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
498 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
499 [/* For disassembly only; pattern left blank */]>;
501 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
502 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
503 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
504 [/* For disassembly only; pattern left blank */]>;
506 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
507 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
508 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
509 [/* For disassembly only; pattern left blank */]>;
511 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
512 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
513 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
514 [/* For disassembly only; pattern left blank */]>;
516 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
517 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
518 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
519 [/* For disassembly only; pattern left blank */]>;
521 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
522 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
523 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
524 [/* For disassembly only; pattern left blank */]>;
526 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
527 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
528 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
529 [/* For disassembly only; pattern left blank */]>;
531 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
532 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
533 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
534 [/* For disassembly only; pattern left blank */]>;
536 } // End of 'let Constraints = "$src = $dst" in'
538 //===----------------------------------------------------------------------===//
539 // FP FMA Operations.
542 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
543 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
544 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
545 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
546 (f64 DPR:$dstin)))]>,
547 RegConstraint<"$dstin = $dst">;
549 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
550 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
551 IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
552 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
553 RegConstraint<"$dstin = $dst">;
555 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
556 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
557 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
558 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
559 (f64 DPR:$dstin)))]>,
560 RegConstraint<"$dstin = $dst">;
562 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
563 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
564 IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
565 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
566 RegConstraint<"$dstin = $dst">;
568 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
569 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
570 IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
571 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
572 (f64 DPR:$dstin)))]>,
573 RegConstraint<"$dstin = $dst">;
575 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
576 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
577 IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
578 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
579 RegConstraint<"$dstin = $dst">;
581 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
582 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
583 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
584 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
586 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
587 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
588 IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
589 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),
590 (f64 DPR:$dstin)))]>,
591 RegConstraint<"$dstin = $dst">;
593 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
594 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
595 IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
596 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
597 RegConstraint<"$dstin = $dst">;
599 //===----------------------------------------------------------------------===//
600 // FP Conditional moves.
603 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
604 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
605 IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
606 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
607 RegConstraint<"$false = $dst">;
609 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
610 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
611 IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
612 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
613 RegConstraint<"$false = $dst">;
615 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
616 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
617 IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
618 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
619 RegConstraint<"$false = $dst">;
621 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
622 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
623 IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
624 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
625 RegConstraint<"$false = $dst">;
628 //===----------------------------------------------------------------------===//
632 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
634 let Defs = [CPSR], Uses = [FPSCR] in
635 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
636 "\tapsr_nzcv, fpscr",
638 let Inst{27-20} = 0b11101111;
639 let Inst{19-16} = 0b0001;
640 let Inst{15-12} = 0b1111;
641 let Inst{11-8} = 0b1010;
646 // FPSCR <-> GPR (for disassembly only)
648 let Uses = [FPSCR] in {
649 def VMRS : VFPAI<(outs GPR:$dst), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
651 [/* For disassembly only; pattern left blank */]> {
652 let Inst{27-20} = 0b11101111;
653 let Inst{19-16} = 0b0001;
654 let Inst{11-8} = 0b1010;
660 let Defs = [FPSCR] in {
661 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT, "vmsr",
663 [/* For disassembly only; pattern left blank */]> {
664 let Inst{27-20} = 0b11101110;
665 let Inst{19-16} = 0b0001;
666 let Inst{11-8} = 0b1010;
672 // Materialize FP immediates. VFP3 only.
673 let isReMaterializable = 1 in {
674 def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
675 VFPMiscFrm, IIC_VMOVImm,
676 "vmov", ".f64\t$dst, $imm",
677 [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
678 let Inst{27-23} = 0b11101;
679 let Inst{21-20} = 0b11;
680 let Inst{11-9} = 0b101;
682 let Inst{7-4} = 0b0000;
685 def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
686 VFPMiscFrm, IIC_VMOVImm,
687 "vmov", ".f32\t$dst, $imm",
688 [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
689 let Inst{27-23} = 0b11101;
690 let Inst{21-20} = 0b11;
691 let Inst{11-9} = 0b101;
693 let Inst{7-4} = 0b0000;