1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
33 //===----------------------------------------------------------------------===//
34 // Load / store Instructions.
37 let isSimpleLoad = 1 in {
38 def FLDD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
39 "fldd", " $dst, $addr",
40 [(set DPR:$dst, (load addrmode5:$addr))]>;
42 def FLDS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
43 "flds", " $dst, $addr",
44 [(set SPR:$dst, (load addrmode5:$addr))]>;
47 def FSTD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
48 "fstd", " $src, $addr",
49 [(store DPR:$src, addrmode5:$addr)]>;
51 def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
52 "fsts", " $src, $addr",
53 [(store SPR:$src, addrmode5:$addr)]>;
55 //===----------------------------------------------------------------------===//
56 // Load / store multiple Instructions.
60 def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
62 "fldm${addr:submode}d${p} ${addr:base}, $dst1",
67 def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
69 "fldm${addr:submode}s${p} ${addr:base}, $dst1",
76 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
78 "fstm${addr:submode}d${p} ${addr:base}, $src1",
83 def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
85 "fstm${addr:submode}s${p} ${addr:base}, $src1",
91 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
93 //===----------------------------------------------------------------------===//
94 // FP Binary Operations.
97 def FADDD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
98 "faddd", " $dst, $a, $b",
99 [(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
101 def FADDS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
102 "fadds", " $dst, $a, $b",
103 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
105 def FCMPED : ADbI<0b11101011, (outs), (ins DPR:$a, DPR:$b),
107 [(arm_cmpfp DPR:$a, DPR:$b)]> {
108 let Inst{19-16} = 0b0100;
109 let Inst{7-6} = 0b11;
112 def FCMPES : ASbI<0b11101011, (outs), (ins SPR:$a, SPR:$b),
114 [(arm_cmpfp SPR:$a, SPR:$b)]> {
115 let Inst{19-16} = 0b0100;
116 let Inst{7-6} = 0b11;
119 def FDIVD : ADbI<0b11101000, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
120 "fdivd", " $dst, $a, $b",
121 [(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
123 def FDIVS : ASbI<0b11101000, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
124 "fdivs", " $dst, $a, $b",
125 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
127 def FMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
128 "fmuld", " $dst, $a, $b",
129 [(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
131 def FMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
132 "fmuls", " $dst, $a, $b",
133 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
135 def FNMULD : ADbI<0b11100010, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
136 "fnmuld", " $dst, $a, $b",
137 [(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]> {
141 def FNMULS : ASbI<0b11100010, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
142 "fnmuls", " $dst, $a, $b",
143 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]> {
147 // Match reassociated forms only if not sign dependent rounding.
148 def : Pat<(fmul (fneg DPR:$a), DPR:$b),
149 (FNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
150 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
151 (FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
154 def FSUBD : ADbI<0b11100011, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
155 "fsubd", " $dst, $a, $b",
156 [(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
158 def FSUBS : ASbI<0b11100011, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
159 "fsubs", " $dst, $a, $b",
160 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
162 //===----------------------------------------------------------------------===//
163 // FP Unary Operations.
166 def FABSD : ADuI<0b11101011, 0b0000, 0b1100, (outs DPR:$dst), (ins DPR:$a),
167 "fabsd", " $dst, $a",
168 [(set DPR:$dst, (fabs DPR:$a))]>;
170 def FABSS : ASuI<0b11101011, 0b0000, 0b1100, (outs SPR:$dst), (ins SPR:$a),
171 "fabss", " $dst, $a",
172 [(set SPR:$dst, (fabs SPR:$a))]>;
174 def FCMPEZD : ADuI<0b11101011, 0b0101, 0b1100, (outs), (ins DPR:$a),
176 [(arm_cmpfp0 DPR:$a)]>;
178 def FCMPEZS : ASuI<0b11101011, 0b0101, 0b1100, (outs), (ins SPR:$a),
180 [(arm_cmpfp0 SPR:$a)]>;
182 def FCVTDS : ASuI<0b11101011, 0b0111, 0b1100, (outs DPR:$dst), (ins SPR:$a),
183 "fcvtds", " $dst, $a",
184 [(set DPR:$dst, (fextend SPR:$a))]>;
186 // Special case encoding: bits 11-8 is 0b1011.
187 def FCVTSD : AI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
188 "fcvtsd", " $dst, $a",
189 [(set SPR:$dst, (fround DPR:$a))]> {
190 let Inst{27-23} = 0b11101;
191 let Inst{21-16} = 0b110111;
192 let Inst{11-8} = 0b1011;
193 let Inst{7-4} = 0b1100;
196 def FCPYD : ADuI<0b11101011, 0b0000, 0b0100, (outs DPR:$dst), (ins DPR:$a),
197 "fcpyd", " $dst, $a", []>;
199 def FCPYS : ASuI<0b11101011, 0b0000, 0b0100, (outs SPR:$dst), (ins SPR:$a),
200 "fcpys", " $dst, $a", []>;
202 def FNEGD : ADuI<0b11101011, 0b0001, 0b0100, (outs DPR:$dst), (ins DPR:$a),
203 "fnegd", " $dst, $a",
204 [(set DPR:$dst, (fneg DPR:$a))]>;
206 def FNEGS : ASuI<0b11101011, 0b0001, 0b0100, (outs SPR:$dst), (ins SPR:$a),
207 "fnegs", " $dst, $a",
208 [(set SPR:$dst, (fneg SPR:$a))]>;
210 def FSQRTD : ADuI<0b11101011, 0b0001, 0b1100, (outs DPR:$dst), (ins DPR:$a),
211 "fsqrtd", " $dst, $a",
212 [(set DPR:$dst, (fsqrt DPR:$a))]>;
214 def FSQRTS : ASuI<0b11101011, 0b0001, 0b1100, (outs SPR:$dst), (ins SPR:$a),
215 "fsqrts", " $dst, $a",
216 [(set SPR:$dst, (fsqrt SPR:$a))]>;
218 //===----------------------------------------------------------------------===//
219 // FP <-> GPR Copies. Int <-> FP Conversions.
222 def FMRS : AVConv1I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
223 "fmrs", " $dst, $src",
224 [(set GPR:$dst, (bitconvert SPR:$src))]>;
226 def FMSR : AVConv1I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
227 "fmsr", " $dst, $src",
228 [(set SPR:$dst, (bitconvert GPR:$src))]>;
230 def FMRRD : AVConv1I<0b11000101, 0b1011,
231 (outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
232 "fmrrd", " $dst1, $dst2, $src",
233 [/* FIXME: Can't write pattern for multiple result instr*/]>;
238 def FMDRR : AVConv1I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
239 "fmdrr", " $dst, $src1, $src2",
240 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
245 // FMRX : SPR system reg -> GPR
249 // FMXR: GPR -> VFP Sstem reg
254 def FSITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
255 "fsitod", " $dst, $a",
256 [(set DPR:$dst, (arm_sitof SPR:$a))]> {
257 let Inst{7} = 1; // Z bit
260 def FSITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
261 "fsitos", " $dst, $a",
262 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
263 let Inst{7} = 1; // Z bit
266 def FUITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
267 "fuitod", " $dst, $a",
268 [(set DPR:$dst, (arm_uitof SPR:$a))]> {
269 let Inst{7} = 0; // Z bit
272 def FUITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
273 "fuitos", " $dst, $a",
274 [(set SPR:$dst, (arm_uitof SPR:$a))]> {
275 let Inst{7} = 1; // Z bit
279 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
281 def FTOSIZD : AVConv2I<0b11101011, 0b1101, 0b1011,
282 (outs SPR:$dst), (ins DPR:$a),
283 "ftosizd", " $dst, $a",
284 [(set SPR:$dst, (arm_ftosi DPR:$a))]> {
285 let Inst{7} = 1; // Z bit
288 def FTOSIZS : AVConv2I<0b11101011, 0b1101, 0b1010,
289 (outs SPR:$dst), (ins SPR:$a),
290 "ftosizs", " $dst, $a",
291 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
292 let Inst{7} = 1; // Z bit
295 def FTOUIZD : AVConv2I<0b11101011, 0b1100, 0b1011,
296 (outs SPR:$dst), (ins DPR:$a),
297 "ftouizd", " $dst, $a",
298 [(set SPR:$dst, (arm_ftoui DPR:$a))]> {
299 let Inst{7} = 1; // Z bit
302 def FTOUIZS : AVConv2I<0b11101011, 0b1100, 0b1010,
303 (outs SPR:$dst), (ins SPR:$a),
304 "ftouizs", " $dst, $a",
305 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
306 let Inst{7} = 1; // Z bit
309 //===----------------------------------------------------------------------===//
310 // FP FMA Operations.
313 def FMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
314 "fmacd", " $dst, $a, $b",
315 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
316 RegConstraint<"$dstin = $dst">;
318 def FMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
319 "fmacs", " $dst, $a, $b",
320 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
321 RegConstraint<"$dstin = $dst">;
323 def FMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
324 "fmscd", " $dst, $a, $b",
325 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
326 RegConstraint<"$dstin = $dst">;
328 def FMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
329 "fmscs", " $dst, $a, $b",
330 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
331 RegConstraint<"$dstin = $dst">;
333 def FNMACD : ADbI<0b11100000, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
334 "fnmacd", " $dst, $a, $b",
335 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
336 RegConstraint<"$dstin = $dst"> {
340 def FNMACS : ASbI<0b11100000, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
341 "fnmacs", " $dst, $a, $b",
342 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
343 RegConstraint<"$dstin = $dst"> {
347 def FNMSCD : ADbI<0b11100001, (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
348 "fnmscd", " $dst, $a, $b",
349 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
350 RegConstraint<"$dstin = $dst"> {
354 def FNMSCS : ASbI<0b11100001, (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
355 "fnmscs", " $dst, $a, $b",
356 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
357 RegConstraint<"$dstin = $dst"> {
361 //===----------------------------------------------------------------------===//
362 // FP Conditional moves.
365 def FCPYDcc : ADuI<0b11101011, 0b0000, 0b0100,
366 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
367 "fcpyd", " $dst, $true",
368 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
369 RegConstraint<"$false = $dst">;
371 def FCPYScc : ASuI<0b11101011, 0b0000, 0b0100,
372 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
373 "fcpys", " $dst, $true",
374 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
375 RegConstraint<"$false = $dst">;
377 def FNEGDcc : ADuI<0b11101011, 0b0001, 0b0100,
378 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
379 "fnegd", " $dst, $true",
380 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
381 RegConstraint<"$false = $dst">;
383 def FNEGScc : ASuI<0b11101011, 0b0001, 0b0100,
384 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
385 "fnegs", " $dst, $true",
386 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
387 RegConstraint<"$false = $dst">;
390 //===----------------------------------------------------------------------===//
395 def FMSTAT : AI<(outs), (ins), VFPMiscFrm, "fmstat", "", [(arm_fmstat)]> {
396 let Inst{27-20} = 0b11101111;
397 let Inst{19-16} = 0b0001;
398 let Inst{15-12} = 0b1111;
399 let Inst{11-8} = 0b1010;