1 //===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
15 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
17 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
19 SDTypeProfile<0, 1, [SDTCisFP<0>]>;
21 SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
24 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
25 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
26 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
27 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
28 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag,SDNPOutFlag]>;
29 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
30 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
31 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
33 //===----------------------------------------------------------------------===//
34 // Operand Definitions.
38 def vfp_f32imm : Operand<f32>,
39 PatLeaf<(f32 fpimm), [{
40 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
42 let PrintMethod = "printVFPf32ImmOperand";
45 def vfp_f64imm : Operand<f64>,
46 PatLeaf<(f64 fpimm), [{
47 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
49 let PrintMethod = "printVFPf64ImmOperand";
53 //===----------------------------------------------------------------------===//
54 // Load / store Instructions.
57 let canFoldAsLoad = 1, isReMaterializable = 1 in {
58 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
60 [(set DPR:$dst, (f64 (load addrmode5:$addr)))]>;
62 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
63 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
64 [(set SPR:$dst, (load addrmode5:$addr))]>;
67 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
68 IIC_fpStore64, "vstr", ".64\t$src, $addr",
69 [(store (f64 DPR:$src), addrmode5:$addr)]>;
71 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
72 IIC_fpStore32, "vstr", ".32\t$src, $addr",
73 [(store SPR:$src, addrmode5:$addr)]>;
75 //===----------------------------------------------------------------------===//
76 // Load / store multiple Instructions.
79 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
80 def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
81 variable_ops), IndexModeNone, IIC_fpLoadm,
82 "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> {
86 def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
87 variable_ops), IndexModeNone, IIC_fpLoadm,
88 "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> {
92 def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
93 reglist:$dsts, variable_ops),
94 IndexModeUpd, IIC_fpLoadm,
95 "vldm${addr:submode}${p}\t${addr:base}!, $dsts",
96 "$addr.base = $wb", []> {
100 def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
101 reglist:$dsts, variable_ops),
102 IndexModeUpd, IIC_fpLoadm,
103 "vldm${addr:submode}${p}\t${addr:base}!, $dsts",
104 "$addr.base = $wb", []> {
107 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
109 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
110 def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
111 variable_ops), IndexModeNone, IIC_fpStorem,
112 "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> {
116 def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
117 variable_ops), IndexModeNone, IIC_fpStorem,
118 "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> {
122 def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
123 reglist:$srcs, variable_ops),
124 IndexModeUpd, IIC_fpStorem,
125 "vstm${addr:submode}${p}\t${addr:base}!, $srcs",
126 "$addr.base = $wb", []> {
130 def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
131 reglist:$srcs, variable_ops),
132 IndexModeUpd, IIC_fpStorem,
133 "vstm${addr:submode}${p}\t${addr:base}!, $srcs",
134 "$addr.base = $wb", []> {
137 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
139 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
141 //===----------------------------------------------------------------------===//
142 // FP Binary Operations.
145 def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
146 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
147 [(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
149 def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
150 IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
151 [(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
153 // These are encoded as unary instructions.
154 let Defs = [FPSCR] in {
155 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$a, DPR:$b),
156 IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
157 [(arm_cmpfp DPR:$a, (f64 DPR:$b))]>;
159 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
160 IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
161 [/* For disassembly only; pattern left blank */]>;
163 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins SPR:$a, SPR:$b),
164 IIC_fpCMP32, "vcmpe", ".f32\t$a, $b",
165 [(arm_cmpfp SPR:$a, SPR:$b)]>;
167 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
168 IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
169 [/* For disassembly only; pattern left blank */]>;
172 def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
173 IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
174 [(set DPR:$dst, (fdiv DPR:$a, (f64 DPR:$b)))]>;
176 def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
177 IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
178 [(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
180 def VMULD : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
181 IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
182 [(set DPR:$dst, (fmul DPR:$a, (f64 DPR:$b)))]>;
184 def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
185 IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
186 [(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
188 def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
189 IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
190 [(set DPR:$dst, (fneg (fmul DPR:$a, (f64 DPR:$b))))]>;
192 def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
193 IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
194 [(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
196 // Match reassociated forms only if not sign dependent rounding.
197 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
198 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
199 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
200 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
203 def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
204 IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
205 [(set DPR:$dst, (fsub DPR:$a, (f64 DPR:$b)))]>;
207 def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
208 IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
209 [(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
211 //===----------------------------------------------------------------------===//
212 // FP Unary Operations.
215 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
216 IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
217 [(set DPR:$dst, (fabs (f64 DPR:$a)))]>;
219 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
220 IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
221 [(set SPR:$dst, (fabs SPR:$a))]>;
223 let Defs = [FPSCR] in {
224 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a),
225 IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
226 [(arm_cmpfp0 (f64 DPR:$a))]>;
228 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
229 IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
230 [/* For disassembly only; pattern left blank */]>;
232 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins SPR:$a),
233 IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
234 [(arm_cmpfp0 SPR:$a)]>;
236 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
237 IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
238 [/* For disassembly only; pattern left blank */]>;
241 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, (outs DPR:$dst), (ins SPR:$a),
242 IIC_fpCVTDS, "vcvt", ".f64.f32\t$dst, $a",
243 [(set DPR:$dst, (fextend SPR:$a))]>;
245 // Special case encoding: bits 11-8 is 0b1011.
246 def VCVTSD : VFPAI<(outs SPR:$dst), (ins DPR:$a), VFPUnaryFrm,
247 IIC_fpCVTSD, "vcvt", ".f32.f64\t$dst, $a",
248 [(set SPR:$dst, (fround DPR:$a))]> {
249 let Inst{27-23} = 0b11101;
250 let Inst{21-16} = 0b110111;
251 let Inst{11-8} = 0b1011;
252 let Inst{7-6} = 0b11;
256 // Between half-precision and single-precision. For disassembly only.
258 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
259 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
260 [/* For disassembly only; pattern left blank */]>;
262 def : ARMPat<(f32_to_f16 SPR:$a),
263 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
265 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
266 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
267 [/* For disassembly only; pattern left blank */]>;
269 def : ARMPat<(f16_to_f32 GPR:$a),
270 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
272 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
273 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
274 [/* For disassembly only; pattern left blank */]>;
276 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
277 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
278 [/* For disassembly only; pattern left blank */]>;
280 let neverHasSideEffects = 1 in {
281 def VMOVD: ADuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
282 IIC_fpUNA64, "vmov", ".f64\t$dst, $a", []>;
284 def VMOVS: ASuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
285 IIC_fpUNA32, "vmov", ".f32\t$dst, $a", []>;
286 } // neverHasSideEffects
288 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
289 IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
290 [(set DPR:$dst, (fneg (f64 DPR:$a)))]>;
292 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
293 IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
294 [(set SPR:$dst, (fneg SPR:$a))]>;
296 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
297 IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
298 [(set DPR:$dst, (fsqrt (f64 DPR:$a)))]>;
300 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
301 IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
302 [(set SPR:$dst, (fsqrt SPR:$a))]>;
304 //===----------------------------------------------------------------------===//
305 // FP <-> GPR Copies. Int <-> FP Conversions.
308 def VMOVRS : AVConv2I<0b11100001, 0b1010, (outs GPR:$dst), (ins SPR:$src),
309 IIC_fpMOVSI, "vmov", "\t$dst, $src",
310 [(set GPR:$dst, (bitconvert SPR:$src))]>;
312 def VMOVSR : AVConv4I<0b11100000, 0b1010, (outs SPR:$dst), (ins GPR:$src),
313 IIC_fpMOVIS, "vmov", "\t$dst, $src",
314 [(set SPR:$dst, (bitconvert GPR:$src))]>;
316 let neverHasSideEffects = 1 in {
317 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
318 (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
319 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src",
320 [/* FIXME: Can't write pattern for multiple result instr*/]> {
321 let Inst{7-6} = 0b00;
324 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
325 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
326 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
327 [/* For disassembly only; pattern left blank */]> {
328 let Inst{7-6} = 0b00;
330 } // neverHasSideEffects
335 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
336 (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
337 IIC_fpMOVID, "vmov", "\t$dst, $src1, $src2",
338 [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
339 let Inst{7-6} = 0b00;
342 let neverHasSideEffects = 1 in
343 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
344 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
345 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
346 [/* For disassembly only; pattern left blank */]> {
347 let Inst{7-6} = 0b00;
353 // FMRX : SPR system reg -> GPR
357 // FMXR: GPR -> VFP Sstem reg
362 def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
363 (outs DPR:$dst), (ins SPR:$a),
364 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
365 [(set DPR:$dst, (f64 (arm_sitof SPR:$a)))]> {
366 let Inst{7} = 1; // s32
369 def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
370 (outs SPR:$dst),(ins SPR:$a),
371 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
372 [(set SPR:$dst, (arm_sitof SPR:$a))]> {
373 let Inst{7} = 1; // s32
376 def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
377 (outs DPR:$dst), (ins SPR:$a),
378 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
379 [(set DPR:$dst, (f64 (arm_uitof SPR:$a)))]> {
380 let Inst{7} = 0; // u32
383 def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
384 (outs SPR:$dst), (ins SPR:$a),
385 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
386 [(set SPR:$dst, (arm_uitof SPR:$a))]> {
387 let Inst{7} = 0; // u32
391 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
393 def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
394 (outs SPR:$dst), (ins DPR:$a),
395 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
396 [(set SPR:$dst, (arm_ftosi (f64 DPR:$a)))]> {
397 let Inst{7} = 1; // Z bit
400 def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
401 (outs SPR:$dst), (ins SPR:$a),
402 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
403 [(set SPR:$dst, (arm_ftosi SPR:$a))]> {
404 let Inst{7} = 1; // Z bit
407 def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
408 (outs SPR:$dst), (ins DPR:$a),
409 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
410 [(set SPR:$dst, (arm_ftoui (f64 DPR:$a)))]> {
411 let Inst{7} = 1; // Z bit
414 def VTOUIZS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
415 (outs SPR:$dst), (ins SPR:$a),
416 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
417 [(set SPR:$dst, (arm_ftoui SPR:$a))]> {
418 let Inst{7} = 1; // Z bit
421 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
422 // For disassembly only.
423 let Uses = [FPSCR] in {
424 def VTOSIRD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
425 (outs SPR:$dst), (ins DPR:$a),
426 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$dst, $a",
427 [(set SPR:$dst, (int_arm_vcvtr (f64 DPR:$a)))]> {
428 let Inst{7} = 0; // Z bit
431 def VTOSIRS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
432 (outs SPR:$dst), (ins SPR:$a),
433 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$dst, $a",
434 [(set SPR:$dst, (int_arm_vcvtr SPR:$a))]> {
435 let Inst{7} = 0; // Z bit
438 def VTOUIRD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
439 (outs SPR:$dst), (ins DPR:$a),
440 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$dst, $a",
441 [(set SPR:$dst, (int_arm_vcvtru (f64 DPR:$a)))]> {
442 let Inst{7} = 0; // Z bit
445 def VTOUIRS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
446 (outs SPR:$dst), (ins SPR:$a),
447 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$dst, $a",
448 [(set SPR:$dst, (int_arm_vcvtru SPR:$a))]> {
449 let Inst{7} = 0; // Z bit
453 // Convert between floating-point and fixed-point
454 // Data type for fixed-point naming convention:
455 // S16 (U=0, sx=0) -> SH
456 // U16 (U=1, sx=0) -> UH
457 // S32 (U=0, sx=1) -> SL
458 // U32 (U=1, sx=1) -> UL
460 let Constraints = "$a = $dst" in {
462 // FP to Fixed-Point:
464 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
465 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
466 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
467 [/* For disassembly only; pattern left blank */]>;
469 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
470 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
471 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
472 [/* For disassembly only; pattern left blank */]>;
474 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
475 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
476 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
477 [/* For disassembly only; pattern left blank */]>;
479 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
480 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
481 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
482 [/* For disassembly only; pattern left blank */]>;
484 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
485 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
486 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
487 [/* For disassembly only; pattern left blank */]>;
489 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
490 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
491 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
492 [/* For disassembly only; pattern left blank */]>;
494 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
495 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
496 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
497 [/* For disassembly only; pattern left blank */]>;
499 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
500 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
501 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
502 [/* For disassembly only; pattern left blank */]>;
504 // Fixed-Point to FP:
506 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
507 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
508 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
509 [/* For disassembly only; pattern left blank */]>;
511 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
512 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
513 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
514 [/* For disassembly only; pattern left blank */]>;
516 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
517 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
518 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
519 [/* For disassembly only; pattern left blank */]>;
521 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
522 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
523 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
524 [/* For disassembly only; pattern left blank */]>;
526 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
527 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
528 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
529 [/* For disassembly only; pattern left blank */]>;
531 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
532 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
533 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
534 [/* For disassembly only; pattern left blank */]>;
536 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
537 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
538 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
539 [/* For disassembly only; pattern left blank */]>;
541 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
542 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
543 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
544 [/* For disassembly only; pattern left blank */]>;
546 } // End of 'let Constraints = "$src = $dst" in'
548 //===----------------------------------------------------------------------===//
549 // FP FMA Operations.
552 def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
553 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
554 IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
555 [(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
556 (f64 DPR:$dstin)))]>,
557 RegConstraint<"$dstin = $dst">;
559 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
560 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
561 IIC_fpMAC32, "vmla", ".f32\t$dst, $a, $b",
562 [(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
563 RegConstraint<"$dstin = $dst">;
565 def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
566 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
567 IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
568 [(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
569 (f64 DPR:$dstin)))]>,
570 RegConstraint<"$dstin = $dst">;
572 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
573 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
574 IIC_fpMAC32, "vnmls", ".f32\t$dst, $a, $b",
575 [(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
576 RegConstraint<"$dstin = $dst">;
578 def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
579 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
580 IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
581 [(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
582 (f64 DPR:$dstin)))]>,
583 RegConstraint<"$dstin = $dst">;
585 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
586 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
587 IIC_fpMAC32, "vmls", ".f32\t$dst, $a, $b",
588 [(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
589 RegConstraint<"$dstin = $dst">;
591 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
592 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
593 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
594 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
596 def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
597 (outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
598 IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
599 [(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),
600 (f64 DPR:$dstin)))]>,
601 RegConstraint<"$dstin = $dst">;
603 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
604 (outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
605 IIC_fpMAC32, "vnmla", ".f32\t$dst, $a, $b",
606 [(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
607 RegConstraint<"$dstin = $dst">;
609 //===----------------------------------------------------------------------===//
610 // FP Conditional moves.
613 let neverHasSideEffects = 1 in {
614 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
615 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
616 IIC_fpUNA64, "vmov", ".f64\t$dst, $true",
617 [/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
618 RegConstraint<"$false = $dst">;
620 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
621 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
622 IIC_fpUNA32, "vmov", ".f32\t$dst, $true",
623 [/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
624 RegConstraint<"$false = $dst">;
626 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
627 (outs DPR:$dst), (ins DPR:$false, DPR:$true),
628 IIC_fpUNA64, "vneg", ".f64\t$dst, $true",
629 [/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
630 RegConstraint<"$false = $dst">;
632 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
633 (outs SPR:$dst), (ins SPR:$false, SPR:$true),
634 IIC_fpUNA32, "vneg", ".f32\t$dst, $true",
635 [/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
636 RegConstraint<"$false = $dst">;
637 } // neverHasSideEffects
639 //===----------------------------------------------------------------------===//
643 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
645 let Defs = [CPSR], Uses = [FPSCR] in
646 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
647 "\tapsr_nzcv, fpscr",
649 let Inst{27-20} = 0b11101111;
650 let Inst{19-16} = 0b0001;
651 let Inst{15-12} = 0b1111;
652 let Inst{11-8} = 0b1010;
657 // FPSCR <-> GPR (for disassembly only)
658 let hasSideEffects = 1, Uses = [FPSCR] in
659 def VMRS : VFPAI<(outs GPR:$dst), (ins), VFPMiscFrm, IIC_fpSTAT,
660 "vmrs", "\t$dst, fpscr",
661 [(set GPR:$dst, (int_arm_get_fpscr))]> {
662 let Inst{27-20} = 0b11101111;
663 let Inst{19-16} = 0b0001;
664 let Inst{11-8} = 0b1010;
669 let Defs = [FPSCR] in
670 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
671 "vmsr", "\tfpscr, $src",
672 [(int_arm_set_fpscr GPR:$src)]> {
673 let Inst{27-20} = 0b11101110;
674 let Inst{19-16} = 0b0001;
675 let Inst{11-8} = 0b1010;
680 // Materialize FP immediates. VFP3 only.
681 let isReMaterializable = 1 in {
682 def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
683 VFPMiscFrm, IIC_fpUNA64,
684 "vmov", ".f64\t$dst, $imm",
685 [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
686 let Inst{27-23} = 0b11101;
687 let Inst{21-20} = 0b11;
688 let Inst{11-9} = 0b101;
690 let Inst{7-4} = 0b0000;
693 def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
694 VFPMiscFrm, IIC_fpUNA32,
695 "vmov", ".f32\t$dst, $imm",
696 [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
697 let Inst{27-23} = 0b11101;
698 let Inst{21-20} = 0b11;
699 let Inst{11-9} = 0b101;
701 let Inst{7-4} = 0b0000;