1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag, SDNPOutFlag]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
41 def vfp_f64imm : Operand<f64>,
42 PatLeaf<(f64 fpimm), [{
43 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
45 let PrintMethod = "printVFPf64ImmOperand";
49 //===----------------------------------------------------------------------===//
50 // Load / store Instructions.
53 let canFoldAsLoad = 1, isReMaterializable = 1 in {
54 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
55 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
56 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]> {
57 // Instruction operands.
61 // Encode instruction operands.
62 let Inst{23} = addr{16}; // U (add = (U == '1'))
64 let Inst{19-16} = addr{20-17}; // Rn
65 let Inst{15-12} = Dd{3-0};
66 let Inst{7-0} = addr{7-0}; // imm8
69 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
70 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
71 [(set SPR:$dst, (load addrmode5:$addr))]>;
74 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
75 IIC_fpStore64, "vstr", ".64\t$src, $addr",
76 [(store (f64 DPR:$src), addrmode5:$addr)]>;
78 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
79 IIC_fpStore32, "vstr", ".32\t$src, $addr",
80 [(store SPR:$src, addrmode5:$addr)]>;
82 //===----------------------------------------------------------------------===//
83 // Load / store multiple Instructions.
86 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
87 isCodeGenOnly = 1 in {
88 def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
89 reglist:$dsts, variable_ops),
90 IndexModeNone, IIC_fpLoad_m,
91 "vldm${amode}${p}\t$Rn, $dsts", "", []> {
95 def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
96 reglist:$dsts, variable_ops),
97 IndexModeNone, IIC_fpLoad_m,
98 "vldm${amode}${p}\t$Rn, $dsts", "", []> {
102 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
103 reglist:$dsts, variable_ops),
104 IndexModeUpd, IIC_fpLoad_mu,
105 "vldm${amode}${p}\t$Rn!, $dsts",
110 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
111 reglist:$dsts, variable_ops),
112 IndexModeUpd, IIC_fpLoad_mu,
113 "vldm${amode}${p}\t$Rn!, $dsts",
117 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
119 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
120 isCodeGenOnly = 1 in {
121 def VSTMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
122 reglist:$srcs, variable_ops),
123 IndexModeNone, IIC_fpStore_m,
124 "vstm${amode}${p}\t$Rn, $srcs", "", []> {
128 def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
129 reglist:$srcs, variable_ops), IndexModeNone,
131 "vstm${amode}${p}\t$Rn, $srcs", "", []> {
135 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
136 reglist:$srcs, variable_ops),
137 IndexModeUpd, IIC_fpStore_mu,
138 "vstm${amode}${p}\t$Rn!, $srcs",
143 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
144 reglist:$srcs, variable_ops),
145 IndexModeUpd, IIC_fpStore_mu,
146 "vstm${amode}${p}\t$Rn!, $srcs",
150 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
152 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
154 //===----------------------------------------------------------------------===//
155 // FP Binary Operations.
158 def VADDD : ADbI<0b11100, 0b11, 0, 0,
159 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
160 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
161 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
163 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
164 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
165 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
166 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
168 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
169 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
170 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
171 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
173 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
174 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
175 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
176 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
178 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
179 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
180 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
181 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
183 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
184 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
185 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
186 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
188 def VMULD : ADbI<0b11100, 0b10, 0, 0,
189 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
190 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
191 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
193 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
194 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
195 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
196 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
198 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
199 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
200 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
201 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
203 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
204 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
205 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
206 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
208 // Match reassociated forms only if not sign dependent rounding.
209 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
210 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
211 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
212 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
214 // These are encoded as unary instructions.
215 let Defs = [FPSCR] in {
216 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
217 (outs), (ins DPR:$Dd, DPR:$Dm),
218 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
219 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
221 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
222 (outs), (ins SPR:$Sd, SPR:$Sm),
223 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
224 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
226 // FIXME: Verify encoding after integrated assembler is working.
227 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
228 (outs), (ins DPR:$Dd, DPR:$Dm),
229 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
230 [/* For disassembly only; pattern left blank */]>;
232 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
233 (outs), (ins SPR:$Sd, SPR:$Sm),
234 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
235 [/* For disassembly only; pattern left blank */]>;
238 //===----------------------------------------------------------------------===//
239 // FP Unary Operations.
242 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
243 (outs DPR:$Dd), (ins DPR:$Dm),
244 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
245 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
247 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
248 (outs SPR:$Sd), (ins SPR:$Sm),
249 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
250 [(set SPR:$Sd, (fabs SPR:$Sm))]>;
252 let Defs = [FPSCR] in {
253 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
254 (outs), (ins DPR:$Dd),
255 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
256 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
257 let Inst{3-0} = 0b0000;
261 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
262 (outs), (ins SPR:$Sd),
263 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
264 [(arm_cmpfp0 SPR:$Sd)]> {
265 let Inst{3-0} = 0b0000;
269 // FIXME: Verify encoding after integrated assembler is working.
270 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
271 (outs), (ins DPR:$Dd),
272 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
273 [/* For disassembly only; pattern left blank */]> {
274 let Inst{3-0} = 0b0000;
278 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
279 (outs), (ins SPR:$Sd),
280 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
281 [/* For disassembly only; pattern left blank */]> {
282 let Inst{3-0} = 0b0000;
287 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
288 (outs DPR:$Dd), (ins SPR:$Sm),
289 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
290 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
291 // Instruction operands.
295 // Encode instruction operands.
296 let Inst{3-0} = Sm{4-1};
298 let Inst{15-12} = Dd{3-0};
299 let Inst{22} = Dd{4};
302 // Special case encoding: bits 11-8 is 0b1011.
303 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
304 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
305 [(set SPR:$Sd, (fround DPR:$Dm))]> {
306 // Instruction operands.
310 // Encode instruction operands.
311 let Inst{3-0} = Dm{3-0};
313 let Inst{15-12} = Sd{4-1};
314 let Inst{22} = Sd{0};
316 let Inst{27-23} = 0b11101;
317 let Inst{21-16} = 0b110111;
318 let Inst{11-8} = 0b1011;
319 let Inst{7-6} = 0b11;
323 // Between half-precision and single-precision. For disassembly only.
325 // FIXME: Verify encoding after integrated assembler is working.
326 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
327 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
328 [/* For disassembly only; pattern left blank */]>;
330 def : ARMPat<(f32_to_f16 SPR:$a),
331 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
333 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
334 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
335 [/* For disassembly only; pattern left blank */]>;
337 def : ARMPat<(f16_to_f32 GPR:$a),
338 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
340 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
341 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
342 [/* For disassembly only; pattern left blank */]>;
344 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
345 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
346 [/* For disassembly only; pattern left blank */]>;
348 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
349 (outs DPR:$Dd), (ins DPR:$Dm),
350 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
351 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
353 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
354 (outs SPR:$Sd), (ins SPR:$Sm),
355 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
356 [(set SPR:$Sd, (fneg SPR:$Sm))]>;
358 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
359 (outs DPR:$Dd), (ins DPR:$Dm),
360 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
361 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
363 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
364 (outs SPR:$Sd), (ins SPR:$Sm),
365 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
366 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
368 let neverHasSideEffects = 1 in {
369 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
370 (outs DPR:$Dd), (ins DPR:$Dm),
371 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
373 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
374 (outs SPR:$Sd), (ins SPR:$Sm),
375 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
376 } // neverHasSideEffects
378 //===----------------------------------------------------------------------===//
379 // FP <-> GPR Copies. Int <-> FP Conversions.
382 def VMOVRS : AVConv2I<0b11100001, 0b1010,
383 (outs GPR:$Rt), (ins SPR:$Sn),
384 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
385 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
386 // Instruction operands.
390 // Encode instruction operands.
391 let Inst{19-16} = Sn{4-1};
393 let Inst{15-12} = Rt;
395 let Inst{6-5} = 0b00;
396 let Inst{3-0} = 0b0000;
399 def VMOVSR : AVConv4I<0b11100000, 0b1010,
400 (outs SPR:$Sn), (ins GPR:$Rt),
401 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
402 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
403 // Instruction operands.
407 // Encode instruction operands.
408 let Inst{19-16} = Sn{4-1};
410 let Inst{15-12} = Rt;
412 let Inst{6-5} = 0b00;
413 let Inst{3-0} = 0b0000;
416 let neverHasSideEffects = 1 in {
417 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
418 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
419 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
420 [/* FIXME: Can't write pattern for multiple result instr*/]> {
421 // Instruction operands.
426 // Encode instruction operands.
427 let Inst{3-0} = Dm{3-0};
429 let Inst{15-12} = Rt;
430 let Inst{19-16} = Rt2;
432 let Inst{7-6} = 0b00;
435 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
436 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
437 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
438 [/* For disassembly only; pattern left blank */]> {
439 let Inst{7-6} = 0b00;
441 } // neverHasSideEffects
446 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
447 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
448 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
449 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
450 // Instruction operands.
455 // Encode instruction operands.
456 let Inst{3-0} = Dm{3-0};
458 let Inst{15-12} = Rt;
459 let Inst{19-16} = Rt2;
461 let Inst{7-6} = 0b00;
464 let neverHasSideEffects = 1 in
465 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
466 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
467 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
468 [/* For disassembly only; pattern left blank */]> {
469 let Inst{7-6} = 0b00;
475 // FMRX: SPR system reg -> GPR
477 // FMXR: GPR -> VFP system reg
482 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
483 bits<4> opcod4, dag oops, dag iops,
484 InstrItinClass itin, string opc, string asm,
486 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
488 // Instruction operands.
492 // Encode instruction operands.
493 let Inst{3-0} = Sm{4-1};
495 let Inst{15-12} = Dd{3-0};
496 let Inst{22} = Dd{4};
499 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
500 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
501 string opc, string asm, list<dag> pattern>
502 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
504 // Instruction operands.
508 // Encode instruction operands.
509 let Inst{3-0} = Sm{4-1};
511 let Inst{15-12} = Sd{4-1};
512 let Inst{22} = Sd{0};
515 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
516 (outs DPR:$Dd), (ins SPR:$Sm),
517 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
518 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
519 let Inst{7} = 1; // s32
522 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
523 (outs SPR:$Sd),(ins SPR:$Sm),
524 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
525 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
526 let Inst{7} = 1; // s32
529 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
530 (outs DPR:$Dd), (ins SPR:$Sm),
531 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
532 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
533 let Inst{7} = 0; // u32
536 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
537 (outs SPR:$Sd), (ins SPR:$Sm),
538 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
539 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
540 let Inst{7} = 0; // u32
545 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
546 bits<4> opcod4, dag oops, dag iops,
547 InstrItinClass itin, string opc, string asm,
549 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
551 // Instruction operands.
555 // Encode instruction operands.
556 let Inst{3-0} = Dm{3-0};
558 let Inst{15-12} = Sd{4-1};
559 let Inst{22} = Sd{0};
562 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
563 bits<4> opcod4, dag oops, dag iops,
564 InstrItinClass itin, string opc, string asm,
566 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
568 // Instruction operands.
572 // Encode instruction operands.
573 let Inst{3-0} = Sm{4-1};
575 let Inst{15-12} = Sd{4-1};
576 let Inst{22} = Sd{0};
579 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
580 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
581 (outs SPR:$Sd), (ins DPR:$Dm),
582 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
583 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
584 let Inst{7} = 1; // Z bit
587 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
588 (outs SPR:$Sd), (ins SPR:$Sm),
589 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
590 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
591 let Inst{7} = 1; // Z bit
594 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
595 (outs SPR:$Sd), (ins DPR:$Dm),
596 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
597 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
598 let Inst{7} = 1; // Z bit
601 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
602 (outs SPR:$Sd), (ins SPR:$Sm),
603 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
604 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
605 let Inst{7} = 1; // Z bit
608 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
609 // For disassembly only.
610 let Uses = [FPSCR] in {
611 // FIXME: Verify encoding after integrated assembler is working.
612 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
613 (outs SPR:$Sd), (ins DPR:$Dm),
614 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
615 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
616 let Inst{7} = 0; // Z bit
619 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
620 (outs SPR:$Sd), (ins SPR:$Sm),
621 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
622 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
623 let Inst{7} = 0; // Z bit
626 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
627 (outs SPR:$Sd), (ins DPR:$Dm),
628 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
629 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
630 let Inst{7} = 0; // Z bit
633 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
634 (outs SPR:$Sd), (ins SPR:$Sm),
635 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
636 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
637 let Inst{7} = 0; // Z bit
641 // Convert between floating-point and fixed-point
642 // Data type for fixed-point naming convention:
643 // S16 (U=0, sx=0) -> SH
644 // U16 (U=1, sx=0) -> UH
645 // S32 (U=0, sx=1) -> SL
646 // U32 (U=1, sx=1) -> UL
648 // FIXME: Marking these as codegen only seems wrong. They are real
650 let Constraints = "$a = $dst", isCodeGenOnly = 1 in {
652 // FP to Fixed-Point:
654 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
655 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
656 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
657 [/* For disassembly only; pattern left blank */]>;
659 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
660 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
661 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
662 [/* For disassembly only; pattern left blank */]>;
664 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
665 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
666 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
667 [/* For disassembly only; pattern left blank */]>;
669 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
670 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
671 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
672 [/* For disassembly only; pattern left blank */]>;
674 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
675 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
676 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
677 [/* For disassembly only; pattern left blank */]>;
679 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
680 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
681 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
682 [/* For disassembly only; pattern left blank */]>;
684 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
685 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
686 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
687 [/* For disassembly only; pattern left blank */]>;
689 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
690 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
691 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
692 [/* For disassembly only; pattern left blank */]>;
694 // Fixed-Point to FP:
696 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
697 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
698 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
699 [/* For disassembly only; pattern left blank */]>;
701 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
702 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
703 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
704 [/* For disassembly only; pattern left blank */]>;
706 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
707 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
708 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
709 [/* For disassembly only; pattern left blank */]>;
711 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
712 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
713 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
714 [/* For disassembly only; pattern left blank */]>;
716 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
717 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
718 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
719 [/* For disassembly only; pattern left blank */]>;
721 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
722 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
723 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
724 [/* For disassembly only; pattern left blank */]>;
726 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
727 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
728 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
729 [/* For disassembly only; pattern left blank */]>;
731 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
732 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
733 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
734 [/* For disassembly only; pattern left blank */]>;
736 } // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
738 //===----------------------------------------------------------------------===//
739 // FP FMA Operations.
742 def VMLAD : ADbI_vmlX<0b11100, 0b00, 0, 0,
743 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
744 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
745 [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
747 RegConstraint<"$Ddin = $Dd">;
749 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
750 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
751 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
752 [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
754 RegConstraint<"$Sdin = $Sd">;
756 def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
757 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
758 def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
759 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
761 def VMLSD : ADbI_vmlX<0b11100, 0b00, 1, 0,
762 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
763 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
764 [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
766 RegConstraint<"$Ddin = $Dd">;
768 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
769 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
770 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
771 [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
773 RegConstraint<"$Sdin = $Sd">;
775 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
776 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
777 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
778 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
780 def VNMLAD : ADbI_vmlX<0b11100, 0b01, 1, 0,
781 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
782 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
783 [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
785 RegConstraint<"$Ddin = $Dd">;
787 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
788 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
789 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
790 [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
792 RegConstraint<"$Sdin = $Sd">;
794 def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
795 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
796 def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
797 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
799 def VNMLSD : ADbI_vmlX<0b11100, 0b01, 0, 0,
800 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
801 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
802 [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
804 RegConstraint<"$Ddin = $Dd">;
806 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
807 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
808 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
809 [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
810 RegConstraint<"$Sdin = $Sd">;
812 def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
813 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
814 def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
815 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
818 //===----------------------------------------------------------------------===//
819 // FP Conditional moves.
822 let neverHasSideEffects = 1 in {
823 def VMOVDcc : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
824 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
825 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
826 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
827 RegConstraint<"$Dn = $Dd">;
829 def VMOVScc : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
830 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
831 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
832 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
833 RegConstraint<"$Sn = $Sd">;
835 def VNEGDcc : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
836 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
837 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
838 [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
839 RegConstraint<"$Dn = $Dd">;
841 def VNEGScc : ASuI<0b11101, 0b11, 0b0001, 0b01, 0,
842 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
843 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
844 [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
845 RegConstraint<"$Sn = $Sd">;
846 } // neverHasSideEffects
848 //===----------------------------------------------------------------------===//
852 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
854 let Defs = [CPSR], Uses = [FPSCR] in
855 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT,
856 "vmrs", "\tapsr_nzcv, fpscr",
858 let Inst{27-20} = 0b11101111;
859 let Inst{19-16} = 0b0001;
860 let Inst{15-12} = 0b1111;
861 let Inst{11-8} = 0b1010;
863 let Inst{6-5} = 0b00;
865 let Inst{3-0} = 0b0000;
869 let hasSideEffects = 1, Uses = [FPSCR] in
870 def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
871 "vmrs", "\t$Rt, fpscr",
872 [(set GPR:$Rt, (int_arm_get_fpscr))]> {
873 // Instruction operand.
876 // Encode instruction operand.
877 let Inst{15-12} = Rt;
879 let Inst{27-20} = 0b11101111;
880 let Inst{19-16} = 0b0001;
881 let Inst{11-8} = 0b1010;
883 let Inst{6-5} = 0b00;
885 let Inst{3-0} = 0b0000;
888 let Defs = [FPSCR] in
889 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
890 "vmsr", "\tfpscr, $src",
891 [(int_arm_set_fpscr GPR:$src)]> {
892 // Instruction operand.
895 // Encode instruction operand.
896 let Inst{15-12} = src;
898 let Inst{27-20} = 0b11101110;
899 let Inst{19-16} = 0b0001;
900 let Inst{11-8} = 0b1010;
905 // Materialize FP immediates. VFP3 only.
906 let isReMaterializable = 1 in {
907 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
908 VFPMiscFrm, IIC_fpUNA64,
909 "vmov", ".f64\t$Dd, $imm",
910 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
911 // Instruction operands.
915 // Encode instruction operands.
916 let Inst{15-12} = Dd{3-0};
917 let Inst{22} = Dd{4};
918 let Inst{19} = imm{31};
919 let Inst{18-16} = imm{22-20};
920 let Inst{3-0} = imm{19-16};
922 // Encode remaining instruction bits.
923 let Inst{27-23} = 0b11101;
924 let Inst{21-20} = 0b11;
925 let Inst{11-9} = 0b101;
926 let Inst{8} = 1; // Double precision.
927 let Inst{7-4} = 0b0000;
930 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
931 VFPMiscFrm, IIC_fpUNA32,
932 "vmov", ".f32\t$Sd, $imm",
933 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
934 // Instruction operands.
938 // Encode instruction operands.
939 let Inst{15-12} = Sd{4-1};
940 let Inst{22} = Sd{0};
941 let Inst{19} = imm{31}; // The immediate is handled as a double.
942 let Inst{18-16} = imm{22-20};
943 let Inst{3-0} = imm{19-16};
945 // Encode remaining instruction bits.
946 let Inst{27-23} = 0b11101;
947 let Inst{21-20} = 0b11;
948 let Inst{11-9} = 0b101;
949 let Inst{8} = 0; // Single precision.
950 let Inst{7-4} = 0b0000;