1 //===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the JIT interfaces for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "jit"
15 #include "ARMJITInfo.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMRelocations.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/JITCodeEmitter.h"
22 #include "llvm/Config/alloca.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Streams.h"
26 #include "llvm/System/Memory.h"
30 void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
31 llvm_report_error("ARMJITInfo::replaceMachineCodeForFunction");
34 /// JITCompilerFunction - This contains the address of the JIT function used to
35 /// compile a function lazily.
36 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
38 // Get the ASMPREFIX for the current host. This is often '_'.
39 #ifndef __USER_LABEL_PREFIX__
40 #define __USER_LABEL_PREFIX__
42 #define GETASMPREFIX2(X) #X
43 #define GETASMPREFIX(X) GETASMPREFIX2(X)
44 #define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
46 // CompilationCallback stub - We can't use a C function with inline assembly in
47 // it, because we the prolog/epilog inserted by GCC won't work for us (we need
48 // to preserve more context and manipulate the stack directly). Instead,
49 // write our own wrapper, which does things our way, so we have complete
50 // control over register saving and restoring.
53 void ARMCompilationCallback(void);
57 ".globl " ASMPREFIX "ARMCompilationCallback\n"
58 ASMPREFIX "ARMCompilationCallback:\n"
59 // Save caller saved registers since they may contain stuff
60 // for the real target function right now. We have to act as if this
61 // whole compilation callback doesn't exist as far as the caller is
62 // concerned, so we can't just preserve the callee saved regs.
63 "stmdb sp!, {r0, r1, r2, r3, lr}\n"
65 "fstmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
67 // The LR contains the address of the stub function on entry.
68 // pass it as the argument to the C part of the callback
71 // Call the C portion of the callback
72 "bl " ASMPREFIX "ARMCompilationCallbackC\n"
74 // Restoring the LR to the return address of the function that invoked
75 // the stub and de-allocating the stack space for it requires us to
76 // swap the two saved LR values on the stack, as they're backwards
77 // for what we need since the pop instruction has a pre-determined
78 // order for the registers.
80 // 0 | LR | Original return address
82 // 1 | LR | Stub address (start of stub)
83 // 2-5 | R3..R0 | Saved registers (we need to preserve all regs)
84 // 6-20 | D0..D7 | Saved VFP registers
88 // Restore VFP caller-saved registers.
89 "fldmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
92 // We need to exchange the values in slots 0 and 1 so we can
93 // return to the address in slot 1 with the address in slot 0
94 // restored to the LR.
99 // Return to the (newly modified) stub to invoke the real function.
100 // The above twiddling of the saved return addresses allows us to
101 // deallocate everything, including the LR the stub saved, all in one
103 "ldmia sp!, {r0, r1, r2, r3, lr, pc}\n"
105 #else // Not an ARM host
106 void ARMCompilationCallback() {
107 llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
112 /// ARMCompilationCallbackC - This is the target-specific function invoked
113 /// by the function stub when we did not know the real target of a call.
114 /// This function must locate the start of the stub or call site and pass
115 /// it into the JIT compiler function.
116 extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) {
117 // Get the address of the compiled code for this function.
118 intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)StubAddr);
120 // Rewrite the call target... so that we don't end up here every time we
121 // execute the call. We're replacing the first two instructions of the
125 if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
126 llvm_unreachable("ERROR: Unable to mark stub writable");
128 *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
129 *(intptr_t *)(StubAddr+4) = NewVal;
130 if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
131 llvm_unreachable("ERROR: Unable to mark stub executable");
135 TargetJITInfo::LazyResolverFn
136 ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) {
137 JITCompilerFunction = F;
138 return ARMCompilationCallback;
141 void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
142 JITCodeEmitter &JCE) {
143 JCE.startGVStub(GV, 4, 4);
144 JCE.emitWordLE((intptr_t)Ptr);
145 void *PtrAddr = JCE.finishGVStub(GV);
146 addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
150 void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
151 JITCodeEmitter &JCE) {
152 // If this is just a call to an external function, emit a branch instead of a
153 // call. The code is the same except for one bit of the last instruction.
154 if (Fn != (void*)(intptr_t)ARMCompilationCallback) {
155 // Branch to the corresponding function addr.
157 // The stub is 8-byte size and 4-aligned.
158 intptr_t LazyPtr = getIndirectSymAddr(Fn);
160 // In PIC mode, the function stub is loading a lazy-ptr.
161 LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, JCE);
163 DOUT << "JIT: Indirect symbol emitted at [" << LazyPtr << "] for GV '"
164 << F->getName() << "'\n";
166 DOUT << "JIT: Stub emitted at [" << LazyPtr
167 << "] for external function at '" << Fn << "'\n";
169 JCE.startGVStub(F, 16, 4);
170 intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
171 JCE.emitWordLE(0xe59fc004); // ldr pc, [pc, #+4]
172 JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip
173 JCE.emitWordLE(0xe59cf000); // ldr pc, [ip]
174 JCE.emitWordLE(LazyPtr - (Addr+4+8)); // func - (L_func$scv+8)
175 sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
177 // The stub is 8-byte size and 4-aligned.
178 JCE.startGVStub(F, 8, 4);
179 intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
180 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
181 JCE.emitWordLE((intptr_t)Fn); // addr of function
182 sys::Memory::InvalidateInstructionCache((void*)Addr, 8);
185 // The compilation callback will overwrite the first two words of this
186 // stub with indirect branch instructions targeting the compiled code.
187 // This stub sets the return address to restart the stub, so that
188 // the new branch will be invoked when we come back.
190 // Branch and link to the compilation callback.
191 // The stub is 16-byte size and 4-byte aligned.
192 JCE.startGVStub(F, 16, 4);
193 intptr_t Addr = (intptr_t)JCE.getCurrentPCValue();
194 // Save LR so the callback can determine which stub called it.
195 // The compilation callback is responsible for popping this prior
197 JCE.emitWordLE(0xe92d4000); // push {lr}
198 // Set the return address to go back to the start of this stub.
199 JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
200 // Invoke the compilation callback.
201 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
202 // The address of the compilation callback.
203 JCE.emitWordLE((intptr_t)ARMCompilationCallback);
204 sys::Memory::InvalidateInstructionCache((void*)Addr, 16);
207 return JCE.finishGVStub(F);
210 intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
211 ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
214 return (intptr_t)(MR->getResultPointer());
215 case ARM::reloc_arm_pic_jt:
216 // Destination address - jump table base.
217 return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal();
218 case ARM::reloc_arm_jt_base:
219 // Jump table base address.
220 return getJumpTableBaseAddr(MR->getJumpTableIndex());
221 case ARM::reloc_arm_cp_entry:
222 case ARM::reloc_arm_vfp_cp_entry:
223 // Constant pool entry address.
224 return getConstantPoolEntryAddr(MR->getConstantPoolIndex());
225 case ARM::reloc_arm_machine_cp_entry: {
226 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal();
227 assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) &&
228 "Can't handle this machine constant pool entry yet!");
229 intptr_t Addr = (intptr_t)(MR->getResultPointer());
230 Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment();
236 /// relocate - Before the JIT can run a block of code that has been emitted,
237 /// it must rewrite the code to contain the actual addresses of any
238 /// referenced global symbols.
239 void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
240 unsigned NumRelocs, unsigned char* GOTBase) {
241 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
242 void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
243 intptr_t ResultPtr = resolveRelocDestAddr(MR);
244 switch ((ARM::RelocationType)MR->getRelocationType()) {
245 case ARM::reloc_arm_cp_entry:
246 case ARM::reloc_arm_vfp_cp_entry:
247 case ARM::reloc_arm_relative: {
248 // It is necessary to calculate the correct PC relative value. We
249 // subtract the base addr from the target addr to form a byte offset.
250 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
251 // If the result is positive, set bit U(23) to 1.
253 *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift;
255 // Otherwise, obtain the absolute value and set bit U(23) to 0.
256 *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift);
257 ResultPtr = - ResultPtr;
259 // Set the immed value calculated.
260 // VFP immediate offset is multiplied by 4.
261 if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
262 ResultPtr = ResultPtr >> 2;
263 *((intptr_t*)RelocPos) |= ResultPtr;
264 // Set register Rn to PC.
265 *((intptr_t*)RelocPos) |=
266 ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
269 case ARM::reloc_arm_pic_jt:
270 case ARM::reloc_arm_machine_cp_entry:
271 case ARM::reloc_arm_absolute: {
272 // These addresses have already been resolved.
273 *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr;
276 case ARM::reloc_arm_branch: {
277 // It is necessary to calculate the correct value of signed_immed_24
278 // field. We subtract the base addr from the target addr to form a
279 // byte offset, which must be inside the range -33554432 and +33554428.
280 // Then, we set the signed_immed_24 field of the instruction to bits
281 // [25:2] of the byte offset. More details ARM-ARM p. A4-11.
282 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
283 ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;
284 assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);
285 *((intptr_t*)RelocPos) |= ResultPtr;
288 case ARM::reloc_arm_jt_base: {
289 // JT base - (instruction addr + 8)
290 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
291 *((intptr_t*)RelocPos) |= ResultPtr;