1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that performs load / store related peephole
11 // optimizations. This pass should be run after register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-ldst-opt"
17 #include "ARMAddressingModes.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/Statistic.h"
41 STATISTIC(NumLDMGened , "Number of ldm instructions generated");
42 STATISTIC(NumSTMGened , "Number of stm instructions generated");
43 STATISTIC(NumFLDMGened, "Number of fldm instructions generated");
44 STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
45 STATISTIC(NumLdStMoved, "Number of load / store instructions moved");
46 STATISTIC(NumLDRDFormed,"Number of ldrd created before allocation");
47 STATISTIC(NumSTRDFormed,"Number of strd created before allocation");
48 STATISTIC(NumLDRD2LDM, "Number of ldrd instructions turned back into ldm");
49 STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
50 STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
51 STATISTIC(NumSTRD2STR, "Number of strd instructions turned back into str's");
53 /// ARMAllocLoadStoreOpt - Post- register allocation pass the combine
54 /// load / store instructions to form ldm / stm instructions.
57 struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
59 ARMLoadStoreOpt() : MachineFunctionPass(&ID) {}
61 const TargetInstrInfo *TII;
62 const TargetRegisterInfo *TRI;
67 virtual bool runOnMachineFunction(MachineFunction &Fn);
69 virtual const char *getPassName() const {
70 return "ARM load / store optimization pass";
74 struct MemOpQueueEntry {
77 MachineBasicBlock::iterator MBBI;
79 MemOpQueueEntry(int o, int p, MachineBasicBlock::iterator i)
80 : Offset(o), Position(p), MBBI(i), Merged(false) {};
82 typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
83 typedef MemOpQueue::iterator MemOpQueueIter;
85 bool MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
86 int Offset, unsigned Base, bool BaseKill, int Opcode,
87 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
88 DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
89 void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
90 int Opcode, unsigned Size,
91 ARMCC::CondCodes Pred, unsigned PredReg,
92 unsigned Scratch, MemOpQueue &MemOps,
93 SmallVector<MachineBasicBlock::iterator, 4> &Merges);
95 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
96 bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator &MBBI);
98 bool MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MBBI,
100 const TargetInstrInfo *TII,
102 MachineBasicBlock::iterator &I);
103 bool MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator MBBI,
106 MachineBasicBlock::iterator &I);
107 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
108 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
110 char ARMLoadStoreOpt::ID = 0;
113 static int getLoadStoreMultipleOpcode(int Opcode) {
141 default: llvm_unreachable("Unhandled opcode!");
146 static bool isi32Load(unsigned Opc) {
147 return Opc == ARM::LDR || Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
150 static bool isi32Store(unsigned Opc) {
151 return Opc == ARM::STR || Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8;
154 /// MergeOps - Create and insert a LDM or STM with Base as base register and
155 /// registers in Regs as the register operands that would be loaded / stored.
156 /// It returns true if the transformation is done.
158 ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator MBBI,
160 int Offset, unsigned Base, bool BaseKill,
161 int Opcode, ARMCC::CondCodes Pred,
162 unsigned PredReg, unsigned Scratch, DebugLoc dl,
163 SmallVector<std::pair<unsigned, bool>, 8> &Regs) {
164 // Only a single register to load / store. Don't bother.
165 unsigned NumRegs = Regs.size();
169 ARM_AM::AMSubMode Mode = ARM_AM::ia;
170 bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode);
171 if (isAM4 && Offset == 4)
173 else if (isAM4 && Offset == -4 * (int)NumRegs + 4)
175 else if (isAM4 && Offset == -4 * (int)NumRegs)
177 else if (Offset != 0) {
178 // If starting offset isn't zero, insert a MI to materialize a new base.
179 // But only do so if it is cost effective, i.e. merging more than two
185 if (isi32Load(Opcode))
186 // If it is a load, then just use one of the destination register to
187 // use as the new base.
188 NewBase = Regs[NumRegs-1].first;
190 // Use the scratch register to use as a new base.
195 int BaseOpc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
197 BaseOpc = isThumb2 ? ARM::t2SUBri : ARM::SUBri;
200 int ImmedOffset = isThumb2
201 ? ARM_AM::getT2SOImmVal(Offset) : ARM_AM::getSOImmVal(Offset);
202 if (ImmedOffset == -1)
203 // FIXME: Try t2ADDri12 or t2SUBri12?
204 return false; // Probably not worth it then.
206 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
207 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
208 .addImm(Pred).addReg(PredReg).addReg(0);
210 BaseKill = true; // New base is always killed right its use.
213 bool isDPR = Opcode == ARM::FLDD || Opcode == ARM::FSTD;
214 bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
215 Opcode = getLoadStoreMultipleOpcode(Opcode);
216 MachineInstrBuilder MIB = (isAM4)
217 ? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
218 .addReg(Base, getKillRegState(BaseKill))
219 .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
220 : BuildMI(MBB, MBBI, dl, TII->get(Opcode))
221 .addReg(Base, getKillRegState(BaseKill))
222 .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
223 .addImm(Pred).addReg(PredReg);
224 for (unsigned i = 0; i != NumRegs; ++i)
225 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
226 | getKillRegState(Regs[i].second));
231 /// MergeLDR_STR - Merge a number of load / store instructions into one or more
232 /// load / store multiple instructions.
234 ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
235 unsigned Base, int Opcode, unsigned Size,
236 ARMCC::CondCodes Pred, unsigned PredReg,
237 unsigned Scratch, MemOpQueue &MemOps,
238 SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
239 bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode);
240 int Offset = MemOps[SIndex].Offset;
241 int SOffset = Offset;
242 unsigned Pos = MemOps[SIndex].Position;
243 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
244 DebugLoc dl = Loc->getDebugLoc();
245 unsigned PReg = Loc->getOperand(0).getReg();
246 unsigned PRegNum = ARMRegisterInfo::getRegisterNumbering(PReg);
247 bool isKill = Loc->getOperand(0).isKill();
249 SmallVector<std::pair<unsigned,bool>, 8> Regs;
250 Regs.push_back(std::make_pair(PReg, isKill));
251 for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
252 int NewOffset = MemOps[i].Offset;
253 unsigned Reg = MemOps[i].MBBI->getOperand(0).getReg();
254 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
255 isKill = MemOps[i].MBBI->getOperand(0).isKill();
256 // AM4 - register numbers in ascending order.
257 // AM5 - consecutive register numbers in ascending order.
258 if (NewOffset == Offset + (int)Size &&
259 ((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
261 Regs.push_back(std::make_pair(Reg, isKill));
264 // Can't merge this in. Try merge the earlier ones first.
265 if (MergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
266 Scratch, dl, Regs)) {
267 Merges.push_back(prior(Loc));
268 for (unsigned j = SIndex; j < i; ++j) {
269 MBB.erase(MemOps[j].MBBI);
270 MemOps[j].Merged = true;
273 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
278 if (MemOps[i].Position > Pos) {
279 Pos = MemOps[i].Position;
280 Loc = MemOps[i].MBBI;
284 bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
285 if (MergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
286 Scratch, dl, Regs)) {
287 Merges.push_back(prior(Loc));
288 for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
289 MBB.erase(MemOps[i].MBBI);
290 MemOps[i].Merged = true;
297 /// getInstrPredicate - If instruction is predicated, returns its predicate
298 /// condition, otherwise returns AL. It also returns the condition code
299 /// register by reference.
300 static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
301 int PIdx = MI->findFirstPredOperandIdx();
307 PredReg = MI->getOperand(PIdx+1).getReg();
308 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
311 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
312 unsigned Bytes, ARMCC::CondCodes Pred,
313 unsigned PredReg, bool isThumb2) {
314 unsigned MyPredReg = 0;
318 if (MI->getOpcode() != ARM::t2SUBri)
320 // Make sure the offset fits in 8 bits.
321 if (Bytes <= 0 || Bytes >= 0x100)
324 if (MI->getOpcode() != ARM::SUBri)
326 // Make sure the offset fits in 12 bits.
327 if (Bytes <= 0 || Bytes >= 0x1000)
331 return (MI->getOperand(0).getReg() == Base &&
332 MI->getOperand(1).getReg() == Base &&
333 MI->getOperand(2).getImm() == Bytes &&
334 getInstrPredicate(MI, MyPredReg) == Pred &&
335 MyPredReg == PredReg);
338 static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
339 unsigned Bytes, ARMCC::CondCodes Pred,
340 unsigned PredReg, bool isThumb2) {
341 unsigned MyPredReg = 0;
345 if (MI->getOpcode() != ARM::t2ADDri)
347 // Make sure the offset fits in 8 bits.
348 if (Bytes <= 0 || Bytes >= 0x100)
351 if (MI->getOpcode() != ARM::ADDri)
353 // Make sure the offset fits in 12 bits.
354 if (Bytes <= 0 || Bytes >= 0x1000)
358 return (MI->getOperand(0).getReg() == Base &&
359 MI->getOperand(1).getReg() == Base &&
360 MI->getOperand(2).getImm() == Bytes &&
361 getInstrPredicate(MI, MyPredReg) == Pred &&
362 MyPredReg == PredReg);
365 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
366 switch (MI->getOpcode()) {
382 return (MI->getNumOperands() - 4) * 4;
387 return ARM_AM::getAM5Offset(MI->getOperand(1).getImm()) * 4;
391 /// MergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
392 /// register into the LDM/STM/FLDM{D|S}/FSTM{D|S} op when possible:
394 /// stmia rn, <ra, rb, rc>
395 /// rn := rn + 4 * 3;
397 /// stmia rn!, <ra, rb, rc>
399 /// rn := rn - 4 * 3;
400 /// ldmia rn, <ra, rb, rc>
402 /// ldmdb rn!, <ra, rb, rc>
403 bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator MBBI,
406 MachineBasicBlock::iterator &I) {
407 MachineInstr *MI = MBBI;
408 unsigned Base = MI->getOperand(0).getReg();
409 unsigned Bytes = getLSMultipleTransferSize(MI);
410 unsigned PredReg = 0;
411 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
412 int Opcode = MI->getOpcode();
413 bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::t2LDM ||
414 Opcode == ARM::STM || Opcode == ARM::t2STM;
417 if (ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()))
420 // Can't use the updating AM4 sub-mode if the base register is also a dest
421 // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
422 for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) {
423 if (MI->getOperand(i).getReg() == Base)
427 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
428 if (MBBI != MBB.begin()) {
429 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
430 if (Mode == ARM_AM::ia &&
431 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg, isThumb2)) {
432 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
435 } else if (Mode == ARM_AM::ib &&
436 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg,
438 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
444 if (MBBI != MBB.end()) {
445 MachineBasicBlock::iterator NextMBBI = next(MBBI);
446 if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
447 isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg, isThumb2)) {
448 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
455 } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
456 isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg,
458 MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
468 // FLDM{D|S}, FSTM{D|S} addressing mode 5 ops.
469 if (ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()))
472 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
473 unsigned Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
474 if (MBBI != MBB.begin()) {
475 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
476 if (Mode == ARM_AM::ia &&
477 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg, isThumb2)) {
478 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
484 if (MBBI != MBB.end()) {
485 MachineBasicBlock::iterator NextMBBI = next(MBBI);
486 if (Mode == ARM_AM::ia &&
487 isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg, isThumb2)) {
488 MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
502 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
504 case ARM::LDR: return ARM::LDR_PRE;
505 case ARM::STR: return ARM::STR_PRE;
506 case ARM::FLDS: return ARM::FLDMS;
507 case ARM::FLDD: return ARM::FLDMD;
508 case ARM::FSTS: return ARM::FSTMS;
509 case ARM::FSTD: return ARM::FSTMD;
512 return ARM::t2LDR_PRE;
515 return ARM::t2STR_PRE;
516 default: llvm_unreachable("Unhandled opcode!");
521 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
523 case ARM::LDR: return ARM::LDR_POST;
524 case ARM::STR: return ARM::STR_POST;
525 case ARM::FLDS: return ARM::FLDMS;
526 case ARM::FLDD: return ARM::FLDMD;
527 case ARM::FSTS: return ARM::FSTMS;
528 case ARM::FSTD: return ARM::FSTMD;
531 return ARM::t2LDR_POST;
534 return ARM::t2STR_POST;
535 default: llvm_unreachable("Unhandled opcode!");
540 /// MergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
541 /// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
542 bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator MBBI,
544 const TargetInstrInfo *TII,
546 MachineBasicBlock::iterator &I) {
547 MachineInstr *MI = MBBI;
548 unsigned Base = MI->getOperand(1).getReg();
549 bool BaseKill = MI->getOperand(1).isKill();
550 unsigned Bytes = getLSMultipleTransferSize(MI);
551 int Opcode = MI->getOpcode();
552 DebugLoc dl = MI->getDebugLoc();
553 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
554 if (isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
556 else if (!isAM2 && !isThumb2 &&
557 ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
559 else if (isThumb2 && MI->getOperand(2).getImm() != 0)
562 bool isLd = isi32Load(Opcode) || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
563 // Can't do the merge if the destination register is the same as the would-be
564 // writeback register.
565 if (isLd && MI->getOperand(0).getReg() == Base)
568 unsigned PredReg = 0;
569 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
570 bool DoMerge = false;
571 ARM_AM::AddrOpc AddSub = ARM_AM::add;
573 if (MBBI != MBB.begin()) {
574 MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
575 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg, isThumb2)) {
577 AddSub = ARM_AM::sub;
578 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
579 } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes,
580 Pred, PredReg, isThumb2)) {
582 NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
588 if (!DoMerge && MBBI != MBB.end()) {
589 MachineBasicBlock::iterator NextMBBI = next(MBBI);
590 if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg,
593 AddSub = ARM_AM::sub;
594 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
595 } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg,
598 NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
612 bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
613 unsigned Offset = isAM2
614 ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
617 : ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
618 true, isDPR ? 2 : 1));
620 if (isAM2 || isThumb2)
621 // LDR_PRE, LDR_POST, t2LDR_PRE, t2LDR_POST
622 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
623 .addReg(Base, RegState::Define)
624 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
627 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
628 .addReg(Base, getKillRegState(BaseKill))
629 .addImm(Offset).addImm(Pred).addReg(PredReg)
630 .addReg(MI->getOperand(0).getReg(), RegState::Define);
632 MachineOperand &MO = MI->getOperand(0);
633 if (isAM2 || isThumb2)
634 // STR_PRE, STR_POST, t2STR_PRE, t2STR_POST
635 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
636 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
637 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
640 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
641 .addImm(Pred).addReg(PredReg)
642 .addReg(MO.getReg(), getKillRegState(MO.isKill()));
649 /// isMemoryOp - Returns true if instruction is a memory operations (that this
650 /// pass is capable of operating on).
651 static bool isMemoryOp(const MachineInstr *MI) {
652 int Opcode = MI->getOpcode();
657 return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
660 return MI->getOperand(1).isReg();
663 return MI->getOperand(1).isReg();
673 /// AdvanceRS - Advance register scavenger to just before the earliest memory
674 /// op that is being merged.
675 void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
676 MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
677 unsigned Position = MemOps[0].Position;
678 for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
679 if (MemOps[i].Position < Position) {
680 Position = MemOps[i].Position;
681 Loc = MemOps[i].MBBI;
685 if (Loc != MBB.begin())
686 RS->forward(prior(Loc));
689 static int getMemoryOpOffset(const MachineInstr *MI) {
690 int Opcode = MI->getOpcode();
691 bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
692 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
693 unsigned NumOperands = MI->getDesc().getNumOperands();
694 unsigned OffField = MI->getOperand(NumOperands-3).getImm();
696 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
697 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
698 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8)
702 ? ARM_AM::getAM2Offset(OffField)
703 : (isAM3 ? ARM_AM::getAM3Offset(OffField)
704 : ARM_AM::getAM5Offset(OffField) * 4);
706 if (ARM_AM::getAM2Op(OffField) == ARM_AM::sub)
709 if (ARM_AM::getAM3Op(OffField) == ARM_AM::sub)
712 if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
718 static void InsertLDR_STR(MachineBasicBlock &MBB,
719 MachineBasicBlock::iterator &MBBI,
720 int OffImm, bool isDef,
721 DebugLoc dl, unsigned NewOpc,
722 unsigned Reg, bool RegDeadKill,
723 unsigned BaseReg, bool BaseKill,
724 unsigned OffReg, bool OffKill,
725 ARMCC::CondCodes Pred, unsigned PredReg,
726 const TargetInstrInfo *TII) {
729 Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
731 Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift);
733 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
734 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
735 .addReg(BaseReg, getKillRegState(BaseKill))
736 .addReg(OffReg, getKillRegState(OffKill))
738 .addImm(Pred).addReg(PredReg);
740 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
741 .addReg(Reg, getKillRegState(RegDeadKill))
742 .addReg(BaseReg, getKillRegState(BaseKill))
743 .addReg(OffReg, getKillRegState(OffKill))
745 .addImm(Pred).addReg(PredReg);
748 bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator &MBBI) {
750 MachineInstr *MI = &*MBBI;
751 unsigned Opcode = MI->getOpcode();
752 if (Opcode == ARM::LDRD || Opcode == ARM::STRD) {
753 unsigned EvenReg = MI->getOperand(0).getReg();
754 unsigned OddReg = MI->getOperand(1).getReg();
755 unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
756 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
757 if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)
760 bool isLd = Opcode == ARM::LDRD;
761 bool EvenDeadKill = isLd ?
762 MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
763 bool OddDeadKill = isLd ?
764 MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
765 const MachineOperand &BaseOp = MI->getOperand(2);
766 unsigned BaseReg = BaseOp.getReg();
767 bool BaseKill = BaseOp.isKill();
768 const MachineOperand &OffOp = MI->getOperand(3);
769 unsigned OffReg = OffOp.getReg();
770 bool OffKill = OffOp.isKill();
771 int OffImm = getMemoryOpOffset(MI);
772 unsigned PredReg = 0;
773 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
775 if (OddRegNum > EvenRegNum && OffReg == 0 && OffImm == 0) {
776 // Ascending register numbers and no offset. It's safe to change it to a
778 unsigned NewOpc = (Opcode == ARM::LDRD) ? ARM::LDM : ARM::STM;
780 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
781 .addReg(BaseReg, getKillRegState(BaseKill))
782 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
783 .addImm(Pred).addReg(PredReg)
784 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
785 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
788 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
789 .addReg(BaseReg, getKillRegState(BaseKill))
790 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
791 .addImm(Pred).addReg(PredReg)
792 .addReg(EvenReg, getKillRegState(EvenDeadKill))
793 .addReg(OddReg, getKillRegState(OddDeadKill));
797 // Split into two instructions.
798 unsigned NewOpc = (Opcode == ARM::LDRD) ? ARM::LDR : ARM::STR;
799 DebugLoc dl = MBBI->getDebugLoc();
800 // If this is a load and base register is killed, it may have been
801 // re-defed by the load, make sure the first load does not clobber it.
803 (BaseKill || OffKill) &&
804 (TRI->regsOverlap(EvenReg, BaseReg) ||
805 (OffReg && TRI->regsOverlap(EvenReg, OffReg)))) {
806 assert(!TRI->regsOverlap(OddReg, BaseReg) &&
807 (!OffReg || !TRI->regsOverlap(OddReg, OffReg)));
808 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc, OddReg, OddDeadKill,
809 BaseReg, false, OffReg, false, Pred, PredReg, TII);
810 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc, EvenReg, EvenDeadKill,
811 BaseReg, BaseKill, OffReg, OffKill, Pred, PredReg, TII);
813 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
814 EvenReg, EvenDeadKill, BaseReg, false, OffReg, false,
816 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
817 OddReg, OddDeadKill, BaseReg, BaseKill, OffReg, OffKill,
832 /// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
833 /// ops of the same base and incrementing offset into LDM / STM ops.
834 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
835 unsigned NumMerges = 0;
836 unsigned NumMemOps = 0;
838 unsigned CurrBase = 0;
840 unsigned CurrSize = 0;
841 ARMCC::CondCodes CurrPred = ARMCC::AL;
842 unsigned CurrPredReg = 0;
843 unsigned Position = 0;
844 SmallVector<MachineBasicBlock::iterator,4> Merges;
846 RS->enterBasicBlock(&MBB);
847 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
849 if (FixInvalidRegPairOp(MBB, MBBI))
852 bool Advance = false;
853 bool TryMerge = false;
854 bool Clobber = false;
856 bool isMemOp = isMemoryOp(MBBI);
858 int Opcode = MBBI->getOpcode();
859 unsigned Size = getLSMultipleTransferSize(MBBI);
860 unsigned Base = MBBI->getOperand(1).getReg();
861 unsigned PredReg = 0;
862 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
863 int Offset = getMemoryOpOffset(MBBI);
866 // r5 := ldr [r5, #4]
867 // r6 := ldr [r5, #8]
869 // The second ldr has effectively broken the chain even though it
870 // looks like the later ldr(s) use the same base register. Try to
871 // merge the ldr's so far, including this one. But don't try to
872 // combine the following ldr(s).
873 Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
874 if (CurrBase == 0 && !Clobber) {
875 // Start of a new chain.
880 CurrPredReg = PredReg;
881 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
890 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
891 // No need to match PredReg.
892 // Continue adding to the queue.
893 if (Offset > MemOps.back().Offset) {
894 MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
898 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
900 if (Offset < I->Offset) {
901 MemOps.insert(I, MemOpQueueEntry(Offset, Position, MBBI));
905 } else if (Offset == I->Offset) {
906 // Collision! This can't be merged!
923 // Try to find a free register to use as a new base in case it's needed.
924 // First advance to the instruction just before the start of the chain.
925 AdvanceRS(MBB, MemOps);
926 // Find a scratch register. Make sure it's a call clobbered register or
927 // a spilled callee-saved register.
928 unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
930 Scratch = RS->FindUnusedReg(&ARM::GPRRegClass,
931 AFI->getSpilledCSRegisters());
932 // Process the load / store instructions.
933 RS->forward(prior(MBBI));
937 MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,
938 CurrPred, CurrPredReg, Scratch, MemOps, Merges);
940 // Try folding preceeding/trailing base inc/dec into the generated
942 for (unsigned i = 0, e = Merges.size(); i < e; ++i)
943 if (MergeBaseUpdateLSMultiple(MBB, Merges[i], Advance, MBBI))
945 NumMerges += Merges.size();
947 // Try folding preceeding/trailing base inc/dec into those load/store
948 // that were not merged to form LDM/STM ops.
949 for (unsigned i = 0; i != NumMemOps; ++i)
950 if (!MemOps[i].Merged)
951 if (MergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
954 // RS may be pointing to an instruction that's deleted.
955 RS->skipTo(prior(MBBI));
956 } else if (NumMemOps == 1) {
957 // Try folding preceeding/trailing base inc/dec into the single
959 if (MergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
961 RS->forward(prior(MBBI));
968 CurrPred = ARMCC::AL;
975 // If iterator hasn't been advanced and this is not a memory op, skip it.
976 // It can't start a new chain anyway.
977 if (!Advance && !isMemOp && MBBI != E) {
983 return NumMerges > 0;
987 struct OffsetCompare {
988 bool operator()(const MachineInstr *LHS, const MachineInstr *RHS) const {
989 int LOffset = getMemoryOpOffset(LHS);
990 int ROffset = getMemoryOpOffset(RHS);
991 assert(LHS == RHS || LOffset != ROffset);
992 return LOffset > ROffset;
997 /// MergeReturnIntoLDM - If this is a exit BB, try merging the return op
998 /// (bx lr) into the preceeding stack restore so it directly restore the value
1000 /// ldmfd sp!, {r7, lr}
1003 /// ldmfd sp!, {r7, pc}
1004 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
1005 if (MBB.empty()) return false;
1007 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1008 if (MBBI != MBB.begin() &&
1009 (MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET)) {
1010 MachineInstr *PrevMI = prior(MBBI);
1011 if (PrevMI->getOpcode() == ARM::LDM || PrevMI->getOpcode() == ARM::t2LDM) {
1012 MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
1013 if (MO.getReg() == ARM::LR) {
1014 unsigned NewOpc = isThumb2 ? ARM::t2LDM_RET : ARM::LDM_RET;
1015 PrevMI->setDesc(TII->get(NewOpc));
1025 bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
1026 const TargetMachine &TM = Fn.getTarget();
1027 AFI = Fn.getInfo<ARMFunctionInfo>();
1028 TII = TM.getInstrInfo();
1029 TRI = TM.getRegisterInfo();
1030 RS = new RegScavenger();
1031 isThumb2 = AFI->isThumb2Function();
1033 bool Modified = false;
1034 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
1036 MachineBasicBlock &MBB = *MFI;
1037 Modified |= LoadStoreMultipleOpti(MBB);
1038 Modified |= MergeReturnIntoLDM(MBB);
1046 /// ARMPreAllocLoadStoreOpt - Pre- register allocation pass that move
1047 /// load / stores from consecutive locations close to make it more
1048 /// likely they will be combined later.
1051 struct VISIBILITY_HIDDEN ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
1053 ARMPreAllocLoadStoreOpt() : MachineFunctionPass(&ID) {}
1055 const TargetData *TD;
1056 const TargetInstrInfo *TII;
1057 const TargetRegisterInfo *TRI;
1058 const ARMSubtarget *STI;
1059 MachineRegisterInfo *MRI;
1061 virtual bool runOnMachineFunction(MachineFunction &Fn);
1063 virtual const char *getPassName() const {
1064 return "ARM pre- register allocation load / store optimization pass";
1068 bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
1069 unsigned &NewOpc, unsigned &EvenReg,
1070 unsigned &OddReg, unsigned &BaseReg,
1071 unsigned &OffReg, unsigned &Offset,
1072 unsigned &PredReg, ARMCC::CondCodes &Pred);
1073 bool RescheduleOps(MachineBasicBlock *MBB,
1074 SmallVector<MachineInstr*, 4> &Ops,
1075 unsigned Base, bool isLd,
1076 DenseMap<MachineInstr*, unsigned> &MI2LocMap);
1077 bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
1079 char ARMPreAllocLoadStoreOpt::ID = 0;
1082 bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
1083 TD = Fn.getTarget().getTargetData();
1084 TII = Fn.getTarget().getInstrInfo();
1085 TRI = Fn.getTarget().getRegisterInfo();
1086 STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
1087 MRI = &Fn.getRegInfo();
1089 bool Modified = false;
1090 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
1092 Modified |= RescheduleLoadStoreInstrs(MFI);
1097 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
1098 MachineBasicBlock::iterator I,
1099 MachineBasicBlock::iterator E,
1100 SmallPtrSet<MachineInstr*, 4> &MemOps,
1101 SmallSet<unsigned, 4> &MemRegs,
1102 const TargetRegisterInfo *TRI) {
1103 // Are there stores / loads / calls between them?
1104 // FIXME: This is overly conservative. We should make use of alias information
1106 SmallSet<unsigned, 4> AddedRegPressure;
1108 if (MemOps.count(&*I))
1110 const TargetInstrDesc &TID = I->getDesc();
1111 if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects())
1113 if (isLd && TID.mayStore())
1118 // It's not safe to move the first 'str' down.
1121 // str r4, [r0, #+4]
1125 for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
1126 MachineOperand &MO = I->getOperand(j);
1129 unsigned Reg = MO.getReg();
1130 if (MO.isDef() && TRI->regsOverlap(Reg, Base))
1132 if (Reg != Base && !MemRegs.count(Reg))
1133 AddedRegPressure.insert(Reg);
1137 // Estimate register pressure increase due to the transformation.
1138 if (MemRegs.size() <= 4)
1139 // Ok if we are moving small number of instructions.
1141 return AddedRegPressure.size() <= MemRegs.size() * 2;
1145 ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
1147 unsigned &NewOpc, unsigned &EvenReg,
1148 unsigned &OddReg, unsigned &BaseReg,
1149 unsigned &OffReg, unsigned &Offset,
1151 ARMCC::CondCodes &Pred) {
1152 // FIXME: FLDS / FSTS -> FLDD / FSTD
1153 unsigned Opcode = Op0->getOpcode();
1154 if (Opcode == ARM::LDR)
1156 else if (Opcode == ARM::STR)
1161 // Must sure the base address satisfies i64 ld / st alignment requirement.
1162 if (!Op0->hasOneMemOperand() ||
1163 !Op0->memoperands_begin()->getValue() ||
1164 Op0->memoperands_begin()->isVolatile())
1167 unsigned Align = Op0->memoperands_begin()->getAlignment();
1168 unsigned ReqAlign = STI->hasV6Ops()
1169 ? TD->getPrefTypeAlignment(Type::Int64Ty) : 8; // Pre-v6 need 8-byte align
1170 if (Align < ReqAlign)
1173 // Then make sure the immediate offset fits.
1174 int OffImm = getMemoryOpOffset(Op0);
1175 ARM_AM::AddrOpc AddSub = ARM_AM::add;
1177 AddSub = ARM_AM::sub;
1180 if (OffImm >= 256) // 8 bits
1182 Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
1184 EvenReg = Op0->getOperand(0).getReg();
1185 OddReg = Op1->getOperand(0).getReg();
1186 if (EvenReg == OddReg)
1188 BaseReg = Op0->getOperand(1).getReg();
1189 OffReg = Op0->getOperand(2).getReg();
1190 Pred = getInstrPredicate(Op0, PredReg);
1191 dl = Op0->getDebugLoc();
1195 bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
1196 SmallVector<MachineInstr*, 4> &Ops,
1197 unsigned Base, bool isLd,
1198 DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
1199 bool RetVal = false;
1201 // Sort by offset (in reverse order).
1202 std::sort(Ops.begin(), Ops.end(), OffsetCompare());
1204 // The loads / stores of the same base are in order. Scan them from first to
1205 // last and check for the followins:
1206 // 1. Any def of base.
1208 while (Ops.size() > 1) {
1209 unsigned FirstLoc = ~0U;
1210 unsigned LastLoc = 0;
1211 MachineInstr *FirstOp = 0;
1212 MachineInstr *LastOp = 0;
1214 unsigned LastOpcode = 0;
1215 unsigned LastBytes = 0;
1216 unsigned NumMove = 0;
1217 for (int i = Ops.size() - 1; i >= 0; --i) {
1218 MachineInstr *Op = Ops[i];
1219 unsigned Loc = MI2LocMap[Op];
1220 if (Loc <= FirstLoc) {
1224 if (Loc >= LastLoc) {
1229 unsigned Opcode = Op->getOpcode();
1230 if (LastOpcode && Opcode != LastOpcode)
1233 int Offset = getMemoryOpOffset(Op);
1234 unsigned Bytes = getLSMultipleTransferSize(Op);
1236 if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
1239 LastOffset = Offset;
1241 LastOpcode = Opcode;
1242 if (++NumMove == 8) // FIXME: Tune
1249 SmallPtrSet<MachineInstr*, 4> MemOps;
1250 SmallSet<unsigned, 4> MemRegs;
1251 for (int i = NumMove-1; i >= 0; --i) {
1252 MemOps.insert(Ops[i]);
1253 MemRegs.insert(Ops[i]->getOperand(0).getReg());
1256 // Be conservative, if the instructions are too far apart, don't
1257 // move them. We want to limit the increase of register pressure.
1258 bool DoMove = (LastLoc - FirstLoc) <= NumMove*4; // FIXME: Tune this.
1260 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
1261 MemOps, MemRegs, TRI);
1263 for (unsigned i = 0; i != NumMove; ++i)
1266 // This is the new location for the loads / stores.
1267 MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
1268 while (InsertPos != MBB->end() && MemOps.count(InsertPos))
1271 // If we are moving a pair of loads / stores, see if it makes sense
1272 // to try to allocate a pair of registers that can form register pairs.
1273 MachineInstr *Op0 = Ops.back();
1274 MachineInstr *Op1 = Ops[Ops.size()-2];
1275 unsigned EvenReg = 0, OddReg = 0;
1276 unsigned BaseReg = 0, OffReg = 0, PredReg = 0;
1277 ARMCC::CondCodes Pred = ARMCC::AL;
1278 unsigned NewOpc = 0;
1279 unsigned Offset = 0;
1281 if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
1282 EvenReg, OddReg, BaseReg, OffReg,
1283 Offset, PredReg, Pred)) {
1287 // Form the pair instruction.
1289 BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc))
1290 .addReg(EvenReg, RegState::Define)
1291 .addReg(OddReg, RegState::Define)
1292 .addReg(BaseReg).addReg(0).addImm(Offset)
1293 .addImm(Pred).addReg(PredReg);
1296 BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc))
1299 .addReg(BaseReg).addReg(0).addImm(Offset)
1300 .addImm(Pred).addReg(PredReg);
1306 // Add register allocation hints to form register pairs.
1307 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
1308 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
1310 for (unsigned i = 0; i != NumMove; ++i) {
1311 MachineInstr *Op = Ops.back();
1313 MBB->splice(InsertPos, MBB, Op);
1317 NumLdStMoved += NumMove;
1327 ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
1328 bool RetVal = false;
1330 DenseMap<MachineInstr*, unsigned> MI2LocMap;
1331 DenseMap<unsigned, SmallVector<MachineInstr*, 4> > Base2LdsMap;
1332 DenseMap<unsigned, SmallVector<MachineInstr*, 4> > Base2StsMap;
1333 SmallVector<unsigned, 4> LdBases;
1334 SmallVector<unsigned, 4> StBases;
1337 MachineBasicBlock::iterator MBBI = MBB->begin();
1338 MachineBasicBlock::iterator E = MBB->end();
1340 for (; MBBI != E; ++MBBI) {
1341 MachineInstr *MI = MBBI;
1342 const TargetInstrDesc &TID = MI->getDesc();
1343 if (TID.isCall() || TID.isTerminator()) {
1344 // Stop at barriers.
1349 MI2LocMap[MI] = Loc++;
1350 if (!isMemoryOp(MI))
1352 unsigned PredReg = 0;
1353 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
1356 int Opcode = MI->getOpcode();
1357 bool isLd = Opcode == ARM::LDR ||
1358 Opcode == ARM::FLDS || Opcode == ARM::FLDD;
1359 unsigned Base = MI->getOperand(1).getReg();
1360 int Offset = getMemoryOpOffset(MI);
1362 bool StopHere = false;
1364 DenseMap<unsigned, SmallVector<MachineInstr*, 4> >::iterator BI =
1365 Base2LdsMap.find(Base);
1366 if (BI != Base2LdsMap.end()) {
1367 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
1368 if (Offset == getMemoryOpOffset(BI->second[i])) {
1374 BI->second.push_back(MI);
1376 SmallVector<MachineInstr*, 4> MIs;
1378 Base2LdsMap[Base] = MIs;
1379 LdBases.push_back(Base);
1382 DenseMap<unsigned, SmallVector<MachineInstr*, 4> >::iterator BI =
1383 Base2StsMap.find(Base);
1384 if (BI != Base2StsMap.end()) {
1385 for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
1386 if (Offset == getMemoryOpOffset(BI->second[i])) {
1392 BI->second.push_back(MI);
1394 SmallVector<MachineInstr*, 4> MIs;
1396 Base2StsMap[Base] = MIs;
1397 StBases.push_back(Base);
1402 // Found a duplicate (a base+offset combination that's seen earlier).
1409 // Re-schedule loads.
1410 for (unsigned i = 0, e = LdBases.size(); i != e; ++i) {
1411 unsigned Base = LdBases[i];
1412 SmallVector<MachineInstr*, 4> &Lds = Base2LdsMap[Base];
1414 RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
1417 // Re-schedule stores.
1418 for (unsigned i = 0, e = StBases.size(); i != e; ++i) {
1419 unsigned Base = StBases[i];
1420 SmallVector<MachineInstr*, 4> &Sts = Base2StsMap[Base];
1422 RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
1426 Base2LdsMap.clear();
1427 Base2StsMap.clear();
1437 /// createARMLoadStoreOptimizationPass - returns an instance of the load / store
1438 /// optimization pass.
1439 FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
1441 return new ARMPreAllocLoadStoreOpt();
1442 return new ARMLoadStoreOpt();