1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
52 { "fixup_arm_movt_hi16", 0, 16, 0 },
53 { "fixup_arm_movw_lo16", 0, 16, 0 },
56 if (Kind < FirstTargetFixupKind)
57 return MCCodeEmitter::getFixupKindInfo(Kind);
59 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
61 return Infos[Kind - FirstTargetFixupKind];
63 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 unsigned getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getMachineOpValue - Return binary encoding of operand. If the machine
71 /// operand requires relocation, record the relocation and return zero.
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
76 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
77 SmallVectorImpl<MCFixup> &Fixups) const;
79 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
80 unsigned &Reg, unsigned &Imm,
81 SmallVectorImpl<MCFixup> &Fixups) const;
83 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
85 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
90 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
91 SmallVectorImpl<MCFixup> &Fixups) const;
93 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
94 /// operand as needed by load/store instructions.
95 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
96 SmallVectorImpl<MCFixup> &Fixups) const;
98 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
99 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
100 SmallVectorImpl<MCFixup> &Fixups) const {
101 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
103 default: assert(0 && "Unknown addressing sub-mode!");
104 case ARM_AM::da: return 0;
105 case ARM_AM::ia: return 1;
106 case ARM_AM::db: return 2;
107 case ARM_AM::ib: return 3;
110 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
112 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
114 default: llvm_unreachable("Unknown shift opc!");
115 case ARM_AM::no_shift:
116 case ARM_AM::lsl: return 0;
117 case ARM_AM::lsr: return 1;
118 case ARM_AM::asr: return 2;
120 case ARM_AM::rrx: return 3;
125 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
126 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
127 SmallVectorImpl<MCFixup> &Fixups) const;
129 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
130 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
133 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
134 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
138 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const;
141 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
142 uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups) const;
145 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
146 uint32_t getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups) const;
149 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
150 uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
151 SmallVectorImpl<MCFixup> &Fixups) const;
153 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
154 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 /// getCCOutOpValue - Return encoding of the 's' bit.
158 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
159 SmallVectorImpl<MCFixup> &Fixups) const {
160 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
162 return MI.getOperand(Op).getReg() == ARM::CPSR;
165 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
166 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
167 SmallVectorImpl<MCFixup> &Fixups) const {
168 unsigned SoImm = MI.getOperand(Op).getImm();
169 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
170 assert(SoImmVal != -1 && "Not a valid so_imm value!");
172 // Encode rotate_imm.
173 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
174 << ARMII::SoRotImmShift;
177 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
181 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
182 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
183 SmallVectorImpl<MCFixup> &Fixups) const {
184 unsigned SoImm = MI.getOperand(Op).getImm();
185 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
186 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
190 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
191 SmallVectorImpl<MCFixup> &Fixups) const;
192 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
193 SmallVectorImpl<MCFixup> &Fixups) const;
194 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
195 SmallVectorImpl<MCFixup> &Fixups) const;
196 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
197 SmallVectorImpl<MCFixup> &Fixups) const;
199 /// getSORegOpValue - Return an encoded so_reg shifted register value.
200 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
201 SmallVectorImpl<MCFixup> &Fixups) const;
202 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
203 SmallVectorImpl<MCFixup> &Fixups) const;
205 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
206 SmallVectorImpl<MCFixup> &Fixups) const {
207 switch (MI.getOperand(Op).getImm()) {
208 default: assert (0 && "Not a valid rot_imm value!");
216 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
217 SmallVectorImpl<MCFixup> &Fixups) const {
218 return MI.getOperand(Op).getImm() - 1;
221 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
222 SmallVectorImpl<MCFixup> &Fixups) const {
223 return 64 - MI.getOperand(Op).getImm();
226 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
227 SmallVectorImpl<MCFixup> &Fixups) const;
229 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
230 SmallVectorImpl<MCFixup> &Fixups) const;
231 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
232 SmallVectorImpl<MCFixup> &Fixups) const;
233 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
234 SmallVectorImpl<MCFixup> &Fixups) const;
235 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
236 SmallVectorImpl<MCFixup> &Fixups) const;
238 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
239 unsigned EncodedValue) const;
240 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
241 unsigned EncodedValue) const;
242 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
243 unsigned EncodedValue) const;
245 void EmitByte(unsigned char C, raw_ostream &OS) const {
249 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
250 // Output the constant in little endian byte order.
251 for (unsigned i = 0; i != Size; ++i) {
252 EmitByte(Val & 255, OS);
257 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
258 SmallVectorImpl<MCFixup> &Fixups) const;
261 } // end anonymous namespace
263 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
265 return new ARMMCCodeEmitter(TM, Ctx);
268 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
269 /// instructions, and rewrite them to their Thumb2 form if we are currently in
271 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
272 unsigned EncodedValue) const {
273 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
274 if (Subtarget.isThumb2()) {
275 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
276 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
278 unsigned Bit24 = EncodedValue & 0x01000000;
279 unsigned Bit28 = Bit24 << 4;
280 EncodedValue &= 0xEFFFFFFF;
281 EncodedValue |= Bit28;
282 EncodedValue |= 0x0F000000;
288 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
289 /// instructions, and rewrite them to their Thumb2 form if we are currently in
291 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
292 unsigned EncodedValue) const {
293 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
294 if (Subtarget.isThumb2()) {
295 EncodedValue &= 0xF0FFFFFF;
296 EncodedValue |= 0x09000000;
302 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
303 /// instructions, and rewrite them to their Thumb2 form if we are currently in
305 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
306 unsigned EncodedValue) const {
307 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
308 if (Subtarget.isThumb2()) {
309 EncodedValue &= 0x00FFFFFF;
310 EncodedValue |= 0xEE000000;
318 /// getMachineOpValue - Return binary encoding of operand. If the machine
319 /// operand requires relocation, record the relocation and return zero.
320 unsigned ARMMCCodeEmitter::
321 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
322 SmallVectorImpl<MCFixup> &Fixups) const {
324 unsigned Reg = MO.getReg();
325 unsigned RegNo = getARMRegisterNumbering(Reg);
327 // Q registers are encoded as 2x their register number.
331 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
332 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
333 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
334 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
337 } else if (MO.isImm()) {
338 return static_cast<unsigned>(MO.getImm());
339 } else if (MO.isFPImm()) {
340 return static_cast<unsigned>(APFloat(MO.getFPImm())
341 .bitcastToAPInt().getHiBits(32).getLimitedValue());
344 llvm_unreachable("Unable to encode MCOperand!");
348 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
349 bool ARMMCCodeEmitter::
350 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
351 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
352 const MCOperand &MO = MI.getOperand(OpIdx);
353 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
355 Reg = getARMRegisterNumbering(MO.getReg());
357 int32_t SImm = MO1.getImm();
360 // Special value for #-0
361 if (SImm == INT32_MIN)
364 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
374 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
376 uint32_t ARMMCCodeEmitter::
377 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
378 SmallVectorImpl<MCFixup> &Fixups) const {
379 const MCOperand &MO = MI.getOperand(OpIdx);
381 // If the destination is an immediate, we have nothing to do.
382 if (MO.isImm()) return MO.getImm();
383 assert (MO.isExpr() && "Unexpected branch target type!");
384 const MCExpr *Expr = MO.getExpr();
385 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
386 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
388 // All of the information is in the fixup.
392 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
393 uint32_t ARMMCCodeEmitter::
394 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
395 SmallVectorImpl<MCFixup> &Fixups) const {
397 // {12} = (U)nsigned (add == '1', sub == '0')
401 // If The first operand isn't a register, we have a label reference.
402 const MCOperand &MO = MI.getOperand(OpIdx);
404 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
406 isAdd = false ; // 'U' bit is set as part of the fixup.
408 assert(MO.isExpr() && "Unexpected machine operand type!");
409 const MCExpr *Expr = MO.getExpr();
410 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
411 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
413 ++MCNumCPRelocations;
415 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
417 uint32_t Binary = Imm12 & 0xfff;
418 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
421 Binary |= (Reg << 13);
425 uint32_t ARMMCCodeEmitter::
426 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
427 SmallVectorImpl<MCFixup> &Fixups) const {
428 // {20-16} = imm{15-12}
429 // {11-0} = imm{11-0}
430 const MCOperand &MO = MI.getOperand(OpIdx);
432 return static_cast<unsigned>(MO.getImm());
433 } else if (const MCSymbolRefExpr *Expr =
434 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
436 switch (Expr->getKind()) {
437 default: assert(0 && "Unsupported ARMFixup");
438 case MCSymbolRefExpr::VK_ARM_HI16:
439 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
441 case MCSymbolRefExpr::VK_ARM_LO16:
442 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
445 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
448 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
452 uint32_t ARMMCCodeEmitter::
453 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
454 SmallVectorImpl<MCFixup> &Fixups) const {
455 const MCOperand &MO = MI.getOperand(OpIdx);
456 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
457 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
458 unsigned Rn = getARMRegisterNumbering(MO.getReg());
459 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
460 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
461 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
462 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
463 unsigned SBits = getShiftOp(ShOp);
472 uint32_t Binary = Rm;
474 Binary |= SBits << 5;
475 Binary |= ShImm << 7;
481 uint32_t ARMMCCodeEmitter::
482 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
483 SmallVectorImpl<MCFixup> &Fixups) const {
485 // {13} 1 == imm12, 0 == Rm
488 const MCOperand &MO = MI.getOperand(OpIdx);
489 unsigned Rn = getARMRegisterNumbering(MO.getReg());
490 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
495 uint32_t ARMMCCodeEmitter::
496 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
497 SmallVectorImpl<MCFixup> &Fixups) const {
498 // {13} 1 == imm12, 0 == Rm
501 const MCOperand &MO = MI.getOperand(OpIdx);
502 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
503 unsigned Imm = MO1.getImm();
504 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
505 bool isReg = MO.getReg() != 0;
506 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
507 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
509 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
510 Binary <<= 7; // Shift amount is bits [11:7]
511 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
512 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
514 return Binary | (isAdd << 12) | (isReg << 13);
517 uint32_t ARMMCCodeEmitter::
518 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
519 SmallVectorImpl<MCFixup> &Fixups) const {
520 // {9} 1 == imm8, 0 == Rm
524 const MCOperand &MO = MI.getOperand(OpIdx);
525 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
526 unsigned Imm = MO1.getImm();
527 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
528 bool isImm = MO.getReg() == 0;
529 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
530 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
532 Imm8 = getARMRegisterNumbering(MO.getReg());
533 return Imm8 | (isAdd << 8) | (isImm << 9);
536 uint32_t ARMMCCodeEmitter::
537 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
538 SmallVectorImpl<MCFixup> &Fixups) const {
539 // {13} 1 == imm8, 0 == Rm
544 const MCOperand &MO = MI.getOperand(OpIdx);
545 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
546 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
547 unsigned Rn = getARMRegisterNumbering(MO.getReg());
548 unsigned Imm = MO2.getImm();
549 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
550 bool isImm = MO1.getReg() == 0;
551 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
552 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
554 Imm8 = getARMRegisterNumbering(MO1.getReg());
555 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
558 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
559 static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
568 const MCOperand &MO = MI.getOperand(OpIdx);
569 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
570 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
571 unsigned Rn = getARMRegisterNumbering(MO.getReg());
572 unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
573 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
574 return (Rm << 3) | (Imm5 << 3) | Rn;
577 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
578 uint32_t ARMMCCodeEmitter::
579 getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
580 SmallVectorImpl<MCFixup> &) const {
581 return getAddrModeSOpValue(MI, OpIdx, 4);
584 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
585 uint32_t ARMMCCodeEmitter::
586 getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
587 SmallVectorImpl<MCFixup> &) const {
588 return getAddrModeSOpValue(MI, OpIdx, 2);
591 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
592 uint32_t ARMMCCodeEmitter::
593 getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
594 SmallVectorImpl<MCFixup> &) const {
595 return getAddrModeSOpValue(MI, OpIdx, 1);
598 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
599 uint32_t ARMMCCodeEmitter::
600 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
601 SmallVectorImpl<MCFixup> &Fixups) const {
603 // {8} = (U)nsigned (add == '1', sub == '0')
607 // If The first operand isn't a register, we have a label reference.
608 const MCOperand &MO = MI.getOperand(OpIdx);
610 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
612 isAdd = false; // 'U' bit is handled as part of the fixup.
614 assert(MO.isExpr() && "Unexpected machine operand type!");
615 const MCExpr *Expr = MO.getExpr();
616 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_10);
617 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
619 ++MCNumCPRelocations;
621 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
622 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
625 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
626 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
629 Binary |= (Reg << 9);
633 unsigned ARMMCCodeEmitter::
634 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
635 SmallVectorImpl<MCFixup> &Fixups) const {
636 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
637 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
638 // case the imm contains the amount to shift by.
641 // {4} = 1 if reg shift, 0 if imm shift
649 const MCOperand &MO = MI.getOperand(OpIdx);
650 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
651 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
652 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
655 unsigned Binary = getARMRegisterNumbering(MO.getReg());
657 // Encode the shift opcode.
659 unsigned Rs = MO1.getReg();
661 // Set shift operand (bit[7:4]).
666 // RRX - 0110 and bit[11:8] clear.
668 default: llvm_unreachable("Unknown shift opc!");
669 case ARM_AM::lsl: SBits = 0x1; break;
670 case ARM_AM::lsr: SBits = 0x3; break;
671 case ARM_AM::asr: SBits = 0x5; break;
672 case ARM_AM::ror: SBits = 0x7; break;
673 case ARM_AM::rrx: SBits = 0x6; break;
676 // Set shift operand (bit[6:4]).
682 default: llvm_unreachable("Unknown shift opc!");
683 case ARM_AM::lsl: SBits = 0x0; break;
684 case ARM_AM::lsr: SBits = 0x2; break;
685 case ARM_AM::asr: SBits = 0x4; break;
686 case ARM_AM::ror: SBits = 0x6; break;
690 Binary |= SBits << 4;
691 if (SOpc == ARM_AM::rrx)
694 // Encode the shift operation Rs or shift_imm (except rrx).
696 // Encode Rs bit[11:8].
697 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
698 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
701 // Encode shift_imm bit[11:7].
702 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
705 unsigned ARMMCCodeEmitter::
706 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
707 SmallVectorImpl<MCFixup> &Fixups) const {
708 const MCOperand &MO1 = MI.getOperand(OpNum);
709 const MCOperand &MO2 = MI.getOperand(OpNum+1);
710 const MCOperand &MO3 = MI.getOperand(OpNum+2);
712 // Encoded as [Rn, Rm, imm].
713 // FIXME: Needs fixup support.
714 unsigned Value = getARMRegisterNumbering(MO1.getReg());
716 Value |= getARMRegisterNumbering(MO2.getReg());
718 Value |= MO3.getImm();
723 unsigned ARMMCCodeEmitter::
724 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
725 SmallVectorImpl<MCFixup> &Fixups) const {
726 const MCOperand &MO1 = MI.getOperand(OpNum);
727 const MCOperand &MO2 = MI.getOperand(OpNum+1);
729 // FIXME: Needs fixup support.
730 unsigned Value = getARMRegisterNumbering(MO1.getReg());
732 // Even though the immediate is 8 bits long, we need 9 bits in order
733 // to represent the (inverse of the) sign bit.
735 int32_t tmp = (int32_t)MO2.getImm();
739 Value |= 256; // Set the ADD bit
744 unsigned ARMMCCodeEmitter::
745 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
746 SmallVectorImpl<MCFixup> &Fixups) const {
747 const MCOperand &MO1 = MI.getOperand(OpNum);
749 // FIXME: Needs fixup support.
751 int32_t tmp = (int32_t)MO1.getImm();
755 Value |= 256; // Set the ADD bit
760 unsigned ARMMCCodeEmitter::
761 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
762 SmallVectorImpl<MCFixup> &Fixups) const {
763 const MCOperand &MO1 = MI.getOperand(OpNum);
765 // FIXME: Needs fixup support.
767 int32_t tmp = (int32_t)MO1.getImm();
771 Value |= 4096; // Set the ADD bit
776 unsigned ARMMCCodeEmitter::
777 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
778 SmallVectorImpl<MCFixup> &Fixups) const {
779 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
780 // shifted. The second is the amount to shift by.
787 const MCOperand &MO = MI.getOperand(OpIdx);
788 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
789 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
792 unsigned Binary = getARMRegisterNumbering(MO.getReg());
794 // Encode the shift opcode.
796 // Set shift operand (bit[6:4]).
802 default: llvm_unreachable("Unknown shift opc!");
803 case ARM_AM::lsl: SBits = 0x0; break;
804 case ARM_AM::lsr: SBits = 0x2; break;
805 case ARM_AM::asr: SBits = 0x4; break;
806 case ARM_AM::ror: SBits = 0x6; break;
809 Binary |= SBits << 4;
810 if (SOpc == ARM_AM::rrx)
813 // Encode shift_imm bit[11:7].
814 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
817 unsigned ARMMCCodeEmitter::
818 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
819 SmallVectorImpl<MCFixup> &Fixups) const {
820 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
822 const MCOperand &MO = MI.getOperand(Op);
823 uint32_t v = ~MO.getImm();
824 uint32_t lsb = CountTrailingZeros_32(v);
825 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
826 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
827 return lsb | (msb << 5);
830 unsigned ARMMCCodeEmitter::
831 getRegisterListOpValue(const MCInst &MI, unsigned Op,
832 SmallVectorImpl<MCFixup> &Fixups) const {
835 // {7-0} = Number of registers
838 // {15-0} = Bitfield of GPRs.
839 unsigned Reg = MI.getOperand(Op).getReg();
840 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
841 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
845 if (SPRRegs || DPRRegs) {
847 unsigned RegNo = getARMRegisterNumbering(Reg);
848 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
849 Binary |= (RegNo & 0x1f) << 8;
853 Binary |= NumRegs * 2;
855 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
856 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
857 Binary |= 1 << RegNo;
864 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
865 /// with the alignment operand.
866 unsigned ARMMCCodeEmitter::
867 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
868 SmallVectorImpl<MCFixup> &Fixups) const {
869 const MCOperand &Reg = MI.getOperand(Op);
870 const MCOperand &Imm = MI.getOperand(Op + 1);
872 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
875 switch (Imm.getImm()) {
879 case 8: Align = 0x01; break;
880 case 16: Align = 0x02; break;
881 case 32: Align = 0x03; break;
884 return RegNo | (Align << 4);
887 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
888 /// alignment operand for use in VLD-dup instructions. This is the same as
889 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
890 /// different for VLD4-dup.
891 unsigned ARMMCCodeEmitter::
892 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
893 SmallVectorImpl<MCFixup> &Fixups) const {
894 const MCOperand &Reg = MI.getOperand(Op);
895 const MCOperand &Imm = MI.getOperand(Op + 1);
897 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
900 switch (Imm.getImm()) {
904 case 8: Align = 0x01; break;
905 case 16: Align = 0x03; break;
908 return RegNo | (Align << 4);
911 unsigned ARMMCCodeEmitter::
912 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
913 SmallVectorImpl<MCFixup> &Fixups) const {
914 const MCOperand &MO = MI.getOperand(Op);
915 if (MO.getReg() == 0) return 0x0D;
919 void ARMMCCodeEmitter::
920 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
921 SmallVectorImpl<MCFixup> &Fixups) const {
922 // Pseudo instructions don't get encoded.
923 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
924 uint64_t TSFlags = Desc.TSFlags;
925 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
928 // Basic size info comes from the TSFlags field.
929 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
930 default: llvm_unreachable("Unexpected instruction size!");
931 case ARMII::Size2Bytes: Size = 2; break;
932 case ARMII::Size4Bytes: Size = 4; break;
934 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
935 ++MCNumEmitted; // Keep track of the # of mi's emitted.
938 #include "ARMGenMCCodeEmitter.inc"