1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMCExpr.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Support/raw_ostream.h"
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
29 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
32 class ARMMCCodeEmitter : public MCCodeEmitter {
33 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
34 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
35 const TargetMachine &TM;
36 const TargetInstrInfo &TII;
37 const ARMSubtarget *Subtarget;
41 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
42 : TM(tm), TII(*TM.getInstrInfo()),
43 Subtarget(&TM.getSubtarget<ARMSubtarget>()), Ctx(ctx) {
46 ~ARMMCCodeEmitter() {}
48 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
50 // getBinaryCodeForInstr - TableGen'erated function for getting the
51 // binary encoding for an instruction.
52 unsigned getBinaryCodeForInstr(const MCInst &MI,
53 SmallVectorImpl<MCFixup> &Fixups) const;
55 /// getMachineOpValue - Return binary encoding of operand. If the machine
56 /// operand requires relocation, record the relocation and return zero.
57 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
58 SmallVectorImpl<MCFixup> &Fixups) const;
60 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
61 /// the specified operand. This is used for operands with :lower16: and
62 /// :upper16: prefixes.
63 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
64 SmallVectorImpl<MCFixup> &Fixups) const;
66 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
67 unsigned &Reg, unsigned &Imm,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
72 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
76 /// BLX branch target.
77 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
81 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
85 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
89 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
94 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
98 /// immediate Thumb2 direct branch target.
99 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 SmallVectorImpl<MCFixup> &Fixups) const;
102 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
104 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
108 /// ADR label target.
109 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
111 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
113 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
119 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
123 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups)const;
126 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
128 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
132 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
133 /// operand as needed by load/store instructions.
134 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
138 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const {
140 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
142 default: assert(0 && "Unknown addressing sub-mode!");
143 case ARM_AM::da: return 0;
144 case ARM_AM::ia: return 1;
145 case ARM_AM::db: return 2;
146 case ARM_AM::ib: return 3;
149 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
151 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
153 default: llvm_unreachable("Unknown shift opc!");
154 case ARM_AM::no_shift:
155 case ARM_AM::lsl: return 0;
156 case ARM_AM::lsr: return 1;
157 case ARM_AM::asr: return 2;
159 case ARM_AM::rrx: return 3;
164 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
165 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
169 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const;
172 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
173 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups) const;
176 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
177 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups) const;
180 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
182 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &Fixups) const;
185 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
186 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups) const;
189 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
190 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
191 SmallVectorImpl<MCFixup> &Fixups) const;
193 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
194 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups) const;
197 /// getCCOutOpValue - Return encoding of the 's' bit.
198 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
199 SmallVectorImpl<MCFixup> &Fixups) const {
200 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
202 return MI.getOperand(Op).getReg() == ARM::CPSR;
205 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
206 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
207 SmallVectorImpl<MCFixup> &Fixups) const {
208 unsigned SoImm = MI.getOperand(Op).getImm();
209 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
210 assert(SoImmVal != -1 && "Not a valid so_imm value!");
212 // Encode rotate_imm.
213 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
214 << ARMII::SoRotImmShift;
217 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
221 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
222 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
223 SmallVectorImpl<MCFixup> &Fixups) const {
224 unsigned SoImm = MI.getOperand(Op).getImm();
225 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
226 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
230 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
231 SmallVectorImpl<MCFixup> &Fixups) const;
232 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
233 SmallVectorImpl<MCFixup> &Fixups) const;
234 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
235 SmallVectorImpl<MCFixup> &Fixups) const;
236 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
237 SmallVectorImpl<MCFixup> &Fixups) const;
239 /// getSORegOpValue - Return an encoded so_reg shifted register value.
240 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
241 SmallVectorImpl<MCFixup> &Fixups) const;
242 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
243 SmallVectorImpl<MCFixup> &Fixups) const;
245 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
246 SmallVectorImpl<MCFixup> &Fixups) const {
247 switch (MI.getOperand(Op).getImm()) {
248 default: assert (0 && "Not a valid rot_imm value!");
256 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 return MI.getOperand(Op).getImm() - 1;
261 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
262 SmallVectorImpl<MCFixup> &Fixups) const {
263 return 64 - MI.getOperand(Op).getImm();
266 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
267 SmallVectorImpl<MCFixup> &Fixups) const;
269 unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
270 SmallVectorImpl<MCFixup> &Fixups) const;
272 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const;
283 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
284 SmallVectorImpl<MCFixup> &Fixups) const;
285 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
286 SmallVectorImpl<MCFixup> &Fixups) const;
287 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
288 SmallVectorImpl<MCFixup> &Fixups) const;
290 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
291 unsigned EncodedValue) const;
292 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
293 unsigned EncodedValue) const;
294 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
295 unsigned EncodedValue) const;
297 unsigned VFPThumb2PostEncoder(const MCInst &MI,
298 unsigned EncodedValue) const;
300 void EmitByte(unsigned char C, raw_ostream &OS) const {
304 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
305 // Output the constant in little endian byte order.
306 for (unsigned i = 0; i != Size; ++i) {
307 EmitByte(Val & 255, OS);
312 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
313 SmallVectorImpl<MCFixup> &Fixups) const;
316 } // end anonymous namespace
318 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
320 return new ARMMCCodeEmitter(TM, Ctx);
323 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
324 /// instructions, and rewrite them to their Thumb2 form if we are currently in
326 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
327 unsigned EncodedValue) const {
328 if (Subtarget->isThumb2()) {
329 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
330 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
332 unsigned Bit24 = EncodedValue & 0x01000000;
333 unsigned Bit28 = Bit24 << 4;
334 EncodedValue &= 0xEFFFFFFF;
335 EncodedValue |= Bit28;
336 EncodedValue |= 0x0F000000;
342 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
343 /// instructions, and rewrite them to their Thumb2 form if we are currently in
345 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
346 unsigned EncodedValue) const {
347 if (Subtarget->isThumb2()) {
348 EncodedValue &= 0xF0FFFFFF;
349 EncodedValue |= 0x09000000;
355 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
356 /// instructions, and rewrite them to their Thumb2 form if we are currently in
358 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
359 unsigned EncodedValue) const {
360 if (Subtarget->isThumb2()) {
361 EncodedValue &= 0x00FFFFFF;
362 EncodedValue |= 0xEE000000;
368 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
369 /// them to their Thumb2 form if we are currently in Thumb2 mode.
370 unsigned ARMMCCodeEmitter::
371 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
372 if (Subtarget->isThumb2()) {
373 EncodedValue &= 0x0FFFFFFF;
374 EncodedValue |= 0xE0000000;
379 /// getMachineOpValue - Return binary encoding of operand. If the machine
380 /// operand requires relocation, record the relocation and return zero.
381 unsigned ARMMCCodeEmitter::
382 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
383 SmallVectorImpl<MCFixup> &Fixups) const {
385 unsigned Reg = MO.getReg();
386 unsigned RegNo = getARMRegisterNumbering(Reg);
388 // Q registers are encoded as 2x their register number.
392 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
393 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
394 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
395 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
398 } else if (MO.isImm()) {
399 return static_cast<unsigned>(MO.getImm());
400 } else if (MO.isFPImm()) {
401 return static_cast<unsigned>(APFloat(MO.getFPImm())
402 .bitcastToAPInt().getHiBits(32).getLimitedValue());
405 llvm_unreachable("Unable to encode MCOperand!");
409 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
410 bool ARMMCCodeEmitter::
411 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
412 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
413 const MCOperand &MO = MI.getOperand(OpIdx);
414 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
416 Reg = getARMRegisterNumbering(MO.getReg());
418 int32_t SImm = MO1.getImm();
421 // Special value for #-0
422 if (SImm == INT32_MIN)
425 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
435 /// getBranchTargetOpValue - Helper function to get the branch target operand,
436 /// which is either an immediate or requires a fixup.
437 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
439 SmallVectorImpl<MCFixup> &Fixups) {
440 const MCOperand &MO = MI.getOperand(OpIdx);
442 // If the destination is an immediate, we have nothing to do.
443 if (MO.isImm()) return MO.getImm();
444 assert(MO.isExpr() && "Unexpected branch target type!");
445 const MCExpr *Expr = MO.getExpr();
446 MCFixupKind Kind = MCFixupKind(FixupKind);
447 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
449 // All of the information is in the fixup.
453 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
454 uint32_t ARMMCCodeEmitter::
455 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
456 SmallVectorImpl<MCFixup> &Fixups) const {
457 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
460 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
461 /// BLX branch target.
462 uint32_t ARMMCCodeEmitter::
463 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups) const {
465 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
468 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
469 uint32_t ARMMCCodeEmitter::
470 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
471 SmallVectorImpl<MCFixup> &Fixups) const {
472 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
475 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
476 uint32_t ARMMCCodeEmitter::
477 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
478 SmallVectorImpl<MCFixup> &Fixups) const {
479 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
482 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
483 uint32_t ARMMCCodeEmitter::
484 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
485 SmallVectorImpl<MCFixup> &Fixups) const {
486 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
489 /// Return true if this branch has a non-always predication
490 static bool HasConditionalBranch(const MCInst &MI) {
491 int NumOp = MI.getNumOperands();
493 for (int i = 0; i < NumOp-1; ++i) {
494 const MCOperand &MCOp1 = MI.getOperand(i);
495 const MCOperand &MCOp2 = MI.getOperand(i + 1);
496 if (MCOp1.isImm() && MCOp2.isReg() &&
497 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
498 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
506 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
508 uint32_t ARMMCCodeEmitter::
509 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
510 SmallVectorImpl<MCFixup> &Fixups) const {
511 // FIXME: This really, really shouldn't use TargetMachine. We don't want
512 // coupling between MC and TM anywhere we can help it.
513 if (Subtarget->isThumb2())
515 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
516 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
519 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
521 uint32_t ARMMCCodeEmitter::
522 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups) const {
524 if (HasConditionalBranch(MI))
525 return ::getBranchTargetOpValue(MI, OpIdx,
526 ARM::fixup_arm_condbranch, Fixups);
527 return ::getBranchTargetOpValue(MI, OpIdx,
528 ARM::fixup_arm_uncondbranch, Fixups);
534 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
535 /// immediate branch target.
536 uint32_t ARMMCCodeEmitter::
537 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
538 SmallVectorImpl<MCFixup> &Fixups) const {
540 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
541 bool I = (Val & 0x800000);
542 bool J1 = (Val & 0x400000);
543 bool J2 = (Val & 0x200000);
557 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
559 uint32_t ARMMCCodeEmitter::
560 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
561 SmallVectorImpl<MCFixup> &Fixups) const {
562 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
563 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
567 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
569 uint32_t ARMMCCodeEmitter::
570 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
571 SmallVectorImpl<MCFixup> &Fixups) const {
572 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
573 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
577 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
579 uint32_t ARMMCCodeEmitter::
580 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
581 SmallVectorImpl<MCFixup> &Fixups) const {
582 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
583 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
587 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
589 uint32_t ARMMCCodeEmitter::
590 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
591 SmallVectorImpl<MCFixup> &) const {
595 const MCOperand &MO1 = MI.getOperand(OpIdx);
596 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
597 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
598 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
599 return (Rm << 3) | Rn;
602 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
603 uint32_t ARMMCCodeEmitter::
604 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
605 SmallVectorImpl<MCFixup> &Fixups) const {
607 // {12} = (U)nsigned (add == '1', sub == '0')
611 // If The first operand isn't a register, we have a label reference.
612 const MCOperand &MO = MI.getOperand(OpIdx);
614 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
616 isAdd = false ; // 'U' bit is set as part of the fixup.
618 assert(MO.isExpr() && "Unexpected machine operand type!");
619 const MCExpr *Expr = MO.getExpr();
622 if (Subtarget->isThumb2())
623 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
625 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
626 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
628 ++MCNumCPRelocations;
630 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
632 uint32_t Binary = Imm12 & 0xfff;
633 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
636 Binary |= (Reg << 13);
640 /// getT2AddrModeImm8s4OpValue - Return encoding info for
641 /// 'reg +/- imm8<<2' operand.
642 uint32_t ARMMCCodeEmitter::
643 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
644 SmallVectorImpl<MCFixup> &Fixups) const {
646 // {8} = (U)nsigned (add == '1', sub == '0')
650 // If The first operand isn't a register, we have a label reference.
651 const MCOperand &MO = MI.getOperand(OpIdx);
653 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
655 isAdd = false ; // 'U' bit is set as part of the fixup.
657 assert(MO.isExpr() && "Unexpected machine operand type!");
658 const MCExpr *Expr = MO.getExpr();
659 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
660 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
662 ++MCNumCPRelocations;
664 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
666 uint32_t Binary = (Imm8 >> 2) & 0xff;
667 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
670 Binary |= (Reg << 9);
674 // FIXME: This routine assumes that a binary
675 // expression will always result in a PCRel expression
676 // In reality, its only true if one or more subexpressions
677 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
678 // but this is good enough for now.
679 static bool EvaluateAsPCRel(const MCExpr *Expr) {
680 switch (Expr->getKind()) {
681 default: assert(0 && "Unexpected expression type");
682 case MCExpr::SymbolRef: return false;
683 case MCExpr::Binary: return true;
688 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
689 SmallVectorImpl<MCFixup> &Fixups) const {
690 // {20-16} = imm{15-12}
691 // {11-0} = imm{11-0}
692 const MCOperand &MO = MI.getOperand(OpIdx);
694 // Hi / lo 16 bits already extracted during earlier passes.
695 return static_cast<unsigned>(MO.getImm());
697 // Handle :upper16: and :lower16: assembly prefixes.
698 const MCExpr *E = MO.getExpr();
699 if (E->getKind() == MCExpr::Target) {
700 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
701 E = ARM16Expr->getSubExpr();
704 switch (ARM16Expr->getKind()) {
705 default: assert(0 && "Unsupported ARMFixup");
706 case ARMMCExpr::VK_ARM_HI16:
707 if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
708 Kind = MCFixupKind(Subtarget->isThumb2()
709 ? ARM::fixup_t2_movt_hi16_pcrel
710 : ARM::fixup_arm_movt_hi16_pcrel);
712 Kind = MCFixupKind(Subtarget->isThumb2()
713 ? ARM::fixup_t2_movt_hi16
714 : ARM::fixup_arm_movt_hi16);
716 case ARMMCExpr::VK_ARM_LO16:
717 if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
718 Kind = MCFixupKind(Subtarget->isThumb2()
719 ? ARM::fixup_t2_movw_lo16_pcrel
720 : ARM::fixup_arm_movw_lo16_pcrel);
722 Kind = MCFixupKind(Subtarget->isThumb2()
723 ? ARM::fixup_t2_movw_lo16
724 : ARM::fixup_arm_movw_lo16);
727 Fixups.push_back(MCFixup::Create(0, E, Kind));
731 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
735 uint32_t ARMMCCodeEmitter::
736 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
737 SmallVectorImpl<MCFixup> &Fixups) const {
738 const MCOperand &MO = MI.getOperand(OpIdx);
739 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
740 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
741 unsigned Rn = getARMRegisterNumbering(MO.getReg());
742 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
743 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
744 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
745 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
746 unsigned SBits = getShiftOp(ShOp);
755 uint32_t Binary = Rm;
757 Binary |= SBits << 5;
758 Binary |= ShImm << 7;
764 uint32_t ARMMCCodeEmitter::
765 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
766 SmallVectorImpl<MCFixup> &Fixups) const {
768 // {13} 1 == imm12, 0 == Rm
771 const MCOperand &MO = MI.getOperand(OpIdx);
772 unsigned Rn = getARMRegisterNumbering(MO.getReg());
773 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
778 uint32_t ARMMCCodeEmitter::
779 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
780 SmallVectorImpl<MCFixup> &Fixups) const {
781 // {13} 1 == imm12, 0 == Rm
784 const MCOperand &MO = MI.getOperand(OpIdx);
785 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
786 unsigned Imm = MO1.getImm();
787 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
788 bool isReg = MO.getReg() != 0;
789 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
790 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
792 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
793 Binary <<= 7; // Shift amount is bits [11:7]
794 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
795 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
797 return Binary | (isAdd << 12) | (isReg << 13);
800 uint32_t ARMMCCodeEmitter::
801 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
802 SmallVectorImpl<MCFixup> &Fixups) const {
803 // {9} 1 == imm8, 0 == Rm
807 const MCOperand &MO = MI.getOperand(OpIdx);
808 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
809 unsigned Imm = MO1.getImm();
810 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
811 bool isImm = MO.getReg() == 0;
812 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
813 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
815 Imm8 = getARMRegisterNumbering(MO.getReg());
816 return Imm8 | (isAdd << 8) | (isImm << 9);
819 uint32_t ARMMCCodeEmitter::
820 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
821 SmallVectorImpl<MCFixup> &Fixups) const {
822 // {13} 1 == imm8, 0 == Rm
827 const MCOperand &MO = MI.getOperand(OpIdx);
828 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
829 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
830 unsigned Rn = getARMRegisterNumbering(MO.getReg());
831 unsigned Imm = MO2.getImm();
832 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
833 bool isImm = MO1.getReg() == 0;
834 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
835 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
837 Imm8 = getARMRegisterNumbering(MO1.getReg());
838 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
841 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
842 uint32_t ARMMCCodeEmitter::
843 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
844 SmallVectorImpl<MCFixup> &Fixups) const {
847 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
848 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
849 "Unexpected base register!");
851 // The immediate is already shifted for the implicit zeroes, so no change
853 return MO1.getImm() & 0xff;
856 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
857 uint32_t ARMMCCodeEmitter::
858 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
859 SmallVectorImpl<MCFixup> &Fixups) const {
863 const MCOperand &MO = MI.getOperand(OpIdx);
864 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
865 unsigned Rn = getARMRegisterNumbering(MO.getReg());
866 unsigned Imm5 = MO1.getImm();
867 return ((Imm5 & 0x1f) << 3) | Rn;
870 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
871 uint32_t ARMMCCodeEmitter::
872 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
873 SmallVectorImpl<MCFixup> &Fixups) const {
874 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
877 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
878 uint32_t ARMMCCodeEmitter::
879 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
880 SmallVectorImpl<MCFixup> &Fixups) const {
882 // {8} = (U)nsigned (add == '1', sub == '0')
886 // If The first operand isn't a register, we have a label reference.
887 const MCOperand &MO = MI.getOperand(OpIdx);
889 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
891 isAdd = false; // 'U' bit is handled as part of the fixup.
893 assert(MO.isExpr() && "Unexpected machine operand type!");
894 const MCExpr *Expr = MO.getExpr();
896 if (Subtarget->isThumb2())
897 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
899 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
900 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
902 ++MCNumCPRelocations;
904 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
905 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
908 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
909 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
912 Binary |= (Reg << 9);
916 unsigned ARMMCCodeEmitter::
917 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
918 SmallVectorImpl<MCFixup> &Fixups) const {
919 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
920 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
921 // case the imm contains the amount to shift by.
924 // {4} = 1 if reg shift, 0 if imm shift
932 const MCOperand &MO = MI.getOperand(OpIdx);
933 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
934 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
935 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
938 unsigned Binary = getARMRegisterNumbering(MO.getReg());
940 // Encode the shift opcode.
942 unsigned Rs = MO1.getReg();
944 // Set shift operand (bit[7:4]).
949 // RRX - 0110 and bit[11:8] clear.
951 default: llvm_unreachable("Unknown shift opc!");
952 case ARM_AM::lsl: SBits = 0x1; break;
953 case ARM_AM::lsr: SBits = 0x3; break;
954 case ARM_AM::asr: SBits = 0x5; break;
955 case ARM_AM::ror: SBits = 0x7; break;
956 case ARM_AM::rrx: SBits = 0x6; break;
959 // Set shift operand (bit[6:4]).
965 default: llvm_unreachable("Unknown shift opc!");
966 case ARM_AM::lsl: SBits = 0x0; break;
967 case ARM_AM::lsr: SBits = 0x2; break;
968 case ARM_AM::asr: SBits = 0x4; break;
969 case ARM_AM::ror: SBits = 0x6; break;
973 Binary |= SBits << 4;
974 if (SOpc == ARM_AM::rrx)
977 // Encode the shift operation Rs or shift_imm (except rrx).
979 // Encode Rs bit[11:8].
980 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
981 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
984 // Encode shift_imm bit[11:7].
985 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
988 unsigned ARMMCCodeEmitter::
989 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
990 SmallVectorImpl<MCFixup> &Fixups) const {
991 const MCOperand &MO1 = MI.getOperand(OpNum);
992 const MCOperand &MO2 = MI.getOperand(OpNum+1);
993 const MCOperand &MO3 = MI.getOperand(OpNum+2);
995 // Encoded as [Rn, Rm, imm].
996 // FIXME: Needs fixup support.
997 unsigned Value = getARMRegisterNumbering(MO1.getReg());
999 Value |= getARMRegisterNumbering(MO2.getReg());
1001 Value |= MO3.getImm();
1006 unsigned ARMMCCodeEmitter::
1007 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1008 SmallVectorImpl<MCFixup> &Fixups) const {
1009 const MCOperand &MO1 = MI.getOperand(OpNum);
1010 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1012 // FIXME: Needs fixup support.
1013 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1015 // Even though the immediate is 8 bits long, we need 9 bits in order
1016 // to represent the (inverse of the) sign bit.
1018 int32_t tmp = (int32_t)MO2.getImm();
1022 Value |= 256; // Set the ADD bit
1027 unsigned ARMMCCodeEmitter::
1028 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1029 SmallVectorImpl<MCFixup> &Fixups) const {
1030 const MCOperand &MO1 = MI.getOperand(OpNum);
1032 // FIXME: Needs fixup support.
1034 int32_t tmp = (int32_t)MO1.getImm();
1038 Value |= 256; // Set the ADD bit
1043 unsigned ARMMCCodeEmitter::
1044 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1045 SmallVectorImpl<MCFixup> &Fixups) const {
1046 const MCOperand &MO1 = MI.getOperand(OpNum);
1048 // FIXME: Needs fixup support.
1050 int32_t tmp = (int32_t)MO1.getImm();
1054 Value |= 4096; // Set the ADD bit
1055 Value |= tmp & 4095;
1059 unsigned ARMMCCodeEmitter::
1060 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1061 SmallVectorImpl<MCFixup> &Fixups) const {
1062 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1063 // shifted. The second is the amount to shift by.
1070 const MCOperand &MO = MI.getOperand(OpIdx);
1071 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1072 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1075 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1077 // Encode the shift opcode.
1079 // Set shift operand (bit[6:4]).
1085 default: llvm_unreachable("Unknown shift opc!");
1086 case ARM_AM::lsl: SBits = 0x0; break;
1087 case ARM_AM::lsr: SBits = 0x2; break;
1088 case ARM_AM::asr: SBits = 0x4; break;
1089 case ARM_AM::ror: SBits = 0x6; break;
1092 Binary |= SBits << 4;
1093 if (SOpc == ARM_AM::rrx)
1096 // Encode shift_imm bit[11:7].
1097 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1100 unsigned ARMMCCodeEmitter::
1101 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1102 SmallVectorImpl<MCFixup> &Fixups) const {
1103 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1105 const MCOperand &MO = MI.getOperand(Op);
1106 uint32_t v = ~MO.getImm();
1107 uint32_t lsb = CountTrailingZeros_32(v);
1108 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1109 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1110 return lsb | (msb << 5);
1113 unsigned ARMMCCodeEmitter::
1114 getMsbOpValue(const MCInst &MI, unsigned Op,
1115 SmallVectorImpl<MCFixup> &Fixups) const {
1117 uint32_t lsb = MI.getOperand(Op-1).getImm();
1118 uint32_t width = MI.getOperand(Op).getImm();
1119 uint32_t msb = lsb+width-1;
1120 assert (width != 0 && msb < 32 && "Illegal bit width!");
1124 unsigned ARMMCCodeEmitter::
1125 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1126 SmallVectorImpl<MCFixup> &Fixups) const {
1129 // {7-0} = Number of registers
1132 // {15-0} = Bitfield of GPRs.
1133 unsigned Reg = MI.getOperand(Op).getReg();
1134 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1135 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1137 unsigned Binary = 0;
1139 if (SPRRegs || DPRRegs) {
1141 unsigned RegNo = getARMRegisterNumbering(Reg);
1142 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1143 Binary |= (RegNo & 0x1f) << 8;
1147 Binary |= NumRegs * 2;
1149 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1150 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1151 Binary |= 1 << RegNo;
1158 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1159 /// with the alignment operand.
1160 unsigned ARMMCCodeEmitter::
1161 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1162 SmallVectorImpl<MCFixup> &Fixups) const {
1163 const MCOperand &Reg = MI.getOperand(Op);
1164 const MCOperand &Imm = MI.getOperand(Op + 1);
1166 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1169 switch (Imm.getImm()) {
1173 case 8: Align = 0x01; break;
1174 case 16: Align = 0x02; break;
1175 case 32: Align = 0x03; break;
1178 return RegNo | (Align << 4);
1181 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1182 /// alignment operand for use in VLD-dup instructions. This is the same as
1183 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1184 /// different for VLD4-dup.
1185 unsigned ARMMCCodeEmitter::
1186 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1187 SmallVectorImpl<MCFixup> &Fixups) const {
1188 const MCOperand &Reg = MI.getOperand(Op);
1189 const MCOperand &Imm = MI.getOperand(Op + 1);
1191 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1194 switch (Imm.getImm()) {
1198 case 8: Align = 0x01; break;
1199 case 16: Align = 0x03; break;
1202 return RegNo | (Align << 4);
1205 unsigned ARMMCCodeEmitter::
1206 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1207 SmallVectorImpl<MCFixup> &Fixups) const {
1208 const MCOperand &MO = MI.getOperand(Op);
1209 if (MO.getReg() == 0) return 0x0D;
1213 unsigned ARMMCCodeEmitter::
1214 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1215 SmallVectorImpl<MCFixup> &Fixups) const {
1216 return 8 - MI.getOperand(Op).getImm();
1219 unsigned ARMMCCodeEmitter::
1220 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1221 SmallVectorImpl<MCFixup> &Fixups) const {
1222 return 16 - MI.getOperand(Op).getImm();
1225 unsigned ARMMCCodeEmitter::
1226 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1227 SmallVectorImpl<MCFixup> &Fixups) const {
1228 return 32 - MI.getOperand(Op).getImm();
1231 unsigned ARMMCCodeEmitter::
1232 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1233 SmallVectorImpl<MCFixup> &Fixups) const {
1234 return 64 - MI.getOperand(Op).getImm();
1237 void ARMMCCodeEmitter::
1238 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1239 SmallVectorImpl<MCFixup> &Fixups) const {
1240 // Pseudo instructions don't get encoded.
1241 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1242 uint64_t TSFlags = Desc.TSFlags;
1243 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1246 // Basic size info comes from the TSFlags field.
1247 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1248 default: llvm_unreachable("Unexpected instruction size!");
1249 case ARMII::Size2Bytes: Size = 2; break;
1250 case ARMII::Size4Bytes: Size = 4; break;
1252 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1253 // Thumb 32-bit wide instructions need to emit the high order halfword
1255 if (Subtarget->isThumb() && Size == 4) {
1256 EmitConstant(Binary >> 16, 2, OS);
1257 EmitConstant(Binary & 0xffff, 2, OS);
1259 EmitConstant(Binary, Size, OS);
1260 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1263 #include "ARMGenMCCodeEmitter.inc"