1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // This table *must* be in the order that the fixup_* kinds are defined in
51 // Name Offset (bits) Size (bits) Flags
52 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
54 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
55 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
56 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
57 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
58 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
59 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
60 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
61 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
62 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
63 { "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_arm_thumb_ldst", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
73 { "fixup_arm_movt_hi16", 0, 16, 0 },
74 { "fixup_arm_movw_lo16", 0, 16, 0 },
77 if (Kind < FirstTargetFixupKind)
78 return MCCodeEmitter::getFixupKindInfo(Kind);
80 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
82 return Infos[Kind - FirstTargetFixupKind];
84 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
86 // getBinaryCodeForInstr - TableGen'erated function for getting the
87 // binary encoding for an instruction.
88 unsigned getBinaryCodeForInstr(const MCInst &MI,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getMachineOpValue - Return binary encoding of operand. If the machine
92 /// operand requires relocation, record the relocation and return zero.
93 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
94 SmallVectorImpl<MCFixup> &Fixups) const;
96 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
97 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const;
100 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
101 unsigned &Reg, unsigned &Imm,
102 SmallVectorImpl<MCFixup> &Fixups) const;
104 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
105 /// BL branch target.
106 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
110 /// BLX branch target.
111 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
114 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups) const;
118 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
119 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
123 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
126 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
128 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
132 /// immediate Thumb2 direct branch target.
133 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
134 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
138 /// ADR label target.
139 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
140 SmallVectorImpl<MCFixup> &Fixups) const;
141 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
142 SmallVectorImpl<MCFixup> &Fixups) const;
143 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups) const;
147 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
149 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups) const;
152 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
153 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
154 SmallVectorImpl<MCFixup> &Fixups)const;
156 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
158 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups) const;
162 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
163 /// operand as needed by load/store instructions.
164 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
165 SmallVectorImpl<MCFixup> &Fixups) const;
167 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
168 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
172 default: assert(0 && "Unknown addressing sub-mode!");
173 case ARM_AM::da: return 0;
174 case ARM_AM::ia: return 1;
175 case ARM_AM::db: return 2;
176 case ARM_AM::ib: return 3;
179 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
181 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
183 default: llvm_unreachable("Unknown shift opc!");
184 case ARM_AM::no_shift:
185 case ARM_AM::lsl: return 0;
186 case ARM_AM::lsr: return 1;
187 case ARM_AM::asr: return 2;
189 case ARM_AM::rrx: return 3;
194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
196 SmallVectorImpl<MCFixup> &Fixups) const;
198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
200 SmallVectorImpl<MCFixup> &Fixups) const;
202 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
203 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
204 SmallVectorImpl<MCFixup> &Fixups) const;
206 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
207 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups) const;
210 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
212 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
213 SmallVectorImpl<MCFixup> &Fixups) const;
215 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
216 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
217 SmallVectorImpl<MCFixup> &Fixups) const;
219 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
220 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups) const;
223 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
224 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
225 SmallVectorImpl<MCFixup> &Fixups) const;
227 /// getCCOutOpValue - Return encoding of the 's' bit.
228 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
229 SmallVectorImpl<MCFixup> &Fixups) const {
230 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
232 return MI.getOperand(Op).getReg() == ARM::CPSR;
235 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
236 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
237 SmallVectorImpl<MCFixup> &Fixups) const {
238 unsigned SoImm = MI.getOperand(Op).getImm();
239 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
240 assert(SoImmVal != -1 && "Not a valid so_imm value!");
242 // Encode rotate_imm.
243 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
244 << ARMII::SoRotImmShift;
247 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
251 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
252 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
253 SmallVectorImpl<MCFixup> &Fixups) const {
254 unsigned SoImm = MI.getOperand(Op).getImm();
255 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
256 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
260 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
261 SmallVectorImpl<MCFixup> &Fixups) const;
262 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
263 SmallVectorImpl<MCFixup> &Fixups) const;
264 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
265 SmallVectorImpl<MCFixup> &Fixups) const;
266 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
267 SmallVectorImpl<MCFixup> &Fixups) const;
269 /// getSORegOpValue - Return an encoded so_reg shifted register value.
270 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
271 SmallVectorImpl<MCFixup> &Fixups) const;
272 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const {
277 switch (MI.getOperand(Op).getImm()) {
278 default: assert (0 && "Not a valid rot_imm value!");
286 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
287 SmallVectorImpl<MCFixup> &Fixups) const {
288 return MI.getOperand(Op).getImm() - 1;
291 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
292 SmallVectorImpl<MCFixup> &Fixups) const {
293 return 64 - MI.getOperand(Op).getImm();
296 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
297 SmallVectorImpl<MCFixup> &Fixups) const;
299 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
300 SmallVectorImpl<MCFixup> &Fixups) const;
301 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
302 SmallVectorImpl<MCFixup> &Fixups) const;
303 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
304 SmallVectorImpl<MCFixup> &Fixups) const;
305 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
306 SmallVectorImpl<MCFixup> &Fixups) const;
308 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
309 unsigned EncodedValue) const;
310 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
311 unsigned EncodedValue) const;
312 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
313 unsigned EncodedValue) const;
315 unsigned VFPThumb2PostEncoder(const MCInst &MI,
316 unsigned EncodedValue) const;
318 void EmitByte(unsigned char C, raw_ostream &OS) const {
322 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
323 // Output the constant in little endian byte order.
324 for (unsigned i = 0; i != Size; ++i) {
325 EmitByte(Val & 255, OS);
330 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
331 SmallVectorImpl<MCFixup> &Fixups) const;
334 } // end anonymous namespace
336 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
338 return new ARMMCCodeEmitter(TM, Ctx);
341 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
342 /// instructions, and rewrite them to their Thumb2 form if we are currently in
344 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
345 unsigned EncodedValue) const {
346 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
347 if (Subtarget.isThumb2()) {
348 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
349 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
351 unsigned Bit24 = EncodedValue & 0x01000000;
352 unsigned Bit28 = Bit24 << 4;
353 EncodedValue &= 0xEFFFFFFF;
354 EncodedValue |= Bit28;
355 EncodedValue |= 0x0F000000;
361 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
362 /// instructions, and rewrite them to their Thumb2 form if we are currently in
364 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
365 unsigned EncodedValue) const {
366 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
367 if (Subtarget.isThumb2()) {
368 EncodedValue &= 0xF0FFFFFF;
369 EncodedValue |= 0x09000000;
375 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
376 /// instructions, and rewrite them to their Thumb2 form if we are currently in
378 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
379 unsigned EncodedValue) const {
380 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
381 if (Subtarget.isThumb2()) {
382 EncodedValue &= 0x00FFFFFF;
383 EncodedValue |= 0xEE000000;
389 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
390 /// them to their Thumb2 form if we are currently in Thumb2 mode.
391 unsigned ARMMCCodeEmitter::
392 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
393 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
394 EncodedValue &= 0x0FFFFFFF;
395 EncodedValue |= 0xE0000000;
400 /// getMachineOpValue - Return binary encoding of operand. If the machine
401 /// operand requires relocation, record the relocation and return zero.
402 unsigned ARMMCCodeEmitter::
403 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
404 SmallVectorImpl<MCFixup> &Fixups) const {
406 unsigned Reg = MO.getReg();
407 unsigned RegNo = getARMRegisterNumbering(Reg);
409 // Q registers are encoded as 2x their register number.
413 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
414 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
415 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
416 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
419 } else if (MO.isImm()) {
420 return static_cast<unsigned>(MO.getImm());
421 } else if (MO.isFPImm()) {
422 return static_cast<unsigned>(APFloat(MO.getFPImm())
423 .bitcastToAPInt().getHiBits(32).getLimitedValue());
426 llvm_unreachable("Unable to encode MCOperand!");
430 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
431 bool ARMMCCodeEmitter::
432 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
433 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
434 const MCOperand &MO = MI.getOperand(OpIdx);
435 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
437 Reg = getARMRegisterNumbering(MO.getReg());
439 int32_t SImm = MO1.getImm();
442 // Special value for #-0
443 if (SImm == INT32_MIN)
446 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
456 /// getBranchTargetOpValue - Helper function to get the branch target operand,
457 /// which is either an immediate or requires a fixup.
458 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
460 SmallVectorImpl<MCFixup> &Fixups) {
461 const MCOperand &MO = MI.getOperand(OpIdx);
463 // If the destination is an immediate, we have nothing to do.
464 if (MO.isImm()) return MO.getImm();
465 assert(MO.isExpr() && "Unexpected branch target type!");
466 const MCExpr *Expr = MO.getExpr();
467 MCFixupKind Kind = MCFixupKind(FixupKind);
468 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
470 // All of the information is in the fixup.
474 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
475 uint32_t ARMMCCodeEmitter::
476 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
477 SmallVectorImpl<MCFixup> &Fixups) const {
478 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
481 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
482 /// BLX branch target.
483 uint32_t ARMMCCodeEmitter::
484 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
485 SmallVectorImpl<MCFixup> &Fixups) const {
486 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
489 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
490 uint32_t ARMMCCodeEmitter::
491 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
492 SmallVectorImpl<MCFixup> &Fixups) const {
493 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
496 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
497 uint32_t ARMMCCodeEmitter::
498 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
499 SmallVectorImpl<MCFixup> &Fixups) const {
500 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
503 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
504 uint32_t ARMMCCodeEmitter::
505 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
506 SmallVectorImpl<MCFixup> &Fixups) const {
507 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
510 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
512 uint32_t ARMMCCodeEmitter::
513 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
514 SmallVectorImpl<MCFixup> &Fixups) const {
515 // FIXME: This really, really shouldn't use TargetMachine. We don't want
516 // coupling between MC and TM anywhere we can help it.
517 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
518 if (Subtarget.isThumb2())
520 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
521 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
524 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
525 /// immediate branch target.
526 uint32_t ARMMCCodeEmitter::
527 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
528 SmallVectorImpl<MCFixup> &Fixups) const {
530 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
531 bool I = (Val & 0x800000);
532 bool J1 = (Val & 0x400000);
533 bool J2 = (Val & 0x200000);
547 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
549 uint32_t ARMMCCodeEmitter::
550 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
551 SmallVectorImpl<MCFixup> &Fixups) const {
552 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
553 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
557 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
559 uint32_t ARMMCCodeEmitter::
560 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
561 SmallVectorImpl<MCFixup> &Fixups) const {
562 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
563 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
567 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
569 uint32_t ARMMCCodeEmitter::
570 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
571 SmallVectorImpl<MCFixup> &Fixups) const {
572 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
573 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
577 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
579 uint32_t ARMMCCodeEmitter::
580 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
581 SmallVectorImpl<MCFixup> &) const {
585 const MCOperand &MO1 = MI.getOperand(OpIdx);
586 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
587 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
588 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
589 return (Rm << 3) | Rn;
592 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
593 uint32_t ARMMCCodeEmitter::
594 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
595 SmallVectorImpl<MCFixup> &Fixups) const {
597 // {12} = (U)nsigned (add == '1', sub == '0')
601 // If The first operand isn't a register, we have a label reference.
602 const MCOperand &MO = MI.getOperand(OpIdx);
603 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
604 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
605 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
607 isAdd = false ; // 'U' bit is set as part of the fixup.
609 const MCExpr *Expr = 0;
613 Expr = MO2.getExpr();
615 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
617 if (Subtarget.isThumb2())
618 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
620 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
621 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
623 ++MCNumCPRelocations;
625 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
627 uint32_t Binary = Imm12 & 0xfff;
628 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
631 Binary |= (Reg << 13);
635 /// getT2AddrModeImm8s4OpValue - Return encoding info for
636 /// 'reg +/- imm8<<2' operand.
637 uint32_t ARMMCCodeEmitter::
638 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
639 SmallVectorImpl<MCFixup> &Fixups) const {
641 // {8} = (U)nsigned (add == '1', sub == '0')
645 // If The first operand isn't a register, we have a label reference.
646 const MCOperand &MO = MI.getOperand(OpIdx);
648 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
650 isAdd = false ; // 'U' bit is set as part of the fixup.
652 assert(MO.isExpr() && "Unexpected machine operand type!");
653 const MCExpr *Expr = MO.getExpr();
654 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
655 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
657 ++MCNumCPRelocations;
659 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
661 uint32_t Binary = (Imm8 >> 2) & 0xff;
662 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
665 Binary |= (Reg << 9);
669 uint32_t ARMMCCodeEmitter::
670 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
671 SmallVectorImpl<MCFixup> &Fixups) const {
672 // {20-16} = imm{15-12}
673 // {11-0} = imm{11-0}
674 const MCOperand &MO = MI.getOperand(OpIdx);
676 return static_cast<unsigned>(MO.getImm());
677 } else if (const MCSymbolRefExpr *Expr =
678 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
680 switch (Expr->getKind()) {
681 default: assert(0 && "Unsupported ARMFixup");
682 case MCSymbolRefExpr::VK_ARM_HI16:
683 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
685 case MCSymbolRefExpr::VK_ARM_LO16:
686 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
689 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
692 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
696 uint32_t ARMMCCodeEmitter::
697 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
698 SmallVectorImpl<MCFixup> &Fixups) const {
699 const MCOperand &MO = MI.getOperand(OpIdx);
700 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
701 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
702 unsigned Rn = getARMRegisterNumbering(MO.getReg());
703 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
704 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
705 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
706 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
707 unsigned SBits = getShiftOp(ShOp);
716 uint32_t Binary = Rm;
718 Binary |= SBits << 5;
719 Binary |= ShImm << 7;
725 uint32_t ARMMCCodeEmitter::
726 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
727 SmallVectorImpl<MCFixup> &Fixups) const {
729 // {13} 1 == imm12, 0 == Rm
732 const MCOperand &MO = MI.getOperand(OpIdx);
733 unsigned Rn = getARMRegisterNumbering(MO.getReg());
734 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
739 uint32_t ARMMCCodeEmitter::
740 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
741 SmallVectorImpl<MCFixup> &Fixups) const {
742 // {13} 1 == imm12, 0 == Rm
745 const MCOperand &MO = MI.getOperand(OpIdx);
746 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
747 unsigned Imm = MO1.getImm();
748 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
749 bool isReg = MO.getReg() != 0;
750 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
751 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
753 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
754 Binary <<= 7; // Shift amount is bits [11:7]
755 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
756 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
758 return Binary | (isAdd << 12) | (isReg << 13);
761 uint32_t ARMMCCodeEmitter::
762 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
763 SmallVectorImpl<MCFixup> &Fixups) const {
764 // {9} 1 == imm8, 0 == Rm
768 const MCOperand &MO = MI.getOperand(OpIdx);
769 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
770 unsigned Imm = MO1.getImm();
771 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
772 bool isImm = MO.getReg() == 0;
773 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
774 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
776 Imm8 = getARMRegisterNumbering(MO.getReg());
777 return Imm8 | (isAdd << 8) | (isImm << 9);
780 uint32_t ARMMCCodeEmitter::
781 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
782 SmallVectorImpl<MCFixup> &Fixups) const {
783 // {13} 1 == imm8, 0 == Rm
788 const MCOperand &MO = MI.getOperand(OpIdx);
789 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
790 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
791 unsigned Rn = getARMRegisterNumbering(MO.getReg());
792 unsigned Imm = MO2.getImm();
793 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
794 bool isImm = MO1.getReg() == 0;
795 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
796 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
798 Imm8 = getARMRegisterNumbering(MO1.getReg());
799 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
802 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
803 uint32_t ARMMCCodeEmitter::
804 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
805 SmallVectorImpl<MCFixup> &Fixups) const {
808 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
809 #if 0 // FIXME: This crashes2003-05-14-initialize-string.c
810 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
811 "Unexpected base register!");
813 // The immediate is already shifted for the implicit zeroes, so no change
815 return MO1.getImm() & 0xff;
818 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
819 uint32_t ARMMCCodeEmitter::
820 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
821 SmallVectorImpl<MCFixup> &Fixups) const {
825 const MCOperand &MO = MI.getOperand(OpIdx);
826 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
827 unsigned Rn = getARMRegisterNumbering(MO.getReg());
831 const MCExpr *Expr = MO.getExpr();
832 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_ldst);
833 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
838 return ((Imm5 & 0x1f) << 3) | Rn;
841 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
842 uint32_t ARMMCCodeEmitter::
843 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
844 SmallVectorImpl<MCFixup> &Fixups) const {
845 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
848 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
849 uint32_t ARMMCCodeEmitter::
850 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
851 SmallVectorImpl<MCFixup> &Fixups) const {
853 // {8} = (U)nsigned (add == '1', sub == '0')
857 // If The first operand isn't a register, we have a label reference.
858 const MCOperand &MO = MI.getOperand(OpIdx);
860 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
862 isAdd = false; // 'U' bit is handled as part of the fixup.
864 assert(MO.isExpr() && "Unexpected machine operand type!");
865 const MCExpr *Expr = MO.getExpr();
867 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
868 if (Subtarget.isThumb2())
869 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
871 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
872 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
874 ++MCNumCPRelocations;
876 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
877 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
880 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
881 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
884 Binary |= (Reg << 9);
888 unsigned ARMMCCodeEmitter::
889 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
890 SmallVectorImpl<MCFixup> &Fixups) const {
891 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
892 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
893 // case the imm contains the amount to shift by.
896 // {4} = 1 if reg shift, 0 if imm shift
904 const MCOperand &MO = MI.getOperand(OpIdx);
905 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
906 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
907 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
910 unsigned Binary = getARMRegisterNumbering(MO.getReg());
912 // Encode the shift opcode.
914 unsigned Rs = MO1.getReg();
916 // Set shift operand (bit[7:4]).
921 // RRX - 0110 and bit[11:8] clear.
923 default: llvm_unreachable("Unknown shift opc!");
924 case ARM_AM::lsl: SBits = 0x1; break;
925 case ARM_AM::lsr: SBits = 0x3; break;
926 case ARM_AM::asr: SBits = 0x5; break;
927 case ARM_AM::ror: SBits = 0x7; break;
928 case ARM_AM::rrx: SBits = 0x6; break;
931 // Set shift operand (bit[6:4]).
937 default: llvm_unreachable("Unknown shift opc!");
938 case ARM_AM::lsl: SBits = 0x0; break;
939 case ARM_AM::lsr: SBits = 0x2; break;
940 case ARM_AM::asr: SBits = 0x4; break;
941 case ARM_AM::ror: SBits = 0x6; break;
945 Binary |= SBits << 4;
946 if (SOpc == ARM_AM::rrx)
949 // Encode the shift operation Rs or shift_imm (except rrx).
951 // Encode Rs bit[11:8].
952 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
953 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
956 // Encode shift_imm bit[11:7].
957 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
960 unsigned ARMMCCodeEmitter::
961 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
962 SmallVectorImpl<MCFixup> &Fixups) const {
963 const MCOperand &MO1 = MI.getOperand(OpNum);
964 const MCOperand &MO2 = MI.getOperand(OpNum+1);
965 const MCOperand &MO3 = MI.getOperand(OpNum+2);
967 // Encoded as [Rn, Rm, imm].
968 // FIXME: Needs fixup support.
969 unsigned Value = getARMRegisterNumbering(MO1.getReg());
971 Value |= getARMRegisterNumbering(MO2.getReg());
973 Value |= MO3.getImm();
978 unsigned ARMMCCodeEmitter::
979 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
980 SmallVectorImpl<MCFixup> &Fixups) const {
981 const MCOperand &MO1 = MI.getOperand(OpNum);
982 const MCOperand &MO2 = MI.getOperand(OpNum+1);
984 // FIXME: Needs fixup support.
985 unsigned Value = getARMRegisterNumbering(MO1.getReg());
987 // Even though the immediate is 8 bits long, we need 9 bits in order
988 // to represent the (inverse of the) sign bit.
990 int32_t tmp = (int32_t)MO2.getImm();
994 Value |= 256; // Set the ADD bit
999 unsigned ARMMCCodeEmitter::
1000 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1001 SmallVectorImpl<MCFixup> &Fixups) const {
1002 const MCOperand &MO1 = MI.getOperand(OpNum);
1004 // FIXME: Needs fixup support.
1006 int32_t tmp = (int32_t)MO1.getImm();
1010 Value |= 256; // Set the ADD bit
1015 unsigned ARMMCCodeEmitter::
1016 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1017 SmallVectorImpl<MCFixup> &Fixups) const {
1018 const MCOperand &MO1 = MI.getOperand(OpNum);
1020 // FIXME: Needs fixup support.
1022 int32_t tmp = (int32_t)MO1.getImm();
1026 Value |= 4096; // Set the ADD bit
1027 Value |= tmp & 4095;
1031 unsigned ARMMCCodeEmitter::
1032 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1033 SmallVectorImpl<MCFixup> &Fixups) const {
1034 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1035 // shifted. The second is the amount to shift by.
1042 const MCOperand &MO = MI.getOperand(OpIdx);
1043 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1044 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1047 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1049 // Encode the shift opcode.
1051 // Set shift operand (bit[6:4]).
1057 default: llvm_unreachable("Unknown shift opc!");
1058 case ARM_AM::lsl: SBits = 0x0; break;
1059 case ARM_AM::lsr: SBits = 0x2; break;
1060 case ARM_AM::asr: SBits = 0x4; break;
1061 case ARM_AM::ror: SBits = 0x6; break;
1064 Binary |= SBits << 4;
1065 if (SOpc == ARM_AM::rrx)
1068 // Encode shift_imm bit[11:7].
1069 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1072 unsigned ARMMCCodeEmitter::
1073 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1074 SmallVectorImpl<MCFixup> &Fixups) const {
1075 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1077 const MCOperand &MO = MI.getOperand(Op);
1078 uint32_t v = ~MO.getImm();
1079 uint32_t lsb = CountTrailingZeros_32(v);
1080 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1081 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1082 return lsb | (msb << 5);
1085 unsigned ARMMCCodeEmitter::
1086 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1087 SmallVectorImpl<MCFixup> &Fixups) const {
1090 // {7-0} = Number of registers
1093 // {15-0} = Bitfield of GPRs.
1094 unsigned Reg = MI.getOperand(Op).getReg();
1095 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1096 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1098 unsigned Binary = 0;
1100 if (SPRRegs || DPRRegs) {
1102 unsigned RegNo = getARMRegisterNumbering(Reg);
1103 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1104 Binary |= (RegNo & 0x1f) << 8;
1108 Binary |= NumRegs * 2;
1110 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1111 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1112 Binary |= 1 << RegNo;
1119 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1120 /// with the alignment operand.
1121 unsigned ARMMCCodeEmitter::
1122 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1123 SmallVectorImpl<MCFixup> &Fixups) const {
1124 const MCOperand &Reg = MI.getOperand(Op);
1125 const MCOperand &Imm = MI.getOperand(Op + 1);
1127 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1130 switch (Imm.getImm()) {
1134 case 8: Align = 0x01; break;
1135 case 16: Align = 0x02; break;
1136 case 32: Align = 0x03; break;
1139 return RegNo | (Align << 4);
1142 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1143 /// alignment operand for use in VLD-dup instructions. This is the same as
1144 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1145 /// different for VLD4-dup.
1146 unsigned ARMMCCodeEmitter::
1147 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1148 SmallVectorImpl<MCFixup> &Fixups) const {
1149 const MCOperand &Reg = MI.getOperand(Op);
1150 const MCOperand &Imm = MI.getOperand(Op + 1);
1152 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1155 switch (Imm.getImm()) {
1159 case 8: Align = 0x01; break;
1160 case 16: Align = 0x03; break;
1163 return RegNo | (Align << 4);
1166 unsigned ARMMCCodeEmitter::
1167 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1168 SmallVectorImpl<MCFixup> &Fixups) const {
1169 const MCOperand &MO = MI.getOperand(Op);
1170 if (MO.getReg() == 0) return 0x0D;
1174 void ARMMCCodeEmitter::
1175 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1176 SmallVectorImpl<MCFixup> &Fixups) const {
1177 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1178 // Pseudo instructions don't get encoded.
1179 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1180 uint64_t TSFlags = Desc.TSFlags;
1181 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1184 // Basic size info comes from the TSFlags field.
1185 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1186 default: llvm_unreachable("Unexpected instruction size!");
1187 case ARMII::Size2Bytes: Size = 2; break;
1188 case ARMII::Size4Bytes: Size = 4; break;
1190 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1191 // Thumb 32-bit wide instructions need to be have the high order halfword
1193 if (Subtarget.isThumb() && Size == 4) {
1194 EmitConstant(Binary >> 16, 2, OS);
1195 EmitConstant(Binary & 0xffff, 2, OS);
1197 EmitConstant(Binary, Size, OS);
1198 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1201 #include "ARMGenMCCodeEmitter.inc"