1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return 2; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
49 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
59 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
61 // getBinaryCodeForInstr - TableGen'erated function for getting the
62 // binary encoding for an instruction.
63 unsigned getBinaryCodeForInstr(const MCInst &MI,
64 SmallVectorImpl<MCFixup> &Fixups) const;
66 /// getMachineOpValue - Return binary encoding of operand. If the machine
67 /// operand requires relocation, record the relocation and return zero.
68 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
72 unsigned &Reg, unsigned &Imm,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
77 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
81 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 /// getCCOutOpValue - Return encoding of the 's' bit.
85 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
86 SmallVectorImpl<MCFixup> &Fixups) const {
87 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
89 return MI.getOperand(Op).getReg() == ARM::CPSR;
92 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
93 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
94 SmallVectorImpl<MCFixup> &Fixups) const {
95 unsigned SoImm = MI.getOperand(Op).getImm();
96 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
97 assert(SoImmVal != -1 && "Not a valid so_imm value!");
100 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
101 << ARMII::SoRotImmShift;
104 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
108 /// getSORegOpValue - Return an encoded so_reg shifted register value.
109 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
113 SmallVectorImpl<MCFixup> &Fixups) const {
114 switch (MI.getOperand(Op).getImm()) {
115 default: assert (0 && "Not a valid rot_imm value!");
123 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
124 SmallVectorImpl<MCFixup> &Fixups) const {
125 return MI.getOperand(Op).getImm() - 1;
128 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
129 SmallVectorImpl<MCFixup> &Fixups) const {
130 return 64 - MI.getOperand(Op).getImm();
133 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
134 SmallVectorImpl<MCFixup> &Fixups) const;
136 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
137 SmallVectorImpl<MCFixup> &Fixups) const;
138 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
139 SmallVectorImpl<MCFixup> &Fixups) const;
140 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 void EmitByte(unsigned char C, raw_ostream &OS) const {
147 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
148 // Output the constant in little endian byte order.
149 for (unsigned i = 0; i != Size; ++i) {
150 EmitByte(Val & 255, OS);
155 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
156 SmallVectorImpl<MCFixup> &Fixups) const;
159 } // end anonymous namespace
161 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
163 return new ARMMCCodeEmitter(TM, Ctx);
166 /// getMachineOpValue - Return binary encoding of operand. If the machine
167 /// operand requires relocation, record the relocation and return zero.
168 unsigned ARMMCCodeEmitter::
169 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
170 SmallVectorImpl<MCFixup> &Fixups) const {
172 unsigned Reg = MO.getReg();
173 unsigned RegNo = getARMRegisterNumbering(Reg);
175 // Q registers are encodes as 2x their register number.
179 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
180 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
181 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
182 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
185 } else if (MO.isImm()) {
186 return static_cast<unsigned>(MO.getImm());
187 } else if (MO.isFPImm()) {
188 return static_cast<unsigned>(APFloat(MO.getFPImm())
189 .bitcastToAPInt().getHiBits(32).getLimitedValue());
199 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
200 bool ARMMCCodeEmitter::
201 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
202 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
203 const MCOperand &MO = MI.getOperand(OpIdx);
204 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
206 Reg = getARMRegisterNumbering(MO.getReg());
208 int32_t SImm = MO1.getImm();
211 // Special value for #-0
212 if (SImm == INT32_MIN)
215 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
225 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
226 uint32_t ARMMCCodeEmitter::
227 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
228 SmallVectorImpl<MCFixup> &Fixups) const {
230 // {12} = (U)nsigned (add == '1', sub == '0')
234 // If The first operand isn't a register, we have a label reference.
235 const MCOperand &MO = MI.getOperand(OpIdx);
237 Reg = ARM::PC; // Rn is PC.
240 assert(MO.isExpr() && "Unexpected machine operand type!");
241 const MCExpr *Expr = MO.getExpr();
242 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
243 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
245 ++MCNumCPRelocations;
247 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
250 return ARM::PC << 13; // Rn is PC;
252 uint32_t Binary = Imm12 & 0xfff;
253 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
256 Binary |= (Reg << 13);
260 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
261 uint32_t ARMMCCodeEmitter::
262 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
263 SmallVectorImpl<MCFixup> &Fixups) const {
265 // {8} = (U)nsigned (add == '1', sub == '0')
268 // If The first operand isn't a register, we have a label reference.
269 const MCOperand &MO = MI.getOperand(OpIdx);
271 Reg = ARM::PC; // Rn is PC.
274 assert(MO.isExpr() && "Unexpected machine operand type!");
275 const MCExpr *Expr = MO.getExpr();
276 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
277 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
279 ++MCNumCPRelocations;
281 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
284 return ARM::PC << 9; // Rn is PC;
286 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
287 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
288 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
290 Binary |= (Reg << 9);
294 unsigned ARMMCCodeEmitter::
295 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
296 SmallVectorImpl<MCFixup> &Fixups) const {
297 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
298 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
299 // case the imm contains the amount to shift by.
302 // {4} = 1 if reg shift, 0 if imm shift
310 const MCOperand &MO = MI.getOperand(OpIdx);
311 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
312 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
313 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
316 unsigned Binary = getARMRegisterNumbering(MO.getReg());
318 // Encode the shift opcode.
320 unsigned Rs = MO1.getReg();
322 // Set shift operand (bit[7:4]).
327 // RRX - 0110 and bit[11:8] clear.
329 default: llvm_unreachable("Unknown shift opc!");
330 case ARM_AM::lsl: SBits = 0x1; break;
331 case ARM_AM::lsr: SBits = 0x3; break;
332 case ARM_AM::asr: SBits = 0x5; break;
333 case ARM_AM::ror: SBits = 0x7; break;
334 case ARM_AM::rrx: SBits = 0x6; break;
337 // Set shift operand (bit[6:4]).
343 default: llvm_unreachable("Unknown shift opc!");
344 case ARM_AM::lsl: SBits = 0x0; break;
345 case ARM_AM::lsr: SBits = 0x2; break;
346 case ARM_AM::asr: SBits = 0x4; break;
347 case ARM_AM::ror: SBits = 0x6; break;
351 Binary |= SBits << 4;
352 if (SOpc == ARM_AM::rrx)
355 // Encode the shift operation Rs or shift_imm (except rrx).
357 // Encode Rs bit[11:8].
358 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
359 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
362 // Encode shift_imm bit[11:7].
363 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
366 unsigned ARMMCCodeEmitter::
367 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
368 SmallVectorImpl<MCFixup> &Fixups) const {
369 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
371 const MCOperand &MO = MI.getOperand(Op);
372 uint32_t v = ~MO.getImm();
373 uint32_t lsb = CountTrailingZeros_32(v);
374 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
375 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
376 return lsb | (msb << 5);
379 unsigned ARMMCCodeEmitter::
380 getRegisterListOpValue(const MCInst &MI, unsigned Op,
381 SmallVectorImpl<MCFixup> &Fixups) const {
382 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
383 // register in the list, set the corresponding bit.
385 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
386 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
387 Binary |= 1 << regno;
392 unsigned ARMMCCodeEmitter::
393 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
394 SmallVectorImpl<MCFixup> &Fixups) const {
395 const MCOperand &Reg = MI.getOperand(Op);
396 const MCOperand &Imm = MI.getOperand(Op + 1);
398 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
401 switch (Imm.getImm()) {
405 case 8: Align = 0x01; break;
406 case 16: Align = 0x02; break;
407 case 32: Align = 0x03; break;
410 return RegNo | (Align << 4);
413 unsigned ARMMCCodeEmitter::
414 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
415 SmallVectorImpl<MCFixup> &Fixups) const {
416 const MCOperand &MO = MI.getOperand(Op);
417 if (MO.getReg() == 0) return 0x0D;
421 void ARMMCCodeEmitter::
422 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
423 SmallVectorImpl<MCFixup> &Fixups) const {
424 // Pseudo instructions don't get encoded.
425 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
426 if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
429 EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
430 ++MCNumEmitted; // Keep track of the # of mi's emitted.
433 #include "ARMGenMCCodeEmitter.inc"