1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMCExpr.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Support/raw_ostream.h"
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
29 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
32 class ARMMCCodeEmitter : public MCCodeEmitter {
33 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
34 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
35 const TargetMachine &TM;
36 const TargetInstrInfo &TII;
37 const ARMSubtarget *Subtarget;
41 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
42 : TM(tm), TII(*TM.getInstrInfo()),
43 Subtarget(&TM.getSubtarget<ARMSubtarget>()), Ctx(ctx) {
46 ~ARMMCCodeEmitter() {}
48 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
50 // getBinaryCodeForInstr - TableGen'erated function for getting the
51 // binary encoding for an instruction.
52 unsigned getBinaryCodeForInstr(const MCInst &MI,
53 SmallVectorImpl<MCFixup> &Fixups) const;
55 /// getMachineOpValue - Return binary encoding of operand. If the machine
56 /// operand requires relocation, record the relocation and return zero.
57 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
58 SmallVectorImpl<MCFixup> &Fixups) const;
60 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
61 /// the specified operand. This is used for operands with :lower16: and
62 /// :upper16: prefixes.
63 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
64 SmallVectorImpl<MCFixup> &Fixups) const;
66 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
67 unsigned &Reg, unsigned &Imm,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
72 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
76 /// BLX branch target.
77 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
81 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
85 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
89 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
94 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
95 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
98 /// immediate Thumb2 direct branch target.
99 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 SmallVectorImpl<MCFixup> &Fixups) const;
102 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
104 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
108 /// ADR label target.
109 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
111 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
112 SmallVectorImpl<MCFixup> &Fixups) const;
113 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
119 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
123 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups)const;
126 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
128 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
132 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
133 /// operand as needed by load/store instructions.
134 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
137 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
138 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const {
140 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
142 default: assert(0 && "Unknown addressing sub-mode!");
143 case ARM_AM::da: return 0;
144 case ARM_AM::ia: return 1;
145 case ARM_AM::db: return 2;
146 case ARM_AM::ib: return 3;
149 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
151 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
153 default: llvm_unreachable("Unknown shift opc!");
154 case ARM_AM::no_shift:
155 case ARM_AM::lsl: return 0;
156 case ARM_AM::lsr: return 1;
157 case ARM_AM::asr: return 2;
159 case ARM_AM::rrx: return 3;
164 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
165 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
169 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const;
172 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
173 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups) const;
176 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
177 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups) const;
180 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
182 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &Fixups) const;
185 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
186 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups) const;
189 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
190 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
191 SmallVectorImpl<MCFixup> &Fixups) const;
193 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
194 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups) const;
197 /// getCCOutOpValue - Return encoding of the 's' bit.
198 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
199 SmallVectorImpl<MCFixup> &Fixups) const {
200 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
202 return MI.getOperand(Op).getReg() == ARM::CPSR;
205 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
206 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
207 SmallVectorImpl<MCFixup> &Fixups) const {
208 unsigned SoImm = MI.getOperand(Op).getImm();
209 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
210 assert(SoImmVal != -1 && "Not a valid so_imm value!");
212 // Encode rotate_imm.
213 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
214 << ARMII::SoRotImmShift;
217 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
221 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
222 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
223 SmallVectorImpl<MCFixup> &Fixups) const {
224 unsigned SoImm = MI.getOperand(Op).getImm();
225 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
226 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
230 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
231 SmallVectorImpl<MCFixup> &Fixups) const;
232 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
233 SmallVectorImpl<MCFixup> &Fixups) const;
234 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
235 SmallVectorImpl<MCFixup> &Fixups) const;
236 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
237 SmallVectorImpl<MCFixup> &Fixups) const;
239 /// getSORegOpValue - Return an encoded so_reg shifted register value.
240 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
241 SmallVectorImpl<MCFixup> &Fixups) const;
242 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
243 SmallVectorImpl<MCFixup> &Fixups) const;
245 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
246 SmallVectorImpl<MCFixup> &Fixups) const {
247 switch (MI.getOperand(Op).getImm()) {
248 default: assert (0 && "Not a valid rot_imm value!");
256 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 return MI.getOperand(Op).getImm() - 1;
261 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
262 SmallVectorImpl<MCFixup> &Fixups) const {
263 return 64 - MI.getOperand(Op).getImm();
266 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
267 SmallVectorImpl<MCFixup> &Fixups) const;
269 unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
270 SmallVectorImpl<MCFixup> &Fixups) const;
272 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const;
276 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
277 SmallVectorImpl<MCFixup> &Fixups) const;
278 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
279 SmallVectorImpl<MCFixup> &Fixups) const;
280 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
281 SmallVectorImpl<MCFixup> &Fixups) const;
283 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
284 SmallVectorImpl<MCFixup> &Fixups) const;
285 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
286 SmallVectorImpl<MCFixup> &Fixups) const;
287 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
288 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
292 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
293 unsigned EncodedValue) const;
294 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
295 unsigned EncodedValue) const;
296 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
297 unsigned EncodedValue) const;
299 unsigned VFPThumb2PostEncoder(const MCInst &MI,
300 unsigned EncodedValue) const;
302 void EmitByte(unsigned char C, raw_ostream &OS) const {
306 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
307 // Output the constant in little endian byte order.
308 for (unsigned i = 0; i != Size; ++i) {
309 EmitByte(Val & 255, OS);
314 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
315 SmallVectorImpl<MCFixup> &Fixups) const;
318 } // end anonymous namespace
320 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
322 return new ARMMCCodeEmitter(TM, Ctx);
325 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
326 /// instructions, and rewrite them to their Thumb2 form if we are currently in
328 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
329 unsigned EncodedValue) const {
330 if (Subtarget->isThumb2()) {
331 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
332 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
334 unsigned Bit24 = EncodedValue & 0x01000000;
335 unsigned Bit28 = Bit24 << 4;
336 EncodedValue &= 0xEFFFFFFF;
337 EncodedValue |= Bit28;
338 EncodedValue |= 0x0F000000;
344 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
345 /// instructions, and rewrite them to their Thumb2 form if we are currently in
347 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
348 unsigned EncodedValue) const {
349 if (Subtarget->isThumb2()) {
350 EncodedValue &= 0xF0FFFFFF;
351 EncodedValue |= 0x09000000;
357 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
358 /// instructions, and rewrite them to their Thumb2 form if we are currently in
360 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
361 unsigned EncodedValue) const {
362 if (Subtarget->isThumb2()) {
363 EncodedValue &= 0x00FFFFFF;
364 EncodedValue |= 0xEE000000;
370 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
371 /// them to their Thumb2 form if we are currently in Thumb2 mode.
372 unsigned ARMMCCodeEmitter::
373 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
374 if (Subtarget->isThumb2()) {
375 EncodedValue &= 0x0FFFFFFF;
376 EncodedValue |= 0xE0000000;
381 /// getMachineOpValue - Return binary encoding of operand. If the machine
382 /// operand requires relocation, record the relocation and return zero.
383 unsigned ARMMCCodeEmitter::
384 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
385 SmallVectorImpl<MCFixup> &Fixups) const {
387 unsigned Reg = MO.getReg();
388 unsigned RegNo = getARMRegisterNumbering(Reg);
390 // Q registers are encoded as 2x their register number.
394 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
395 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
396 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
397 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
400 } else if (MO.isImm()) {
401 return static_cast<unsigned>(MO.getImm());
402 } else if (MO.isFPImm()) {
403 return static_cast<unsigned>(APFloat(MO.getFPImm())
404 .bitcastToAPInt().getHiBits(32).getLimitedValue());
407 llvm_unreachable("Unable to encode MCOperand!");
411 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
412 bool ARMMCCodeEmitter::
413 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
414 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
415 const MCOperand &MO = MI.getOperand(OpIdx);
416 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
418 Reg = getARMRegisterNumbering(MO.getReg());
420 int32_t SImm = MO1.getImm();
423 // Special value for #-0
424 if (SImm == INT32_MIN)
427 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
437 /// getBranchTargetOpValue - Helper function to get the branch target operand,
438 /// which is either an immediate or requires a fixup.
439 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
441 SmallVectorImpl<MCFixup> &Fixups) {
442 const MCOperand &MO = MI.getOperand(OpIdx);
444 // If the destination is an immediate, we have nothing to do.
445 if (MO.isImm()) return MO.getImm();
446 assert(MO.isExpr() && "Unexpected branch target type!");
447 const MCExpr *Expr = MO.getExpr();
448 MCFixupKind Kind = MCFixupKind(FixupKind);
449 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
451 // All of the information is in the fixup.
455 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
456 uint32_t ARMMCCodeEmitter::
457 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
458 SmallVectorImpl<MCFixup> &Fixups) const {
459 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
462 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
463 /// BLX branch target.
464 uint32_t ARMMCCodeEmitter::
465 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
466 SmallVectorImpl<MCFixup> &Fixups) const {
467 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
470 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
471 uint32_t ARMMCCodeEmitter::
472 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
473 SmallVectorImpl<MCFixup> &Fixups) const {
474 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
477 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
478 uint32_t ARMMCCodeEmitter::
479 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
480 SmallVectorImpl<MCFixup> &Fixups) const {
481 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
484 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
485 uint32_t ARMMCCodeEmitter::
486 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
487 SmallVectorImpl<MCFixup> &Fixups) const {
488 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
491 /// Return true if this branch has a non-always predication
492 static bool HasConditionalBranch(const MCInst &MI) {
493 int NumOp = MI.getNumOperands();
495 for (int i = 0; i < NumOp-1; ++i) {
496 const MCOperand &MCOp1 = MI.getOperand(i);
497 const MCOperand &MCOp2 = MI.getOperand(i + 1);
498 if (MCOp1.isImm() && MCOp2.isReg() &&
499 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
500 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
508 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
510 uint32_t ARMMCCodeEmitter::
511 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 // FIXME: This really, really shouldn't use TargetMachine. We don't want
514 // coupling between MC and TM anywhere we can help it.
515 if (Subtarget->isThumb2())
517 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
518 return getARMBranchTargetOpValue(MI, OpIdx, Fixups);
521 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
523 uint32_t ARMMCCodeEmitter::
524 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
525 SmallVectorImpl<MCFixup> &Fixups) const {
526 if (HasConditionalBranch(MI))
527 return ::getBranchTargetOpValue(MI, OpIdx,
528 ARM::fixup_arm_condbranch, Fixups);
529 return ::getBranchTargetOpValue(MI, OpIdx,
530 ARM::fixup_arm_uncondbranch, Fixups);
536 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
537 /// immediate branch target.
538 uint32_t ARMMCCodeEmitter::
539 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
540 SmallVectorImpl<MCFixup> &Fixups) const {
542 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
543 bool I = (Val & 0x800000);
544 bool J1 = (Val & 0x400000);
545 bool J2 = (Val & 0x200000);
559 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
561 uint32_t ARMMCCodeEmitter::
562 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
563 SmallVectorImpl<MCFixup> &Fixups) const {
564 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
565 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
569 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
571 uint32_t ARMMCCodeEmitter::
572 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
573 SmallVectorImpl<MCFixup> &Fixups) const {
574 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
575 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
579 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
581 uint32_t ARMMCCodeEmitter::
582 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
583 SmallVectorImpl<MCFixup> &Fixups) const {
584 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
585 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
589 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
591 uint32_t ARMMCCodeEmitter::
592 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
593 SmallVectorImpl<MCFixup> &) const {
597 const MCOperand &MO1 = MI.getOperand(OpIdx);
598 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
599 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
600 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
601 return (Rm << 3) | Rn;
604 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
605 uint32_t ARMMCCodeEmitter::
606 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
607 SmallVectorImpl<MCFixup> &Fixups) const {
609 // {12} = (U)nsigned (add == '1', sub == '0')
613 // If The first operand isn't a register, we have a label reference.
614 const MCOperand &MO = MI.getOperand(OpIdx);
616 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
618 isAdd = false ; // 'U' bit is set as part of the fixup.
620 assert(MO.isExpr() && "Unexpected machine operand type!");
621 const MCExpr *Expr = MO.getExpr();
624 if (Subtarget->isThumb2())
625 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
627 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
628 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
630 ++MCNumCPRelocations;
632 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
634 uint32_t Binary = Imm12 & 0xfff;
635 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
638 Binary |= (Reg << 13);
642 /// getT2AddrModeImm8s4OpValue - Return encoding info for
643 /// 'reg +/- imm8<<2' operand.
644 uint32_t ARMMCCodeEmitter::
645 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
646 SmallVectorImpl<MCFixup> &Fixups) const {
648 // {8} = (U)nsigned (add == '1', sub == '0')
652 // If The first operand isn't a register, we have a label reference.
653 const MCOperand &MO = MI.getOperand(OpIdx);
655 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
657 isAdd = false ; // 'U' bit is set as part of the fixup.
659 assert(MO.isExpr() && "Unexpected machine operand type!");
660 const MCExpr *Expr = MO.getExpr();
661 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
662 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
664 ++MCNumCPRelocations;
666 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
668 uint32_t Binary = (Imm8 >> 2) & 0xff;
669 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
672 Binary |= (Reg << 9);
676 // FIXME: This routine assumes that a binary
677 // expression will always result in a PCRel expression
678 // In reality, its only true if one or more subexpressions
679 // is itself a PCRel (i.e. "." in asm or some other pcrel construct)
680 // but this is good enough for now.
681 static bool EvaluateAsPCRel(const MCExpr *Expr) {
682 switch (Expr->getKind()) {
683 default: assert(0 && "Unexpected expression type");
684 case MCExpr::SymbolRef: return false;
685 case MCExpr::Binary: return true;
690 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
691 SmallVectorImpl<MCFixup> &Fixups) const {
692 // {20-16} = imm{15-12}
693 // {11-0} = imm{11-0}
694 const MCOperand &MO = MI.getOperand(OpIdx);
696 // Hi / lo 16 bits already extracted during earlier passes.
697 return static_cast<unsigned>(MO.getImm());
699 // Handle :upper16: and :lower16: assembly prefixes.
700 const MCExpr *E = MO.getExpr();
701 if (E->getKind() == MCExpr::Target) {
702 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
703 E = ARM16Expr->getSubExpr();
706 switch (ARM16Expr->getKind()) {
707 default: assert(0 && "Unsupported ARMFixup");
708 case ARMMCExpr::VK_ARM_HI16:
709 if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
710 Kind = MCFixupKind(Subtarget->isThumb2()
711 ? ARM::fixup_t2_movt_hi16_pcrel
712 : ARM::fixup_arm_movt_hi16_pcrel);
714 Kind = MCFixupKind(Subtarget->isThumb2()
715 ? ARM::fixup_t2_movt_hi16
716 : ARM::fixup_arm_movt_hi16);
718 case ARMMCExpr::VK_ARM_LO16:
719 if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E))
720 Kind = MCFixupKind(Subtarget->isThumb2()
721 ? ARM::fixup_t2_movw_lo16_pcrel
722 : ARM::fixup_arm_movw_lo16_pcrel);
724 Kind = MCFixupKind(Subtarget->isThumb2()
725 ? ARM::fixup_t2_movw_lo16
726 : ARM::fixup_arm_movw_lo16);
729 Fixups.push_back(MCFixup::Create(0, E, Kind));
733 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
737 uint32_t ARMMCCodeEmitter::
738 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
739 SmallVectorImpl<MCFixup> &Fixups) const {
740 const MCOperand &MO = MI.getOperand(OpIdx);
741 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
742 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
743 unsigned Rn = getARMRegisterNumbering(MO.getReg());
744 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
745 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
746 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
747 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
748 unsigned SBits = getShiftOp(ShOp);
757 uint32_t Binary = Rm;
759 Binary |= SBits << 5;
760 Binary |= ShImm << 7;
766 uint32_t ARMMCCodeEmitter::
767 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
768 SmallVectorImpl<MCFixup> &Fixups) const {
770 // {13} 1 == imm12, 0 == Rm
773 const MCOperand &MO = MI.getOperand(OpIdx);
774 unsigned Rn = getARMRegisterNumbering(MO.getReg());
775 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
780 uint32_t ARMMCCodeEmitter::
781 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
782 SmallVectorImpl<MCFixup> &Fixups) const {
783 // {13} 1 == imm12, 0 == Rm
786 const MCOperand &MO = MI.getOperand(OpIdx);
787 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
788 unsigned Imm = MO1.getImm();
789 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
790 bool isReg = MO.getReg() != 0;
791 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
792 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
794 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
795 Binary <<= 7; // Shift amount is bits [11:7]
796 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
797 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
799 return Binary | (isAdd << 12) | (isReg << 13);
802 uint32_t ARMMCCodeEmitter::
803 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
804 SmallVectorImpl<MCFixup> &Fixups) const {
805 // {9} 1 == imm8, 0 == Rm
809 const MCOperand &MO = MI.getOperand(OpIdx);
810 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
811 unsigned Imm = MO1.getImm();
812 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
813 bool isImm = MO.getReg() == 0;
814 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
815 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
817 Imm8 = getARMRegisterNumbering(MO.getReg());
818 return Imm8 | (isAdd << 8) | (isImm << 9);
821 uint32_t ARMMCCodeEmitter::
822 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
823 SmallVectorImpl<MCFixup> &Fixups) const {
824 // {13} 1 == imm8, 0 == Rm
829 const MCOperand &MO = MI.getOperand(OpIdx);
830 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
831 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
832 unsigned Rn = getARMRegisterNumbering(MO.getReg());
833 unsigned Imm = MO2.getImm();
834 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
835 bool isImm = MO1.getReg() == 0;
836 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
837 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
839 Imm8 = getARMRegisterNumbering(MO1.getReg());
840 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
843 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
844 uint32_t ARMMCCodeEmitter::
845 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
846 SmallVectorImpl<MCFixup> &Fixups) const {
849 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
850 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
851 "Unexpected base register!");
853 // The immediate is already shifted for the implicit zeroes, so no change
855 return MO1.getImm() & 0xff;
858 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
859 uint32_t ARMMCCodeEmitter::
860 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
861 SmallVectorImpl<MCFixup> &Fixups) const {
865 const MCOperand &MO = MI.getOperand(OpIdx);
866 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
867 unsigned Rn = getARMRegisterNumbering(MO.getReg());
868 unsigned Imm5 = MO1.getImm();
869 return ((Imm5 & 0x1f) << 3) | Rn;
872 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
873 uint32_t ARMMCCodeEmitter::
874 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
875 SmallVectorImpl<MCFixup> &Fixups) const {
876 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
879 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
880 uint32_t ARMMCCodeEmitter::
881 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
882 SmallVectorImpl<MCFixup> &Fixups) const {
884 // {8} = (U)nsigned (add == '1', sub == '0')
888 // If The first operand isn't a register, we have a label reference.
889 const MCOperand &MO = MI.getOperand(OpIdx);
891 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
893 isAdd = false; // 'U' bit is handled as part of the fixup.
895 assert(MO.isExpr() && "Unexpected machine operand type!");
896 const MCExpr *Expr = MO.getExpr();
898 if (Subtarget->isThumb2())
899 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
901 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
902 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
904 ++MCNumCPRelocations;
906 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
907 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
910 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
911 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
914 Binary |= (Reg << 9);
918 unsigned ARMMCCodeEmitter::
919 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
920 SmallVectorImpl<MCFixup> &Fixups) const {
921 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
922 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
923 // case the imm contains the amount to shift by.
926 // {4} = 1 if reg shift, 0 if imm shift
934 const MCOperand &MO = MI.getOperand(OpIdx);
935 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
936 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
937 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
940 unsigned Binary = getARMRegisterNumbering(MO.getReg());
942 // Encode the shift opcode.
944 unsigned Rs = MO1.getReg();
946 // Set shift operand (bit[7:4]).
951 // RRX - 0110 and bit[11:8] clear.
953 default: llvm_unreachable("Unknown shift opc!");
954 case ARM_AM::lsl: SBits = 0x1; break;
955 case ARM_AM::lsr: SBits = 0x3; break;
956 case ARM_AM::asr: SBits = 0x5; break;
957 case ARM_AM::ror: SBits = 0x7; break;
958 case ARM_AM::rrx: SBits = 0x6; break;
961 // Set shift operand (bit[6:4]).
967 default: llvm_unreachable("Unknown shift opc!");
968 case ARM_AM::lsl: SBits = 0x0; break;
969 case ARM_AM::lsr: SBits = 0x2; break;
970 case ARM_AM::asr: SBits = 0x4; break;
971 case ARM_AM::ror: SBits = 0x6; break;
975 Binary |= SBits << 4;
976 if (SOpc == ARM_AM::rrx)
979 // Encode the shift operation Rs or shift_imm (except rrx).
981 // Encode Rs bit[11:8].
982 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
983 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
986 // Encode shift_imm bit[11:7].
987 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
990 unsigned ARMMCCodeEmitter::
991 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
992 SmallVectorImpl<MCFixup> &Fixups) const {
993 const MCOperand &MO1 = MI.getOperand(OpNum);
994 const MCOperand &MO2 = MI.getOperand(OpNum+1);
995 const MCOperand &MO3 = MI.getOperand(OpNum+2);
997 // Encoded as [Rn, Rm, imm].
998 // FIXME: Needs fixup support.
999 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1001 Value |= getARMRegisterNumbering(MO2.getReg());
1003 Value |= MO3.getImm();
1008 unsigned ARMMCCodeEmitter::
1009 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1010 SmallVectorImpl<MCFixup> &Fixups) const {
1011 const MCOperand &MO1 = MI.getOperand(OpNum);
1012 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1014 // FIXME: Needs fixup support.
1015 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1017 // Even though the immediate is 8 bits long, we need 9 bits in order
1018 // to represent the (inverse of the) sign bit.
1020 int32_t tmp = (int32_t)MO2.getImm();
1024 Value |= 256; // Set the ADD bit
1029 unsigned ARMMCCodeEmitter::
1030 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1031 SmallVectorImpl<MCFixup> &Fixups) const {
1032 const MCOperand &MO1 = MI.getOperand(OpNum);
1034 // FIXME: Needs fixup support.
1036 int32_t tmp = (int32_t)MO1.getImm();
1040 Value |= 256; // Set the ADD bit
1045 unsigned ARMMCCodeEmitter::
1046 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1047 SmallVectorImpl<MCFixup> &Fixups) const {
1048 const MCOperand &MO1 = MI.getOperand(OpNum);
1050 // FIXME: Needs fixup support.
1052 int32_t tmp = (int32_t)MO1.getImm();
1056 Value |= 4096; // Set the ADD bit
1057 Value |= tmp & 4095;
1061 unsigned ARMMCCodeEmitter::
1062 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1063 SmallVectorImpl<MCFixup> &Fixups) const {
1064 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1065 // shifted. The second is the amount to shift by.
1072 const MCOperand &MO = MI.getOperand(OpIdx);
1073 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1074 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1077 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1079 // Encode the shift opcode.
1081 // Set shift operand (bit[6:4]).
1087 default: llvm_unreachable("Unknown shift opc!");
1088 case ARM_AM::lsl: SBits = 0x0; break;
1089 case ARM_AM::lsr: SBits = 0x2; break;
1090 case ARM_AM::asr: SBits = 0x4; break;
1091 case ARM_AM::ror: SBits = 0x6; break;
1094 Binary |= SBits << 4;
1095 if (SOpc == ARM_AM::rrx)
1098 // Encode shift_imm bit[11:7].
1099 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1102 unsigned ARMMCCodeEmitter::
1103 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1104 SmallVectorImpl<MCFixup> &Fixups) const {
1105 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1107 const MCOperand &MO = MI.getOperand(Op);
1108 uint32_t v = ~MO.getImm();
1109 uint32_t lsb = CountTrailingZeros_32(v);
1110 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1111 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1112 return lsb | (msb << 5);
1115 unsigned ARMMCCodeEmitter::
1116 getMsbOpValue(const MCInst &MI, unsigned Op,
1117 SmallVectorImpl<MCFixup> &Fixups) const {
1119 uint32_t lsb = MI.getOperand(Op-1).getImm();
1120 uint32_t width = MI.getOperand(Op).getImm();
1121 uint32_t msb = lsb+width-1;
1122 assert (width != 0 && msb < 32 && "Illegal bit width!");
1126 unsigned ARMMCCodeEmitter::
1127 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1128 SmallVectorImpl<MCFixup> &Fixups) const {
1131 // {7-0} = Number of registers
1134 // {15-0} = Bitfield of GPRs.
1135 unsigned Reg = MI.getOperand(Op).getReg();
1136 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1137 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1139 unsigned Binary = 0;
1141 if (SPRRegs || DPRRegs) {
1143 unsigned RegNo = getARMRegisterNumbering(Reg);
1144 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1145 Binary |= (RegNo & 0x1f) << 8;
1149 Binary |= NumRegs * 2;
1151 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1152 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1153 Binary |= 1 << RegNo;
1160 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1161 /// with the alignment operand.
1162 unsigned ARMMCCodeEmitter::
1163 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1164 SmallVectorImpl<MCFixup> &Fixups) const {
1165 const MCOperand &Reg = MI.getOperand(Op);
1166 const MCOperand &Imm = MI.getOperand(Op + 1);
1168 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1171 switch (Imm.getImm()) {
1175 case 8: Align = 0x01; break;
1176 case 16: Align = 0x02; break;
1177 case 32: Align = 0x03; break;
1180 return RegNo | (Align << 4);
1183 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1184 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1185 unsigned ARMMCCodeEmitter::
1186 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1187 SmallVectorImpl<MCFixup> &Fixups) const {
1188 const MCOperand &Reg = MI.getOperand(Op);
1189 const MCOperand &Imm = MI.getOperand(Op + 1);
1191 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1194 switch (Imm.getImm()) {
1199 case 16: Align = 0x00; break;
1200 case 32: Align = 0x03; break;
1203 return RegNo | (Align << 4);
1207 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1208 /// alignment operand for use in VLD-dup instructions. This is the same as
1209 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1210 /// different for VLD4-dup.
1211 unsigned ARMMCCodeEmitter::
1212 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1213 SmallVectorImpl<MCFixup> &Fixups) const {
1214 const MCOperand &Reg = MI.getOperand(Op);
1215 const MCOperand &Imm = MI.getOperand(Op + 1);
1217 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1220 switch (Imm.getImm()) {
1224 case 8: Align = 0x01; break;
1225 case 16: Align = 0x03; break;
1228 return RegNo | (Align << 4);
1231 unsigned ARMMCCodeEmitter::
1232 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1233 SmallVectorImpl<MCFixup> &Fixups) const {
1234 const MCOperand &MO = MI.getOperand(Op);
1235 if (MO.getReg() == 0) return 0x0D;
1239 unsigned ARMMCCodeEmitter::
1240 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1241 SmallVectorImpl<MCFixup> &Fixups) const {
1242 return 8 - MI.getOperand(Op).getImm();
1245 unsigned ARMMCCodeEmitter::
1246 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1247 SmallVectorImpl<MCFixup> &Fixups) const {
1248 return 16 - MI.getOperand(Op).getImm();
1251 unsigned ARMMCCodeEmitter::
1252 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1253 SmallVectorImpl<MCFixup> &Fixups) const {
1254 return 32 - MI.getOperand(Op).getImm();
1257 unsigned ARMMCCodeEmitter::
1258 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1259 SmallVectorImpl<MCFixup> &Fixups) const {
1260 return 64 - MI.getOperand(Op).getImm();
1263 void ARMMCCodeEmitter::
1264 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1265 SmallVectorImpl<MCFixup> &Fixups) const {
1266 // Pseudo instructions don't get encoded.
1267 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1268 uint64_t TSFlags = Desc.TSFlags;
1269 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1272 // Basic size info comes from the TSFlags field.
1273 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1274 default: llvm_unreachable("Unexpected instruction size!");
1275 case ARMII::Size2Bytes: Size = 2; break;
1276 case ARMII::Size4Bytes: Size = 4; break;
1278 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1279 // Thumb 32-bit wide instructions need to emit the high order halfword
1281 if (Subtarget->isThumb() && Size == 4) {
1282 EmitConstant(Binary >> 16, 2, OS);
1283 EmitConstant(Binary & 0xffff, 2, OS);
1285 EmitConstant(Binary, Size, OS);
1286 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1289 #include "ARMGenMCCodeEmitter.inc"