1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class ARMMCCodeEmitter : public MCCodeEmitter {
29 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
32 const TargetInstrInfo &TII;
36 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
37 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
40 ~ARMMCCodeEmitter() {}
42 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
44 // getBinaryCodeForInstr - TableGen'erated function for getting the
45 // binary encoding for an instruction.
46 unsigned getBinaryCodeForInstr(const MCInst &MI) const;
48 /// getMachineOpValue - Return binary encoding of operand. If the machine
49 /// operand requires relocation, record the relocation and return zero.
50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
52 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
53 uint32_t getAddrModeImmOpValue(const MCInst &MI, unsigned Op) const;
55 /// getCCOutOpValue - Return encoding of the 's' bit.
56 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
57 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
59 return MI.getOperand(Op).getReg() == ARM::CPSR;
62 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
63 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const {
64 unsigned SoImm = MI.getOperand(Op).getImm();
65 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
66 assert(SoImmVal != -1 && "Not a valid so_imm value!");
69 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
70 << ARMII::SoRotImmShift;
73 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
77 /// getSORegOpValue - Return an encoded so_reg shifted register value.
78 unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const;
80 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const {
81 switch (MI.getOperand(Op).getImm()) {
82 default: assert (0 && "Not a valid rot_imm value!");
90 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
91 return MI.getOperand(Op).getImm() - 1;
94 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op) const {
95 return 64 - MI.getOperand(Op).getImm();
98 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
100 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
101 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const;
102 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const;
104 unsigned getNumFixupKinds() const {
105 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
109 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
110 static MCFixupKindInfo rtn;
111 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
115 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
120 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
121 raw_ostream &OS) const {
122 // Output the constant in little endian byte order.
123 for (unsigned i = 0; i != Size; ++i) {
124 EmitByte(Val & 255, CurByte, OS);
129 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
130 SmallVectorImpl<MCFixup> &Fixups) const;
133 } // end anonymous namespace
135 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
138 return new ARMMCCodeEmitter(TM, Ctx);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
144 const MCOperand &MO) const {
146 unsigned regno = getARMRegisterNumbering(MO.getReg());
148 // Q registers are encodes as 2x their register number.
149 switch (MO.getReg()) {
150 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
151 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
152 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
153 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
158 } else if (MO.isImm()) {
159 return static_cast<unsigned>(MO.getImm());
160 } else if (MO.isFPImm()) {
161 return static_cast<unsigned>(APFloat(MO.getFPImm())
162 .bitcastToAPInt().getHiBits(32).getLimitedValue());
172 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
173 uint32_t ARMMCCodeEmitter::getAddrModeImmOpValue(const MCInst &MI,
174 unsigned OpIdx) const {
176 // {16} = (U)nsigned (add == '1', sub == '0')
178 const MCOperand &MO = MI.getOperand(OpIdx);
179 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
182 // If The first operand isn't a register, we have a label reference.
184 Binary |= ARM::PC << 17; // Rn is PC.
185 // FIXME: Add a fixup referencing the label.
189 unsigned Reg = getARMRegisterNumbering(MO.getReg());
190 int32_t Imm = MO1.getImm();
191 bool isAdd = Imm >= 0;
193 // Special value for #-0
194 if (Imm == INT32_MIN)
197 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
198 if (Imm < 0) Imm = -Imm;
200 Binary = Imm & 0xffff;
203 Binary |= (Reg << 17);
207 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
208 unsigned OpIdx) const {
209 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg
210 // to be shifted. The second is either Rs, the amount to shift by, or
211 // reg0 in which case the imm contains the amount to shift by.
213 // {4} = 1 if reg shift, 0 if imm shift
221 const MCOperand &MO = MI.getOperand(OpIdx);
222 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
223 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
224 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
227 unsigned Binary = getARMRegisterNumbering(MO.getReg());
229 // Encode the shift opcode.
231 unsigned Rs = MO1.getReg();
233 // Set shift operand (bit[7:4]).
238 // RRX - 0110 and bit[11:8] clear.
240 default: llvm_unreachable("Unknown shift opc!");
241 case ARM_AM::lsl: SBits = 0x1; break;
242 case ARM_AM::lsr: SBits = 0x3; break;
243 case ARM_AM::asr: SBits = 0x5; break;
244 case ARM_AM::ror: SBits = 0x7; break;
245 case ARM_AM::rrx: SBits = 0x6; break;
248 // Set shift operand (bit[6:4]).
254 default: llvm_unreachable("Unknown shift opc!");
255 case ARM_AM::lsl: SBits = 0x0; break;
256 case ARM_AM::lsr: SBits = 0x2; break;
257 case ARM_AM::asr: SBits = 0x4; break;
258 case ARM_AM::ror: SBits = 0x6; break;
261 Binary |= SBits << 4;
262 if (SOpc == ARM_AM::rrx)
265 // Encode the shift operation Rs or shift_imm (except rrx).
267 // Encode Rs bit[11:8].
268 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
269 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
272 // Encode shift_imm bit[11:7].
273 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
276 unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
278 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
280 const MCOperand &MO = MI.getOperand(Op);
281 uint32_t v = ~MO.getImm();
282 uint32_t lsb = CountTrailingZeros_32(v);
283 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
284 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
285 return lsb | (msb << 5);
288 unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
290 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
291 // register in the list, set the corresponding bit.
293 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
294 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
295 Binary |= 1 << regno;
300 unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
302 const MCOperand &Reg = MI.getOperand(Op);
303 const MCOperand &Imm = MI.getOperand(Op+1);
305 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
306 unsigned Align = Imm.getImm();
308 case 2: case 4: case 8: Align = 0x01; break;
309 case 16: Align = 0x02; break;
310 case 32: Align = 0x03; break;
311 default: Align = 0x00; break;
313 return RegNo | (Align << 4);
316 unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI,
318 const MCOperand ®no = MI.getOperand(Op);
319 if (regno.getReg() == 0) return 0x0D;
320 return regno.getReg();
323 void ARMMCCodeEmitter::
324 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
325 SmallVectorImpl<MCFixup> &) const {
326 // Pseudo instructions don't get encoded.
327 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
328 if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
331 // Keep track of the current byte being emitted.
332 unsigned CurByte = 0;
333 EmitConstant(getBinaryCodeForInstr(MI), 4, CurByte, OS);
334 ++MCNumEmitted; // Keep track of the # of mi's emitted.
337 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
338 // be able to generate code emitter helpers for either variant, like it
339 // does for the AsmWriter.
340 #define ARMCodeEmitter ARMMCCodeEmitter
341 #define MachineInstr MCInst
342 #include "ARMGenCodeEmitter.inc"
343 #undef ARMCodeEmitter