1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMInstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
24 class ARMMCCodeEmitter : public MCCodeEmitter {
25 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
26 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
27 const TargetMachine &TM;
28 const TargetInstrInfo &TII;
32 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
33 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
34 assert(0 && "ARMMCCodeEmitter::ARMMCCodeEmitter() not yet implemented.");
37 ~ARMMCCodeEmitter() {}
39 unsigned getNumFixupKinds() const {
40 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 static MCFixupKindInfo rtn;
46 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
50 static unsigned GetARMRegNum(const MCOperand &MO) {
51 // FIXME: getARMRegisterNumbering() is sufficient?
52 assert(0 && "ARMMCCodeEmitter::GetARMRegNum() not yet implemented.");
56 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
61 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
62 raw_ostream &OS) const {
63 // Output the constant in little endian byte order.
64 for (unsigned i = 0; i != Size; ++i) {
65 EmitByte(Val & 255, CurByte, OS);
70 void EmitImmediate(const MCOperand &Disp,
71 unsigned ImmSize, MCFixupKind FixupKind,
72 unsigned &CurByte, raw_ostream &OS,
73 SmallVectorImpl<MCFixup> &Fixups,
74 int ImmOffset = 0) const;
76 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
77 SmallVectorImpl<MCFixup> &Fixups) const;
79 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
80 const MCInst &MI, const TargetInstrDesc &Desc,
81 raw_ostream &OS) const;
84 } // end anonymous namespace
87 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
90 return new ARMMCCodeEmitter(TM, Ctx);
93 void ARMMCCodeEmitter::
94 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
95 unsigned &CurByte, raw_ostream &OS,
96 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
97 assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
100 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
102 /// MemOperand is the operand # of the start of a memory operand if present. If
103 /// Not present, it is -1.
104 void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
105 int MemOperand, const MCInst &MI,
106 const TargetInstrDesc &Desc,
107 raw_ostream &OS) const {
108 assert(0 && "ARMMCCodeEmitter::EmitOpcodePrefix() not yet implemented.");
111 void ARMMCCodeEmitter::
112 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
113 SmallVectorImpl<MCFixup> &Fixups) const {
114 assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented.");