1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
74 unsigned &Reg, unsigned &Imm,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
79 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
84 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
88 /// operand as needed by load/store instructions.
89 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
93 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const {
95 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
97 default: assert(0 && "Unknown addressing sub-mode!");
98 case ARM_AM::da: return 0;
99 case ARM_AM::ia: return 1;
100 case ARM_AM::db: return 2;
101 case ARM_AM::ib: return 3;
104 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
105 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
106 SmallVectorImpl<MCFixup> &Fixups) const;
108 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
109 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
113 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups) const;
116 /// getCCOutOpValue - Return encoding of the 's' bit.
117 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
118 SmallVectorImpl<MCFixup> &Fixups) const {
119 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
121 return MI.getOperand(Op).getReg() == ARM::CPSR;
124 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
125 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
126 SmallVectorImpl<MCFixup> &Fixups) const {
127 unsigned SoImm = MI.getOperand(Op).getImm();
128 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
129 assert(SoImmVal != -1 && "Not a valid so_imm value!");
131 // Encode rotate_imm.
132 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
133 << ARMII::SoRotImmShift;
136 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
140 /// getSORegOpValue - Return an encoded so_reg shifted register value.
141 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
142 SmallVectorImpl<MCFixup> &Fixups) const;
144 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
145 SmallVectorImpl<MCFixup> &Fixups) const {
146 switch (MI.getOperand(Op).getImm()) {
147 default: assert (0 && "Not a valid rot_imm value!");
155 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
156 SmallVectorImpl<MCFixup> &Fixups) const {
157 return MI.getOperand(Op).getImm() - 1;
160 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
161 SmallVectorImpl<MCFixup> &Fixups) const {
162 return 64 - MI.getOperand(Op).getImm();
165 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
169 SmallVectorImpl<MCFixup> &Fixups) const;
170 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
171 SmallVectorImpl<MCFixup> &Fixups) const;
172 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
173 SmallVectorImpl<MCFixup> &Fixups) const;
175 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
176 unsigned EncodedValue) const;
177 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
178 unsigned EncodedValue) const;
180 void EmitByte(unsigned char C, raw_ostream &OS) const {
184 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
185 // Output the constant in little endian byte order.
186 for (unsigned i = 0; i != Size; ++i) {
187 EmitByte(Val & 255, OS);
192 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
193 SmallVectorImpl<MCFixup> &Fixups) const;
196 } // end anonymous namespace
198 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
200 return new ARMMCCodeEmitter(TM, Ctx);
203 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
204 /// instructions, and rewrite them to their Thumb2 form if we are currently in
206 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
207 unsigned EncodedValue) const {
208 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
209 if (Subtarget.isThumb2()) {
210 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
211 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
213 unsigned Bit24 = EncodedValue & 0x01000000;
214 unsigned Bit28 = Bit24 << 4;
215 EncodedValue &= 0xEFFFFFFF;
216 EncodedValue |= Bit28;
217 EncodedValue |= 0x0F000000;
223 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
224 /// instructions, and rewrite them to their Thumb2 form if we are currently in
226 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
227 unsigned EncodedValue) const {
228 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
229 if (Subtarget.isThumb2()) {
230 EncodedValue &= 0xF0FFFFFF;
231 EncodedValue |= 0x09000000;
238 /// getMachineOpValue - Return binary encoding of operand. If the machine
239 /// operand requires relocation, record the relocation and return zero.
240 unsigned ARMMCCodeEmitter::
241 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
242 SmallVectorImpl<MCFixup> &Fixups) const {
244 unsigned Reg = MO.getReg();
245 unsigned RegNo = getARMRegisterNumbering(Reg);
247 // Q registers are encodes as 2x their register number.
251 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
252 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
253 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
254 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
257 } else if (MO.isImm()) {
258 return static_cast<unsigned>(MO.getImm());
259 } else if (MO.isFPImm()) {
260 return static_cast<unsigned>(APFloat(MO.getFPImm())
261 .bitcastToAPInt().getHiBits(32).getLimitedValue());
271 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
272 bool ARMMCCodeEmitter::
273 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
274 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
275 const MCOperand &MO = MI.getOperand(OpIdx);
276 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
278 Reg = getARMRegisterNumbering(MO.getReg());
280 int32_t SImm = MO1.getImm();
283 // Special value for #-0
284 if (SImm == INT32_MIN)
287 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
297 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
299 uint32_t ARMMCCodeEmitter::
300 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
301 SmallVectorImpl<MCFixup> &Fixups) const {
302 const MCOperand &MO = MI.getOperand(OpIdx);
304 // If the destination is an immediate, we have nothing to do.
305 if (MO.isImm()) return MO.getImm();
306 assert (MO.isExpr() && "Unexpected branch target type!");
307 const MCExpr *Expr = MO.getExpr();
308 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
309 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
311 // All of the information is in the fixup.
315 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
316 uint32_t ARMMCCodeEmitter::
317 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
318 SmallVectorImpl<MCFixup> &Fixups) const {
320 // {12} = (U)nsigned (add == '1', sub == '0')
324 // If The first operand isn't a register, we have a label reference.
325 const MCOperand &MO = MI.getOperand(OpIdx);
327 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
330 assert(MO.isExpr() && "Unexpected machine operand type!");
331 const MCExpr *Expr = MO.getExpr();
332 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
333 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
335 ++MCNumCPRelocations;
337 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
339 uint32_t Binary = Imm12 & 0xfff;
340 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
343 Binary |= (Reg << 13);
347 uint32_t ARMMCCodeEmitter::
348 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
349 SmallVectorImpl<MCFixup> &Fixups) const {
350 const MCOperand &MO = MI.getOperand(OpIdx);
351 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
352 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
353 unsigned Rn = getARMRegisterNumbering(MO.getReg());
354 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
355 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
356 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
357 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
364 default: llvm_unreachable("Unknown shift opc!");
365 case ARM_AM::no_shift:
366 assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
368 case ARM_AM::lsl: SBits = 0x0; break;
369 case ARM_AM::lsr: SBits = 0x1; break;
370 case ARM_AM::asr: SBits = 0x2; break;
371 case ARM_AM::ror: SBits = 0x3; break;
381 uint32_t Binary = Rm;
383 Binary |= SBits << 5;
384 Binary |= ShImm << 7;
390 uint32_t ARMMCCodeEmitter::
391 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
392 SmallVectorImpl<MCFixup> &Fixups) const {
393 // {9} 1 == imm8, 0 == Rm
397 const MCOperand &MO = MI.getOperand(OpIdx);
398 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
399 unsigned Imm = MO1.getImm();
400 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
401 bool isImm = MO.getReg() == 0;
402 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
403 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
405 Imm8 = getARMRegisterNumbering(MO.getReg());
406 return Imm8 | (isAdd << 8) | (isImm << 9);
409 uint32_t ARMMCCodeEmitter::
410 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
411 SmallVectorImpl<MCFixup> &Fixups) const {
412 // {13} 1 == imm8, 0 == Rm
417 const MCOperand &MO = MI.getOperand(OpIdx);
418 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
419 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
420 unsigned Rn = getARMRegisterNumbering(MO.getReg());
421 unsigned Imm = MO2.getImm();
422 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
423 bool isImm = MO1.getReg() == 0;
424 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
425 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
427 Imm8 = getARMRegisterNumbering(MO1.getReg());
428 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
431 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
432 uint32_t ARMMCCodeEmitter::
433 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
434 SmallVectorImpl<MCFixup> &Fixups) const {
436 // {8} = (U)nsigned (add == '1', sub == '0')
439 // If The first operand isn't a register, we have a label reference.
440 const MCOperand &MO = MI.getOperand(OpIdx);
442 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
445 assert(MO.isExpr() && "Unexpected machine operand type!");
446 const MCExpr *Expr = MO.getExpr();
447 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
448 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
450 ++MCNumCPRelocations;
452 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
454 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
455 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
456 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
458 Binary |= (Reg << 9);
462 unsigned ARMMCCodeEmitter::
463 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
464 SmallVectorImpl<MCFixup> &Fixups) const {
465 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
466 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
467 // case the imm contains the amount to shift by.
470 // {4} = 1 if reg shift, 0 if imm shift
478 const MCOperand &MO = MI.getOperand(OpIdx);
479 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
480 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
481 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
484 unsigned Binary = getARMRegisterNumbering(MO.getReg());
486 // Encode the shift opcode.
488 unsigned Rs = MO1.getReg();
490 // Set shift operand (bit[7:4]).
495 // RRX - 0110 and bit[11:8] clear.
497 default: llvm_unreachable("Unknown shift opc!");
498 case ARM_AM::lsl: SBits = 0x1; break;
499 case ARM_AM::lsr: SBits = 0x3; break;
500 case ARM_AM::asr: SBits = 0x5; break;
501 case ARM_AM::ror: SBits = 0x7; break;
502 case ARM_AM::rrx: SBits = 0x6; break;
505 // Set shift operand (bit[6:4]).
511 default: llvm_unreachable("Unknown shift opc!");
512 case ARM_AM::lsl: SBits = 0x0; break;
513 case ARM_AM::lsr: SBits = 0x2; break;
514 case ARM_AM::asr: SBits = 0x4; break;
515 case ARM_AM::ror: SBits = 0x6; break;
519 Binary |= SBits << 4;
520 if (SOpc == ARM_AM::rrx)
523 // Encode the shift operation Rs or shift_imm (except rrx).
525 // Encode Rs bit[11:8].
526 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
527 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
530 // Encode shift_imm bit[11:7].
531 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
534 unsigned ARMMCCodeEmitter::
535 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
536 SmallVectorImpl<MCFixup> &Fixups) const {
537 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
539 const MCOperand &MO = MI.getOperand(Op);
540 uint32_t v = ~MO.getImm();
541 uint32_t lsb = CountTrailingZeros_32(v);
542 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
543 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
544 return lsb | (msb << 5);
547 unsigned ARMMCCodeEmitter::
548 getRegisterListOpValue(const MCInst &MI, unsigned Op,
549 SmallVectorImpl<MCFixup> &Fixups) const {
550 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
551 // register in the list, set the corresponding bit.
553 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
554 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
555 Binary |= 1 << regno;
560 unsigned ARMMCCodeEmitter::
561 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
562 SmallVectorImpl<MCFixup> &Fixups) const {
563 const MCOperand &Reg = MI.getOperand(Op);
564 const MCOperand &Imm = MI.getOperand(Op + 1);
566 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
569 switch (Imm.getImm()) {
573 case 8: Align = 0x01; break;
574 case 16: Align = 0x02; break;
575 case 32: Align = 0x03; break;
578 return RegNo | (Align << 4);
581 unsigned ARMMCCodeEmitter::
582 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
583 SmallVectorImpl<MCFixup> &Fixups) const {
584 const MCOperand &MO = MI.getOperand(Op);
585 if (MO.getReg() == 0) return 0x0D;
589 void ARMMCCodeEmitter::
590 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
591 SmallVectorImpl<MCFixup> &Fixups) const {
592 // Pseudo instructions don't get encoded.
593 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
594 if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
597 EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
598 ++MCNumEmitted; // Keep track of the # of mi's emitted.
601 #include "ARMGenMCCodeEmitter.inc"