1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class ARMMCCodeEmitter : public MCCodeEmitter {
29 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
32 const TargetInstrInfo &TII;
36 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
37 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
40 ~ARMMCCodeEmitter() {}
42 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
44 // getBinaryCodeForInstr - TableGen'erated function for getting the
45 // binary encoding for an instruction.
46 unsigned getBinaryCodeForInstr(const MCInst &MI) const;
48 /// getMachineOpValue - Return binary encoding of operand. If the machine
49 /// operand requires relocation, record the relocation and return zero.
50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
52 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
54 unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const;
56 /// getCCOutOpValue - Return encoding of the 's' bit.
57 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
58 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
60 return MI.getOperand(Op).getReg() == ARM::CPSR;
63 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
64 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const {
65 unsigned SoImm = MI.getOperand(Op).getImm();
66 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
67 assert(SoImmVal != -1 && "Not a valid so_imm value!");
70 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
71 << ARMII::SoRotImmShift;
74 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
78 /// getSORegOpValue - Return an encoded so_reg shifted register value.
79 unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const;
81 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const {
82 switch (MI.getOperand(Op).getImm()) {
83 default: assert (0 && "Not a valid rot_imm value!");
91 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
92 return MI.getOperand(Op).getImm() - 1;
95 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op) const {
96 return 64 - MI.getOperand(Op).getImm();
99 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
101 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
102 unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const;
103 unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const;
105 unsigned getNumFixupKinds() const {
106 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
110 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
111 static MCFixupKindInfo rtn;
112 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
116 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
121 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
122 raw_ostream &OS) const {
123 // Output the constant in little endian byte order.
124 for (unsigned i = 0; i != Size; ++i) {
125 EmitByte(Val & 255, CurByte, OS);
130 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
131 SmallVectorImpl<MCFixup> &Fixups) const;
134 } // end anonymous namespace
136 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
139 return new ARMMCCodeEmitter(TM, Ctx);
142 /// getMachineOpValue - Return binary encoding of operand. If the machine
143 /// operand requires relocation, record the relocation and return zero.
144 unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
145 const MCOperand &MO) const {
147 unsigned regno = getARMRegisterNumbering(MO.getReg());
149 // Q registers are encodes as 2x their register number.
150 switch (MO.getReg()) {
151 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
152 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
153 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
154 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
159 } else if (MO.isImm()) {
160 return static_cast<unsigned>(MO.getImm());
161 } else if (MO.isFPImm()) {
162 return static_cast<unsigned>(APFloat(MO.getFPImm())
163 .bitcastToAPInt().getHiBits(32).getLimitedValue());
173 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
175 unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI,
176 unsigned OpIdx) const {
178 // {12} = (U)nsigned (add == '1', sub == '0')
180 const MCOperand &MO = MI.getOperand(OpIdx);
181 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
184 // If The first operand isn't a register, we have a label reference.
186 Binary |= ARM::PC << 13; // Rn is PC.
187 // FIXME: Add a fixup referencing the label.
191 unsigned Reg = getARMRegisterNumbering(MO.getReg());
192 int32_t Imm12 = MO1.getImm();
193 bool isAdd = Imm12 >= 0;
194 // Special value for #-0
195 if (Imm12 == INT32_MIN)
197 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
200 Binary = Imm12 & 0xfff;
203 Binary |= (Reg << 13);
207 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
208 unsigned OpIdx) const {
209 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg
210 // to be shifted. The second is either Rs, the amount to shift by, or
211 // reg0 in which case the imm contains the amount to shift by.
213 // {4} = 1 if reg shift, 0 if imm shift
221 const MCOperand &MO = MI.getOperand(OpIdx);
222 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
223 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
224 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
227 unsigned Binary = getARMRegisterNumbering(MO.getReg());
229 // Encode the shift opcode.
231 unsigned Rs = MO1.getReg();
233 // Set shift operand (bit[7:4]).
238 // RRX - 0110 and bit[11:8] clear.
240 default: llvm_unreachable("Unknown shift opc!");
241 case ARM_AM::lsl: SBits = 0x1; break;
242 case ARM_AM::lsr: SBits = 0x3; break;
243 case ARM_AM::asr: SBits = 0x5; break;
244 case ARM_AM::ror: SBits = 0x7; break;
245 case ARM_AM::rrx: SBits = 0x6; break;
248 // Set shift operand (bit[6:4]).
254 default: llvm_unreachable("Unknown shift opc!");
255 case ARM_AM::lsl: SBits = 0x0; break;
256 case ARM_AM::lsr: SBits = 0x2; break;
257 case ARM_AM::asr: SBits = 0x4; break;
258 case ARM_AM::ror: SBits = 0x6; break;
261 Binary |= SBits << 4;
262 if (SOpc == ARM_AM::rrx)
265 // Encode the shift operation Rs or shift_imm (except rrx).
267 // Encode Rs bit[11:8].
268 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
269 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
272 // Encode shift_imm bit[11:7].
273 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
276 unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
278 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
280 const MCOperand &MO = MI.getOperand(Op);
281 uint32_t v = ~MO.getImm();
282 uint32_t lsb = CountTrailingZeros_32(v);
283 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
284 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
285 return lsb | (msb << 5);
288 unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
290 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
291 // register in the list, set the corresponding bit.
293 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
294 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
295 Binary |= 1 << regno;
300 unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
302 const MCOperand &Reg = MI.getOperand(Op);
303 const MCOperand &Imm = MI.getOperand(Op+1);
305 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
306 unsigned Align = Imm.getImm();
308 case 2: case 4: case 8: Align = 0x01; break;
309 case 16: Align = 0x02; break;
310 case 32: Align = 0x03; break;
311 default: Align = 0x00; break;
313 return RegNo | (Align << 4);
316 unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI,
318 const MCOperand ®no = MI.getOperand(Op);
319 if (regno.getReg() == 0) return 0x0D;
320 return regno.getReg();
324 void ARMMCCodeEmitter::
325 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
326 SmallVectorImpl<MCFixup> &Fixups) const {
327 unsigned Opcode = MI.getOpcode();
328 const TargetInstrDesc &Desc = TII.get(Opcode);
329 uint64_t TSFlags = Desc.TSFlags;
330 // Keep track of the current byte being emitted.
331 unsigned CurByte = 0;
333 // Pseudo instructions don't get encoded.
334 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
337 ++MCNumEmitted; // Keep track of the # of mi's emitted
338 unsigned Value = getBinaryCodeForInstr(MI);
342 EmitConstant(Value, 4, CurByte, OS);
345 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
346 // be able to generate code emitter helpers for either variant, like it
347 // does for the AsmWriter.
348 #define ARMCodeEmitter ARMMCCodeEmitter
349 #define MachineInstr MCInst
350 #include "ARMGenCodeEmitter.inc"
351 #undef ARMCodeEmitter