1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // This table *must* be in the order that the fixup_* kinds are defined in
51 // Name Offset (bits) Size (bits) Flags
52 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
54 MCFixupKindInfo::FKF_IsAligned},
55 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
56 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
57 MCFixupKindInfo::FKF_IsPCRel },
58 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
59 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
60 { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
61 MCFixupKindInfo::FKF_IsAligned},
62 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
63 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_movt_hi16", 0, 16, 0 },
69 { "fixup_arm_movw_lo16", 0, 16, 0 },
72 if (Kind < FirstTargetFixupKind)
73 return MCCodeEmitter::getFixupKindInfo(Kind);
75 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
77 return Infos[Kind - FirstTargetFixupKind];
79 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
81 // getBinaryCodeForInstr - TableGen'erated function for getting the
82 // binary encoding for an instruction.
83 unsigned getBinaryCodeForInstr(const MCInst &MI,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getMachineOpValue - Return binary encoding of operand. If the machine
87 /// operand requires relocation, record the relocation and return zero.
88 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
92 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
96 unsigned &Reg, unsigned &Imm,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
100 /// BL branch target.
101 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups) const;
104 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
105 /// BLX branch target.
106 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
110 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
114 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
118 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 SmallVectorImpl<MCFixup> &Fixups) const;
121 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
123 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
124 SmallVectorImpl<MCFixup> &Fixups) const;
126 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
127 /// ADR label target.
128 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
133 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
134 SmallVectorImpl<MCFixup> &Fixups) const;
136 /// getTAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
137 uint32_t getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups) const;
140 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
142 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups) const;
146 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
147 /// operand as needed by load/store instructions.
148 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
149 SmallVectorImpl<MCFixup> &Fixups) const;
151 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
152 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups) const {
154 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
156 default: assert(0 && "Unknown addressing sub-mode!");
157 case ARM_AM::da: return 0;
158 case ARM_AM::ia: return 1;
159 case ARM_AM::db: return 2;
160 case ARM_AM::ib: return 3;
163 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
165 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
167 default: llvm_unreachable("Unknown shift opc!");
168 case ARM_AM::no_shift:
169 case ARM_AM::lsl: return 0;
170 case ARM_AM::lsr: return 1;
171 case ARM_AM::asr: return 2;
173 case ARM_AM::rrx: return 3;
178 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
179 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups) const;
182 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
183 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
184 SmallVectorImpl<MCFixup> &Fixups) const;
186 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
187 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
188 SmallVectorImpl<MCFixup> &Fixups) const;
190 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
191 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
192 SmallVectorImpl<MCFixup> &Fixups) const;
194 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
196 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
197 SmallVectorImpl<MCFixup> &Fixups) const;
199 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
200 uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &) const;
203 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
204 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
205 SmallVectorImpl<MCFixup> &Fixups) const;
207 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
208 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
209 SmallVectorImpl<MCFixup> &Fixups) const;
211 /// getCCOutOpValue - Return encoding of the 's' bit.
212 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
213 SmallVectorImpl<MCFixup> &Fixups) const {
214 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
216 return MI.getOperand(Op).getReg() == ARM::CPSR;
219 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
220 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
221 SmallVectorImpl<MCFixup> &Fixups) const {
222 unsigned SoImm = MI.getOperand(Op).getImm();
223 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
224 assert(SoImmVal != -1 && "Not a valid so_imm value!");
226 // Encode rotate_imm.
227 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
228 << ARMII::SoRotImmShift;
231 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
235 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
236 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
237 SmallVectorImpl<MCFixup> &Fixups) const {
238 unsigned SoImm = MI.getOperand(Op).getImm();
239 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
240 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
244 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
245 SmallVectorImpl<MCFixup> &Fixups) const;
246 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
247 SmallVectorImpl<MCFixup> &Fixups) const;
248 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
249 SmallVectorImpl<MCFixup> &Fixups) const;
250 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
251 SmallVectorImpl<MCFixup> &Fixups) const;
253 /// getSORegOpValue - Return an encoded so_reg shifted register value.
254 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
255 SmallVectorImpl<MCFixup> &Fixups) const;
256 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const;
259 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
260 SmallVectorImpl<MCFixup> &Fixups) const {
261 switch (MI.getOperand(Op).getImm()) {
262 default: assert (0 && "Not a valid rot_imm value!");
270 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
271 SmallVectorImpl<MCFixup> &Fixups) const {
272 return MI.getOperand(Op).getImm() - 1;
275 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const {
277 return 64 - MI.getOperand(Op).getImm();
280 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
281 SmallVectorImpl<MCFixup> &Fixups) const;
283 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
284 SmallVectorImpl<MCFixup> &Fixups) const;
285 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
286 SmallVectorImpl<MCFixup> &Fixups) const;
287 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
288 SmallVectorImpl<MCFixup> &Fixups) const;
289 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
290 SmallVectorImpl<MCFixup> &Fixups) const;
292 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
293 unsigned EncodedValue) const;
294 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
295 unsigned EncodedValue) const;
296 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
297 unsigned EncodedValue) const;
299 unsigned VFPThumb2PostEncoder(const MCInst &MI,
300 unsigned EncodedValue) const;
302 void EmitByte(unsigned char C, raw_ostream &OS) const {
306 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
307 // Output the constant in little endian byte order.
308 for (unsigned i = 0; i != Size; ++i) {
309 EmitByte(Val & 255, OS);
314 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
315 SmallVectorImpl<MCFixup> &Fixups) const;
318 } // end anonymous namespace
320 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
322 return new ARMMCCodeEmitter(TM, Ctx);
325 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
326 /// instructions, and rewrite them to their Thumb2 form if we are currently in
328 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
329 unsigned EncodedValue) const {
330 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
331 if (Subtarget.isThumb2()) {
332 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
333 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
335 unsigned Bit24 = EncodedValue & 0x01000000;
336 unsigned Bit28 = Bit24 << 4;
337 EncodedValue &= 0xEFFFFFFF;
338 EncodedValue |= Bit28;
339 EncodedValue |= 0x0F000000;
345 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
346 /// instructions, and rewrite them to their Thumb2 form if we are currently in
348 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
349 unsigned EncodedValue) const {
350 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
351 if (Subtarget.isThumb2()) {
352 EncodedValue &= 0xF0FFFFFF;
353 EncodedValue |= 0x09000000;
359 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
360 /// instructions, and rewrite them to their Thumb2 form if we are currently in
362 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
363 unsigned EncodedValue) const {
364 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
365 if (Subtarget.isThumb2()) {
366 EncodedValue &= 0x00FFFFFF;
367 EncodedValue |= 0xEE000000;
373 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
374 /// them to their Thumb2 form if we are currently in Thumb2 mode.
375 unsigned ARMMCCodeEmitter::
376 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
377 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
378 EncodedValue &= 0x0FFFFFFF;
379 EncodedValue |= 0xE0000000;
384 /// getMachineOpValue - Return binary encoding of operand. If the machine
385 /// operand requires relocation, record the relocation and return zero.
386 unsigned ARMMCCodeEmitter::
387 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
388 SmallVectorImpl<MCFixup> &Fixups) const {
390 unsigned Reg = MO.getReg();
391 unsigned RegNo = getARMRegisterNumbering(Reg);
393 // Q registers are encoded as 2x their register number.
397 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
398 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
399 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
400 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
403 } else if (MO.isImm()) {
404 return static_cast<unsigned>(MO.getImm());
405 } else if (MO.isFPImm()) {
406 return static_cast<unsigned>(APFloat(MO.getFPImm())
407 .bitcastToAPInt().getHiBits(32).getLimitedValue());
410 llvm_unreachable("Unable to encode MCOperand!");
414 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
415 bool ARMMCCodeEmitter::
416 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
417 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
418 const MCOperand &MO = MI.getOperand(OpIdx);
419 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
421 Reg = getARMRegisterNumbering(MO.getReg());
423 int32_t SImm = MO1.getImm();
426 // Special value for #-0
427 if (SImm == INT32_MIN)
430 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
440 /// getBranchTargetOpValue - Helper function to get the branch target operand,
441 /// which is either an immediate or requires a fixup.
442 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
444 SmallVectorImpl<MCFixup> &Fixups) {
445 const MCOperand &MO = MI.getOperand(OpIdx);
447 // If the destination is an immediate, we have nothing to do.
448 if (MO.isImm()) return MO.getImm();
449 assert(MO.isExpr() && "Unexpected branch target type!");
450 const MCExpr *Expr = MO.getExpr();
451 MCFixupKind Kind = MCFixupKind(FixupKind);
452 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
454 // All of the information is in the fixup.
458 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
459 uint32_t ARMMCCodeEmitter::
460 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
461 SmallVectorImpl<MCFixup> &Fixups) const {
462 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
465 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
466 /// BLX branch target.
467 uint32_t ARMMCCodeEmitter::
468 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
469 SmallVectorImpl<MCFixup> &Fixups) const {
470 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
473 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
474 uint32_t ARMMCCodeEmitter::
475 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
476 SmallVectorImpl<MCFixup> &Fixups) const {
477 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
480 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
481 uint32_t ARMMCCodeEmitter::
482 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
483 SmallVectorImpl<MCFixup> &Fixups) const {
484 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
487 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
488 uint32_t ARMMCCodeEmitter::
489 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
490 SmallVectorImpl<MCFixup> &Fixups) const {
491 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
494 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
496 uint32_t ARMMCCodeEmitter::
497 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
498 SmallVectorImpl<MCFixup> &Fixups) const {
499 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
500 if (Subtarget.isThumb2())
501 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_branch, Fixups);
502 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
505 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
507 uint32_t ARMMCCodeEmitter::
508 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
509 SmallVectorImpl<MCFixup> &Fixups) const {
510 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
511 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
515 /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
516 uint32_t ARMMCCodeEmitter::
517 getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
518 SmallVectorImpl<MCFixup> &Fixups) const {
519 const MCOperand &MO1 = MI.getOperand(OpIdx);
520 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
521 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
522 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
523 return (Rm << 3) | Rn;
526 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
527 uint32_t ARMMCCodeEmitter::
528 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
529 SmallVectorImpl<MCFixup> &Fixups) const {
531 // {12} = (U)nsigned (add == '1', sub == '0')
535 // If The first operand isn't a register, we have a label reference.
536 const MCOperand &MO = MI.getOperand(OpIdx);
537 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
538 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
539 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
541 isAdd = false ; // 'U' bit is set as part of the fixup.
543 const MCExpr *Expr = 0;
547 Expr = MO2.getExpr();
549 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
551 if (Subtarget.isThumb2())
552 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
554 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
555 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
557 ++MCNumCPRelocations;
559 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
561 uint32_t Binary = Imm12 & 0xfff;
562 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
565 Binary |= (Reg << 13);
569 /// getT2AddrModeImm8s4OpValue - Return encoding info for
570 /// 'reg +/- imm8<<2' operand.
571 uint32_t ARMMCCodeEmitter::
572 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
573 SmallVectorImpl<MCFixup> &Fixups) const {
575 // {8} = (U)nsigned (add == '1', sub == '0')
579 // If The first operand isn't a register, we have a label reference.
580 const MCOperand &MO = MI.getOperand(OpIdx);
582 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
584 isAdd = false ; // 'U' bit is set as part of the fixup.
586 assert(MO.isExpr() && "Unexpected machine operand type!");
587 const MCExpr *Expr = MO.getExpr();
588 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
589 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
591 ++MCNumCPRelocations;
593 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
595 uint32_t Binary = (Imm8 >> 2) & 0xff;
596 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
599 Binary |= (Reg << 9);
603 uint32_t ARMMCCodeEmitter::
604 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
605 SmallVectorImpl<MCFixup> &Fixups) const {
606 // {20-16} = imm{15-12}
607 // {11-0} = imm{11-0}
608 const MCOperand &MO = MI.getOperand(OpIdx);
610 return static_cast<unsigned>(MO.getImm());
611 } else if (const MCSymbolRefExpr *Expr =
612 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
614 switch (Expr->getKind()) {
615 default: assert(0 && "Unsupported ARMFixup");
616 case MCSymbolRefExpr::VK_ARM_HI16:
617 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
619 case MCSymbolRefExpr::VK_ARM_LO16:
620 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
623 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
626 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
630 uint32_t ARMMCCodeEmitter::
631 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
632 SmallVectorImpl<MCFixup> &Fixups) const {
633 const MCOperand &MO = MI.getOperand(OpIdx);
634 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
635 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
636 unsigned Rn = getARMRegisterNumbering(MO.getReg());
637 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
638 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
639 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
640 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
641 unsigned SBits = getShiftOp(ShOp);
650 uint32_t Binary = Rm;
652 Binary |= SBits << 5;
653 Binary |= ShImm << 7;
659 uint32_t ARMMCCodeEmitter::
660 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
661 SmallVectorImpl<MCFixup> &Fixups) const {
663 // {13} 1 == imm12, 0 == Rm
666 const MCOperand &MO = MI.getOperand(OpIdx);
667 unsigned Rn = getARMRegisterNumbering(MO.getReg());
668 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
673 uint32_t ARMMCCodeEmitter::
674 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
675 SmallVectorImpl<MCFixup> &Fixups) const {
676 // {13} 1 == imm12, 0 == Rm
679 const MCOperand &MO = MI.getOperand(OpIdx);
680 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
681 unsigned Imm = MO1.getImm();
682 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
683 bool isReg = MO.getReg() != 0;
684 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
685 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
687 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
688 Binary <<= 7; // Shift amount is bits [11:7]
689 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
690 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
692 return Binary | (isAdd << 12) | (isReg << 13);
695 uint32_t ARMMCCodeEmitter::
696 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
697 SmallVectorImpl<MCFixup> &Fixups) const {
698 // {9} 1 == imm8, 0 == Rm
702 const MCOperand &MO = MI.getOperand(OpIdx);
703 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
704 unsigned Imm = MO1.getImm();
705 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
706 bool isImm = MO.getReg() == 0;
707 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
708 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
710 Imm8 = getARMRegisterNumbering(MO.getReg());
711 return Imm8 | (isAdd << 8) | (isImm << 9);
714 uint32_t ARMMCCodeEmitter::
715 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
716 SmallVectorImpl<MCFixup> &Fixups) const {
717 // {13} 1 == imm8, 0 == Rm
722 const MCOperand &MO = MI.getOperand(OpIdx);
723 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
724 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
725 unsigned Rn = getARMRegisterNumbering(MO.getReg());
726 unsigned Imm = MO2.getImm();
727 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
728 bool isImm = MO1.getReg() == 0;
729 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
730 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
732 Imm8 = getARMRegisterNumbering(MO1.getReg());
733 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
736 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
737 uint32_t ARMMCCodeEmitter::
738 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
739 SmallVectorImpl<MCFixup> &Fixups) const {
742 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
743 #if 0 // FIXME: This crashes2003-05-14-initialize-string.c
744 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
745 "Unexpected base register!");
747 // The immediate is already shifted for the implicit zeroes, so no change
749 return MO1.getImm() & 0xff;
752 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
753 uint32_t ARMMCCodeEmitter::
754 getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
755 SmallVectorImpl<MCFixup> &) const {
763 const MCOperand &MO = MI.getOperand(OpIdx);
764 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
765 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
766 unsigned Rn = getARMRegisterNumbering(MO.getReg());
767 unsigned Imm5 = MO1.getImm();
769 if (MO2.getReg() != 0)
771 Imm5 = getARMRegisterNumbering(MO2.getReg());
773 return ((Imm5 & 0x1f) << 3) | Rn;
776 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
777 uint32_t ARMMCCodeEmitter::
778 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
779 SmallVectorImpl<MCFixup> &Fixups) const {
780 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
783 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
784 uint32_t ARMMCCodeEmitter::
785 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
786 SmallVectorImpl<MCFixup> &Fixups) const {
788 // {8} = (U)nsigned (add == '1', sub == '0')
792 // If The first operand isn't a register, we have a label reference.
793 const MCOperand &MO = MI.getOperand(OpIdx);
795 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
797 isAdd = false; // 'U' bit is handled as part of the fixup.
799 assert(MO.isExpr() && "Unexpected machine operand type!");
800 const MCExpr *Expr = MO.getExpr();
802 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
803 if (Subtarget.isThumb2())
804 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
806 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
807 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
809 ++MCNumCPRelocations;
811 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
812 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
815 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
816 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
819 Binary |= (Reg << 9);
823 unsigned ARMMCCodeEmitter::
824 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
825 SmallVectorImpl<MCFixup> &Fixups) const {
826 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
827 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
828 // case the imm contains the amount to shift by.
831 // {4} = 1 if reg shift, 0 if imm shift
839 const MCOperand &MO = MI.getOperand(OpIdx);
840 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
841 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
842 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
845 unsigned Binary = getARMRegisterNumbering(MO.getReg());
847 // Encode the shift opcode.
849 unsigned Rs = MO1.getReg();
851 // Set shift operand (bit[7:4]).
856 // RRX - 0110 and bit[11:8] clear.
858 default: llvm_unreachable("Unknown shift opc!");
859 case ARM_AM::lsl: SBits = 0x1; break;
860 case ARM_AM::lsr: SBits = 0x3; break;
861 case ARM_AM::asr: SBits = 0x5; break;
862 case ARM_AM::ror: SBits = 0x7; break;
863 case ARM_AM::rrx: SBits = 0x6; break;
866 // Set shift operand (bit[6:4]).
872 default: llvm_unreachable("Unknown shift opc!");
873 case ARM_AM::lsl: SBits = 0x0; break;
874 case ARM_AM::lsr: SBits = 0x2; break;
875 case ARM_AM::asr: SBits = 0x4; break;
876 case ARM_AM::ror: SBits = 0x6; break;
880 Binary |= SBits << 4;
881 if (SOpc == ARM_AM::rrx)
884 // Encode the shift operation Rs or shift_imm (except rrx).
886 // Encode Rs bit[11:8].
887 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
888 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
891 // Encode shift_imm bit[11:7].
892 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
895 unsigned ARMMCCodeEmitter::
896 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
897 SmallVectorImpl<MCFixup> &Fixups) const {
898 const MCOperand &MO1 = MI.getOperand(OpNum);
899 const MCOperand &MO2 = MI.getOperand(OpNum+1);
900 const MCOperand &MO3 = MI.getOperand(OpNum+2);
902 // Encoded as [Rn, Rm, imm].
903 // FIXME: Needs fixup support.
904 unsigned Value = getARMRegisterNumbering(MO1.getReg());
906 Value |= getARMRegisterNumbering(MO2.getReg());
908 Value |= MO3.getImm();
913 unsigned ARMMCCodeEmitter::
914 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
915 SmallVectorImpl<MCFixup> &Fixups) const {
916 const MCOperand &MO1 = MI.getOperand(OpNum);
917 const MCOperand &MO2 = MI.getOperand(OpNum+1);
919 // FIXME: Needs fixup support.
920 unsigned Value = getARMRegisterNumbering(MO1.getReg());
922 // Even though the immediate is 8 bits long, we need 9 bits in order
923 // to represent the (inverse of the) sign bit.
925 int32_t tmp = (int32_t)MO2.getImm();
929 Value |= 256; // Set the ADD bit
934 unsigned ARMMCCodeEmitter::
935 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
936 SmallVectorImpl<MCFixup> &Fixups) const {
937 const MCOperand &MO1 = MI.getOperand(OpNum);
939 // FIXME: Needs fixup support.
941 int32_t tmp = (int32_t)MO1.getImm();
945 Value |= 256; // Set the ADD bit
950 unsigned ARMMCCodeEmitter::
951 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
952 SmallVectorImpl<MCFixup> &Fixups) const {
953 const MCOperand &MO1 = MI.getOperand(OpNum);
955 // FIXME: Needs fixup support.
957 int32_t tmp = (int32_t)MO1.getImm();
961 Value |= 4096; // Set the ADD bit
966 unsigned ARMMCCodeEmitter::
967 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
968 SmallVectorImpl<MCFixup> &Fixups) const {
969 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
970 // shifted. The second is the amount to shift by.
977 const MCOperand &MO = MI.getOperand(OpIdx);
978 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
979 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
982 unsigned Binary = getARMRegisterNumbering(MO.getReg());
984 // Encode the shift opcode.
986 // Set shift operand (bit[6:4]).
992 default: llvm_unreachable("Unknown shift opc!");
993 case ARM_AM::lsl: SBits = 0x0; break;
994 case ARM_AM::lsr: SBits = 0x2; break;
995 case ARM_AM::asr: SBits = 0x4; break;
996 case ARM_AM::ror: SBits = 0x6; break;
999 Binary |= SBits << 4;
1000 if (SOpc == ARM_AM::rrx)
1003 // Encode shift_imm bit[11:7].
1004 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1007 unsigned ARMMCCodeEmitter::
1008 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1009 SmallVectorImpl<MCFixup> &Fixups) const {
1010 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1012 const MCOperand &MO = MI.getOperand(Op);
1013 uint32_t v = ~MO.getImm();
1014 uint32_t lsb = CountTrailingZeros_32(v);
1015 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1016 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1017 return lsb | (msb << 5);
1020 unsigned ARMMCCodeEmitter::
1021 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1022 SmallVectorImpl<MCFixup> &Fixups) const {
1025 // {7-0} = Number of registers
1028 // {15-0} = Bitfield of GPRs.
1029 unsigned Reg = MI.getOperand(Op).getReg();
1030 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1031 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1033 unsigned Binary = 0;
1035 if (SPRRegs || DPRRegs) {
1037 unsigned RegNo = getARMRegisterNumbering(Reg);
1038 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1039 Binary |= (RegNo & 0x1f) << 8;
1043 Binary |= NumRegs * 2;
1045 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1046 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1047 Binary |= 1 << RegNo;
1054 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1055 /// with the alignment operand.
1056 unsigned ARMMCCodeEmitter::
1057 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1058 SmallVectorImpl<MCFixup> &Fixups) const {
1059 const MCOperand &Reg = MI.getOperand(Op);
1060 const MCOperand &Imm = MI.getOperand(Op + 1);
1062 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1065 switch (Imm.getImm()) {
1069 case 8: Align = 0x01; break;
1070 case 16: Align = 0x02; break;
1071 case 32: Align = 0x03; break;
1074 return RegNo | (Align << 4);
1077 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1078 /// alignment operand for use in VLD-dup instructions. This is the same as
1079 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1080 /// different for VLD4-dup.
1081 unsigned ARMMCCodeEmitter::
1082 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1083 SmallVectorImpl<MCFixup> &Fixups) const {
1084 const MCOperand &Reg = MI.getOperand(Op);
1085 const MCOperand &Imm = MI.getOperand(Op + 1);
1087 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1090 switch (Imm.getImm()) {
1094 case 8: Align = 0x01; break;
1095 case 16: Align = 0x03; break;
1098 return RegNo | (Align << 4);
1101 unsigned ARMMCCodeEmitter::
1102 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1103 SmallVectorImpl<MCFixup> &Fixups) const {
1104 const MCOperand &MO = MI.getOperand(Op);
1105 if (MO.getReg() == 0) return 0x0D;
1109 void ARMMCCodeEmitter::
1110 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1111 SmallVectorImpl<MCFixup> &Fixups) const {
1112 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1113 // Pseudo instructions don't get encoded.
1114 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1115 uint64_t TSFlags = Desc.TSFlags;
1116 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1119 // Basic size info comes from the TSFlags field.
1120 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1121 default: llvm_unreachable("Unexpected instruction size!");
1122 case ARMII::Size2Bytes: Size = 2; break;
1123 case ARMII::Size4Bytes: Size = 4; break;
1125 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1126 // Thumb 32-bit wide instructions need to be have the high order halfword
1128 if (Subtarget.isThumb() && Size == 4) {
1129 EmitConstant(Binary >> 16, 2, OS);
1130 EmitConstant(Binary & 0xffff, 2, OS);
1132 EmitConstant(Binary, Size, OS);
1133 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1136 #include "ARMGenMCCodeEmitter.inc"