1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
74 unsigned &Reg, unsigned &Imm,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
79 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
84 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
88 /// operand as needed by load/store instructions.
89 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
90 SmallVectorImpl<MCFixup> &Fixups) const;
92 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
93 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const {
95 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
97 default: assert(0 && "Unknown addressing sub-mode!");
98 case ARM_AM::da: return 0;
99 case ARM_AM::ia: return 1;
100 case ARM_AM::db: return 2;
101 case ARM_AM::ib: return 3;
104 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
106 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
108 default: llvm_unreachable("Unknown shift opc!");
109 case ARM_AM::no_shift:
110 case ARM_AM::lsl: return 0;
111 case ARM_AM::lsr: return 1;
112 case ARM_AM::asr: return 2;
114 case ARM_AM::rrx: return 3;
119 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
120 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
121 SmallVectorImpl<MCFixup> &Fixups) const;
123 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
124 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
128 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
132 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
136 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getCCOutOpValue - Return encoding of the 's' bit.
140 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
141 SmallVectorImpl<MCFixup> &Fixups) const {
142 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
144 return MI.getOperand(Op).getReg() == ARM::CPSR;
147 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
148 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
149 SmallVectorImpl<MCFixup> &Fixups) const {
150 unsigned SoImm = MI.getOperand(Op).getImm();
151 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
152 assert(SoImmVal != -1 && "Not a valid so_imm value!");
154 // Encode rotate_imm.
155 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
156 << ARMII::SoRotImmShift;
159 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
163 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
164 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
165 SmallVectorImpl<MCFixup> &Fixups) const {
166 unsigned SoImm = MI.getOperand(Op).getImm();
167 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
168 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
172 /// getSORegOpValue - Return an encoded so_reg shifted register value.
173 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
174 SmallVectorImpl<MCFixup> &Fixups) const;
175 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
176 SmallVectorImpl<MCFixup> &Fixups) const;
178 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
179 SmallVectorImpl<MCFixup> &Fixups) const {
180 switch (MI.getOperand(Op).getImm()) {
181 default: assert (0 && "Not a valid rot_imm value!");
189 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
190 SmallVectorImpl<MCFixup> &Fixups) const {
191 return MI.getOperand(Op).getImm() - 1;
194 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
195 SmallVectorImpl<MCFixup> &Fixups) const {
196 return 64 - MI.getOperand(Op).getImm();
199 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
200 SmallVectorImpl<MCFixup> &Fixups) const;
202 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
203 SmallVectorImpl<MCFixup> &Fixups) const;
204 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
205 SmallVectorImpl<MCFixup> &Fixups) const;
206 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
207 SmallVectorImpl<MCFixup> &Fixups) const;
209 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
210 unsigned EncodedValue) const;
211 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
212 unsigned EncodedValue) const;
213 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
214 unsigned EncodedValue) const;
216 void EmitByte(unsigned char C, raw_ostream &OS) const {
220 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
221 // Output the constant in little endian byte order.
222 for (unsigned i = 0; i != Size; ++i) {
223 EmitByte(Val & 255, OS);
228 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
229 SmallVectorImpl<MCFixup> &Fixups) const;
232 } // end anonymous namespace
234 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
236 return new ARMMCCodeEmitter(TM, Ctx);
239 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
240 /// instructions, and rewrite them to their Thumb2 form if we are currently in
242 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
243 unsigned EncodedValue) const {
244 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
245 if (Subtarget.isThumb2()) {
246 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
247 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
249 unsigned Bit24 = EncodedValue & 0x01000000;
250 unsigned Bit28 = Bit24 << 4;
251 EncodedValue &= 0xEFFFFFFF;
252 EncodedValue |= Bit28;
253 EncodedValue |= 0x0F000000;
259 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
260 /// instructions, and rewrite them to their Thumb2 form if we are currently in
262 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
263 unsigned EncodedValue) const {
264 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
265 if (Subtarget.isThumb2()) {
266 EncodedValue &= 0xF0FFFFFF;
267 EncodedValue |= 0x09000000;
273 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
274 /// instructions, and rewrite them to their Thumb2 form if we are currently in
276 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
277 unsigned EncodedValue) const {
278 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
279 if (Subtarget.isThumb2()) {
280 EncodedValue &= 0x00FFFFFF;
281 EncodedValue |= 0xEE000000;
289 /// getMachineOpValue - Return binary encoding of operand. If the machine
290 /// operand requires relocation, record the relocation and return zero.
291 unsigned ARMMCCodeEmitter::
292 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
293 SmallVectorImpl<MCFixup> &Fixups) const {
295 unsigned Reg = MO.getReg();
296 unsigned RegNo = getARMRegisterNumbering(Reg);
298 // Q registers are encodes as 2x their register number.
302 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
303 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
304 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
305 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
308 } else if (MO.isImm()) {
309 return static_cast<unsigned>(MO.getImm());
310 } else if (MO.isFPImm()) {
311 return static_cast<unsigned>(APFloat(MO.getFPImm())
312 .bitcastToAPInt().getHiBits(32).getLimitedValue());
322 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
323 bool ARMMCCodeEmitter::
324 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
325 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
326 const MCOperand &MO = MI.getOperand(OpIdx);
327 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
329 Reg = getARMRegisterNumbering(MO.getReg());
331 int32_t SImm = MO1.getImm();
334 // Special value for #-0
335 if (SImm == INT32_MIN)
338 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
348 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
350 uint32_t ARMMCCodeEmitter::
351 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
352 SmallVectorImpl<MCFixup> &Fixups) const {
353 const MCOperand &MO = MI.getOperand(OpIdx);
355 // If the destination is an immediate, we have nothing to do.
356 if (MO.isImm()) return MO.getImm();
357 assert (MO.isExpr() && "Unexpected branch target type!");
358 const MCExpr *Expr = MO.getExpr();
359 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
360 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
362 // All of the information is in the fixup.
366 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
367 uint32_t ARMMCCodeEmitter::
368 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
369 SmallVectorImpl<MCFixup> &Fixups) const {
371 // {12} = (U)nsigned (add == '1', sub == '0')
375 // If The first operand isn't a register, we have a label reference.
376 const MCOperand &MO = MI.getOperand(OpIdx);
378 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
381 assert(MO.isExpr() && "Unexpected machine operand type!");
382 const MCExpr *Expr = MO.getExpr();
383 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
384 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
386 ++MCNumCPRelocations;
388 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
390 uint32_t Binary = Imm12 & 0xfff;
391 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
394 Binary |= (Reg << 13);
398 uint32_t ARMMCCodeEmitter::
399 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
400 SmallVectorImpl<MCFixup> &Fixups) const {
401 const MCOperand &MO = MI.getOperand(OpIdx);
402 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
403 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
404 unsigned Rn = getARMRegisterNumbering(MO.getReg());
405 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
406 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
407 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
408 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
409 unsigned SBits = getShiftOp(ShOp);
418 uint32_t Binary = Rm;
420 Binary |= SBits << 5;
421 Binary |= ShImm << 7;
427 uint32_t ARMMCCodeEmitter::
428 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
429 SmallVectorImpl<MCFixup> &Fixups) const {
431 // {13} 1 == imm12, 0 == Rm
434 const MCOperand &MO = MI.getOperand(OpIdx);
435 unsigned Rn = getARMRegisterNumbering(MO.getReg());
436 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
441 uint32_t ARMMCCodeEmitter::
442 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
443 SmallVectorImpl<MCFixup> &Fixups) const {
444 // {13} 1 == imm12, 0 == Rm
447 const MCOperand &MO = MI.getOperand(OpIdx);
448 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
449 unsigned Imm = MO1.getImm();
450 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
451 bool isReg = MO.getReg() != 0;
452 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
453 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
455 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
456 Binary <<= 7; // Shift amount is bits [11:7]
457 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
458 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
460 return Binary | (isAdd << 12) | (isReg << 13);
463 uint32_t ARMMCCodeEmitter::
464 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
465 SmallVectorImpl<MCFixup> &Fixups) const {
466 // {9} 1 == imm8, 0 == Rm
470 const MCOperand &MO = MI.getOperand(OpIdx);
471 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
472 unsigned Imm = MO1.getImm();
473 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
474 bool isImm = MO.getReg() == 0;
475 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
476 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
478 Imm8 = getARMRegisterNumbering(MO.getReg());
479 return Imm8 | (isAdd << 8) | (isImm << 9);
482 uint32_t ARMMCCodeEmitter::
483 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
484 SmallVectorImpl<MCFixup> &Fixups) const {
485 // {13} 1 == imm8, 0 == Rm
490 const MCOperand &MO = MI.getOperand(OpIdx);
491 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
492 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
493 unsigned Rn = getARMRegisterNumbering(MO.getReg());
494 unsigned Imm = MO2.getImm();
495 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
496 bool isImm = MO1.getReg() == 0;
497 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
498 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
500 Imm8 = getARMRegisterNumbering(MO1.getReg());
501 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
504 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
505 uint32_t ARMMCCodeEmitter::
506 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
507 SmallVectorImpl<MCFixup> &Fixups) const {
509 // {8} = (U)nsigned (add == '1', sub == '0')
512 // If The first operand isn't a register, we have a label reference.
513 const MCOperand &MO = MI.getOperand(OpIdx);
515 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
518 assert(MO.isExpr() && "Unexpected machine operand type!");
519 const MCExpr *Expr = MO.getExpr();
520 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
521 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
523 ++MCNumCPRelocations;
525 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
527 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
528 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
529 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
531 Binary |= (Reg << 9);
535 unsigned ARMMCCodeEmitter::
536 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
537 SmallVectorImpl<MCFixup> &Fixups) const {
538 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
539 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
540 // case the imm contains the amount to shift by.
543 // {4} = 1 if reg shift, 0 if imm shift
551 const MCOperand &MO = MI.getOperand(OpIdx);
552 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
553 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
554 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
557 unsigned Binary = getARMRegisterNumbering(MO.getReg());
559 // Encode the shift opcode.
561 unsigned Rs = MO1.getReg();
563 // Set shift operand (bit[7:4]).
568 // RRX - 0110 and bit[11:8] clear.
570 default: llvm_unreachable("Unknown shift opc!");
571 case ARM_AM::lsl: SBits = 0x1; break;
572 case ARM_AM::lsr: SBits = 0x3; break;
573 case ARM_AM::asr: SBits = 0x5; break;
574 case ARM_AM::ror: SBits = 0x7; break;
575 case ARM_AM::rrx: SBits = 0x6; break;
578 // Set shift operand (bit[6:4]).
584 default: llvm_unreachable("Unknown shift opc!");
585 case ARM_AM::lsl: SBits = 0x0; break;
586 case ARM_AM::lsr: SBits = 0x2; break;
587 case ARM_AM::asr: SBits = 0x4; break;
588 case ARM_AM::ror: SBits = 0x6; break;
592 Binary |= SBits << 4;
593 if (SOpc == ARM_AM::rrx)
596 // Encode the shift operation Rs or shift_imm (except rrx).
598 // Encode Rs bit[11:8].
599 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
600 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
603 // Encode shift_imm bit[11:7].
604 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
607 unsigned ARMMCCodeEmitter::
608 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
609 SmallVectorImpl<MCFixup> &Fixups) const {
610 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
611 // shifted. The second is the amount to shift by.
618 const MCOperand &MO = MI.getOperand(OpIdx);
619 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
620 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
623 unsigned Binary = getARMRegisterNumbering(MO.getReg());
625 // Encode the shift opcode.
627 // Set shift operand (bit[6:4]).
633 default: llvm_unreachable("Unknown shift opc!");
634 case ARM_AM::lsl: SBits = 0x0; break;
635 case ARM_AM::lsr: SBits = 0x2; break;
636 case ARM_AM::asr: SBits = 0x4; break;
637 case ARM_AM::ror: SBits = 0x6; break;
640 Binary |= SBits << 4;
641 if (SOpc == ARM_AM::rrx)
644 // Encode shift_imm bit[11:7].
645 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
648 unsigned ARMMCCodeEmitter::
649 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
650 SmallVectorImpl<MCFixup> &Fixups) const {
651 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
653 const MCOperand &MO = MI.getOperand(Op);
654 uint32_t v = ~MO.getImm();
655 uint32_t lsb = CountTrailingZeros_32(v);
656 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
657 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
658 return lsb | (msb << 5);
661 unsigned ARMMCCodeEmitter::
662 getRegisterListOpValue(const MCInst &MI, unsigned Op,
663 SmallVectorImpl<MCFixup> &Fixups) const {
666 // {7-0} = Number of registers
669 // {15-0} = Bitfield of GPRs.
670 unsigned Reg = MI.getOperand(Op).getReg();
671 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
672 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
676 if (SPRRegs || DPRRegs) {
678 unsigned RegNo = getARMRegisterNumbering(Reg);
679 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
680 Binary |= (RegNo & 0x1f) << 8;
684 Binary |= NumRegs * 2;
686 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
687 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
688 Binary |= 1 << RegNo;
695 unsigned ARMMCCodeEmitter::
696 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
697 SmallVectorImpl<MCFixup> &Fixups) const {
698 const MCOperand &Reg = MI.getOperand(Op);
699 const MCOperand &Imm = MI.getOperand(Op + 1);
701 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
704 switch (Imm.getImm()) {
708 case 8: Align = 0x01; break;
709 case 16: Align = 0x02; break;
710 case 32: Align = 0x03; break;
713 return RegNo | (Align << 4);
716 unsigned ARMMCCodeEmitter::
717 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
718 SmallVectorImpl<MCFixup> &Fixups) const {
719 const MCOperand &MO = MI.getOperand(Op);
720 if (MO.getReg() == 0) return 0x0D;
724 void ARMMCCodeEmitter::
725 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
726 SmallVectorImpl<MCFixup> &Fixups) const {
727 // Pseudo instructions don't get encoded.
728 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
729 uint64_t TSFlags = Desc.TSFlags;
730 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
733 // Basic size info comes from the TSFlags field.
734 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
735 default: llvm_unreachable("Unexpected instruction size!");
736 case ARMII::Size2Bytes: Size = 2; break;
737 case ARMII::Size4Bytes: Size = 4; break;
739 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
740 ++MCNumEmitted; // Keep track of the # of mi's emitted.
743 #include "ARMGenMCCodeEmitter.inc"