1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name off bits flags
49 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
51 MCFixupKindInfo::FKF_IsAligned},
52 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
54 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
55 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
56 { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
57 MCFixupKindInfo::FKF_IsAligned},
58 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
59 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
60 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
61 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
62 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
63 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_arm_movt_hi16", 0, 16, 0 },
65 { "fixup_arm_movw_lo16", 0, 16, 0 },
68 if (Kind < FirstTargetFixupKind)
69 return MCCodeEmitter::getFixupKindInfo(Kind);
71 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
73 return Infos[Kind - FirstTargetFixupKind];
75 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 // getBinaryCodeForInstr - TableGen'erated function for getting the
78 // binary encoding for an instruction.
79 unsigned getBinaryCodeForInstr(const MCInst &MI,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 /// getMachineOpValue - Return binary encoding of operand. If the machine
83 /// operand requires relocation, record the relocation and return zero.
84 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
88 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 unsigned &Reg, unsigned &Imm,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
97 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const;
100 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
101 /// BLX branch target.
102 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
106 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
107 SmallVectorImpl<MCFixup> &Fixups) const;
109 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
110 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
114 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
123 /// ADR label target.
124 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
129 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
130 SmallVectorImpl<MCFixup> &Fixups) const;
132 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
134 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const;
138 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
139 /// operand as needed by load/store instructions.
140 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
144 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups) const {
146 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
148 default: assert(0 && "Unknown addressing sub-mode!");
149 case ARM_AM::da: return 0;
150 case ARM_AM::ia: return 1;
151 case ARM_AM::db: return 2;
152 case ARM_AM::ib: return 3;
155 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
157 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
159 default: llvm_unreachable("Unknown shift opc!");
160 case ARM_AM::no_shift:
161 case ARM_AM::lsl: return 0;
162 case ARM_AM::lsr: return 1;
163 case ARM_AM::asr: return 2;
165 case ARM_AM::rrx: return 3;
170 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
171 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
172 SmallVectorImpl<MCFixup> &Fixups) const;
174 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
175 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
176 SmallVectorImpl<MCFixup> &Fixups) const;
178 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
179 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
180 SmallVectorImpl<MCFixup> &Fixups) const;
182 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
183 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
184 SmallVectorImpl<MCFixup> &Fixups) const;
186 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
188 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
189 SmallVectorImpl<MCFixup> &Fixups) const;
191 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
192 uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
193 SmallVectorImpl<MCFixup> &) const;
195 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
196 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
197 SmallVectorImpl<MCFixup> &Fixups) const;
199 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
200 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups) const;
203 /// getCCOutOpValue - Return encoding of the 's' bit.
204 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
205 SmallVectorImpl<MCFixup> &Fixups) const {
206 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
208 return MI.getOperand(Op).getReg() == ARM::CPSR;
211 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
212 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
213 SmallVectorImpl<MCFixup> &Fixups) const {
214 unsigned SoImm = MI.getOperand(Op).getImm();
215 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
216 assert(SoImmVal != -1 && "Not a valid so_imm value!");
218 // Encode rotate_imm.
219 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
220 << ARMII::SoRotImmShift;
223 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
227 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
228 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
229 SmallVectorImpl<MCFixup> &Fixups) const {
230 unsigned SoImm = MI.getOperand(Op).getImm();
231 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
232 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
236 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
237 SmallVectorImpl<MCFixup> &Fixups) const;
238 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
239 SmallVectorImpl<MCFixup> &Fixups) const;
240 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
241 SmallVectorImpl<MCFixup> &Fixups) const;
242 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
243 SmallVectorImpl<MCFixup> &Fixups) const;
245 /// getSORegOpValue - Return an encoded so_reg shifted register value.
246 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
247 SmallVectorImpl<MCFixup> &Fixups) const;
248 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
249 SmallVectorImpl<MCFixup> &Fixups) const;
251 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
252 SmallVectorImpl<MCFixup> &Fixups) const {
253 switch (MI.getOperand(Op).getImm()) {
254 default: assert (0 && "Not a valid rot_imm value!");
262 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
263 SmallVectorImpl<MCFixup> &Fixups) const {
264 return MI.getOperand(Op).getImm() - 1;
267 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
268 SmallVectorImpl<MCFixup> &Fixups) const {
269 return 64 - MI.getOperand(Op).getImm();
272 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
273 SmallVectorImpl<MCFixup> &Fixups) const;
275 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
276 SmallVectorImpl<MCFixup> &Fixups) const;
277 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
278 SmallVectorImpl<MCFixup> &Fixups) const;
279 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
280 SmallVectorImpl<MCFixup> &Fixups) const;
281 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
282 SmallVectorImpl<MCFixup> &Fixups) const;
284 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
285 unsigned EncodedValue) const;
286 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
287 unsigned EncodedValue) const;
288 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
289 unsigned EncodedValue) const;
291 unsigned VFPThumb2PostEncoder(const MCInst &MI,
292 unsigned EncodedValue) const;
294 void EmitByte(unsigned char C, raw_ostream &OS) const {
298 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
299 // Output the constant in little endian byte order.
300 for (unsigned i = 0; i != Size; ++i) {
301 EmitByte(Val & 255, OS);
306 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
307 SmallVectorImpl<MCFixup> &Fixups) const;
310 } // end anonymous namespace
312 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
314 return new ARMMCCodeEmitter(TM, Ctx);
317 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
318 /// instructions, and rewrite them to their Thumb2 form if we are currently in
320 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
321 unsigned EncodedValue) const {
322 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
323 if (Subtarget.isThumb2()) {
324 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
325 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
327 unsigned Bit24 = EncodedValue & 0x01000000;
328 unsigned Bit28 = Bit24 << 4;
329 EncodedValue &= 0xEFFFFFFF;
330 EncodedValue |= Bit28;
331 EncodedValue |= 0x0F000000;
337 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
338 /// instructions, and rewrite them to their Thumb2 form if we are currently in
340 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
341 unsigned EncodedValue) const {
342 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
343 if (Subtarget.isThumb2()) {
344 EncodedValue &= 0xF0FFFFFF;
345 EncodedValue |= 0x09000000;
351 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
352 /// instructions, and rewrite them to their Thumb2 form if we are currently in
354 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
355 unsigned EncodedValue) const {
356 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
357 if (Subtarget.isThumb2()) {
358 EncodedValue &= 0x00FFFFFF;
359 EncodedValue |= 0xEE000000;
365 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
366 /// them to their Thumb2 form if we are currently in Thumb2 mode.
367 unsigned ARMMCCodeEmitter::
368 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
369 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
370 EncodedValue &= 0x0FFFFFFF;
371 EncodedValue |= 0xE0000000;
376 /// getMachineOpValue - Return binary encoding of operand. If the machine
377 /// operand requires relocation, record the relocation and return zero.
378 unsigned ARMMCCodeEmitter::
379 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
380 SmallVectorImpl<MCFixup> &Fixups) const {
382 unsigned Reg = MO.getReg();
383 unsigned RegNo = getARMRegisterNumbering(Reg);
385 // Q registers are encoded as 2x their register number.
389 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
390 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
391 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
392 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
395 } else if (MO.isImm()) {
396 return static_cast<unsigned>(MO.getImm());
397 } else if (MO.isFPImm()) {
398 return static_cast<unsigned>(APFloat(MO.getFPImm())
399 .bitcastToAPInt().getHiBits(32).getLimitedValue());
402 llvm_unreachable("Unable to encode MCOperand!");
406 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
407 bool ARMMCCodeEmitter::
408 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
409 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
410 const MCOperand &MO = MI.getOperand(OpIdx);
411 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
413 Reg = getARMRegisterNumbering(MO.getReg());
415 int32_t SImm = MO1.getImm();
418 // Special value for #-0
419 if (SImm == INT32_MIN)
422 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
432 /// getBranchTargetOpValue - Helper function to get the branch target operand,
433 /// which is either an immediate or requires a fixup.
434 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
436 SmallVectorImpl<MCFixup> &Fixups) {
437 const MCOperand &MO = MI.getOperand(OpIdx);
439 // If the destination is an immediate, we have nothing to do.
440 if (MO.isImm()) return MO.getImm();
441 assert(MO.isExpr() && "Unexpected branch target type!");
442 const MCExpr *Expr = MO.getExpr();
443 MCFixupKind Kind = MCFixupKind(FixupKind);
444 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
446 // All of the information is in the fixup.
450 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
451 uint32_t ARMMCCodeEmitter::
452 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
453 SmallVectorImpl<MCFixup> &Fixups) const {
454 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
457 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
458 /// BLX branch target.
459 uint32_t ARMMCCodeEmitter::
460 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
461 SmallVectorImpl<MCFixup> &Fixups) const {
462 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
465 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
466 uint32_t ARMMCCodeEmitter::
467 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
468 SmallVectorImpl<MCFixup> &Fixups) const {
469 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
472 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
473 uint32_t ARMMCCodeEmitter::
474 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
475 SmallVectorImpl<MCFixup> &Fixups) const {
476 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
479 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
480 uint32_t ARMMCCodeEmitter::
481 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
482 SmallVectorImpl<MCFixup> &Fixups) const {
483 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
486 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
488 uint32_t ARMMCCodeEmitter::
489 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
490 SmallVectorImpl<MCFixup> &Fixups) const {
491 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
492 if (Subtarget.isThumb2())
493 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_branch, Fixups);
494 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
497 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
499 uint32_t ARMMCCodeEmitter::
500 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
501 SmallVectorImpl<MCFixup> &Fixups) const {
502 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
507 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
508 uint32_t ARMMCCodeEmitter::
509 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
510 SmallVectorImpl<MCFixup> &Fixups) const {
512 // {12} = (U)nsigned (add == '1', sub == '0')
516 // If The first operand isn't a register, we have a label reference.
517 const MCOperand &MO = MI.getOperand(OpIdx);
518 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
519 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
520 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
522 isAdd = false ; // 'U' bit is set as part of the fixup.
524 const MCExpr *Expr = 0;
528 Expr = MO2.getExpr();
530 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
532 if (Subtarget.isThumb2())
533 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
535 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
536 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
538 ++MCNumCPRelocations;
540 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
542 uint32_t Binary = Imm12 & 0xfff;
543 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
546 Binary |= (Reg << 13);
550 /// getT2AddrModeImm8s4OpValue - Return encoding info for
551 /// 'reg +/- imm8<<2' operand.
552 uint32_t ARMMCCodeEmitter::
553 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
554 SmallVectorImpl<MCFixup> &Fixups) const {
556 // {8} = (U)nsigned (add == '1', sub == '0')
560 // If The first operand isn't a register, we have a label reference.
561 const MCOperand &MO = MI.getOperand(OpIdx);
563 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
565 isAdd = false ; // 'U' bit is set as part of the fixup.
567 assert(MO.isExpr() && "Unexpected machine operand type!");
568 const MCExpr *Expr = MO.getExpr();
569 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
570 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
572 ++MCNumCPRelocations;
574 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
576 uint32_t Binary = (Imm8 >> 2) & 0xff;
577 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
580 Binary |= (Reg << 9);
584 uint32_t ARMMCCodeEmitter::
585 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
586 SmallVectorImpl<MCFixup> &Fixups) const {
587 // {20-16} = imm{15-12}
588 // {11-0} = imm{11-0}
589 const MCOperand &MO = MI.getOperand(OpIdx);
591 return static_cast<unsigned>(MO.getImm());
592 } else if (const MCSymbolRefExpr *Expr =
593 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
595 switch (Expr->getKind()) {
596 default: assert(0 && "Unsupported ARMFixup");
597 case MCSymbolRefExpr::VK_ARM_HI16:
598 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
600 case MCSymbolRefExpr::VK_ARM_LO16:
601 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
604 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
607 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
611 uint32_t ARMMCCodeEmitter::
612 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
613 SmallVectorImpl<MCFixup> &Fixups) const {
614 const MCOperand &MO = MI.getOperand(OpIdx);
615 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
616 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
617 unsigned Rn = getARMRegisterNumbering(MO.getReg());
618 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
619 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
620 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
621 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
622 unsigned SBits = getShiftOp(ShOp);
631 uint32_t Binary = Rm;
633 Binary |= SBits << 5;
634 Binary |= ShImm << 7;
640 uint32_t ARMMCCodeEmitter::
641 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
642 SmallVectorImpl<MCFixup> &Fixups) const {
644 // {13} 1 == imm12, 0 == Rm
647 const MCOperand &MO = MI.getOperand(OpIdx);
648 unsigned Rn = getARMRegisterNumbering(MO.getReg());
649 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
654 uint32_t ARMMCCodeEmitter::
655 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
656 SmallVectorImpl<MCFixup> &Fixups) const {
657 // {13} 1 == imm12, 0 == Rm
660 const MCOperand &MO = MI.getOperand(OpIdx);
661 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
662 unsigned Imm = MO1.getImm();
663 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
664 bool isReg = MO.getReg() != 0;
665 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
666 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
668 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
669 Binary <<= 7; // Shift amount is bits [11:7]
670 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
671 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
673 return Binary | (isAdd << 12) | (isReg << 13);
676 uint32_t ARMMCCodeEmitter::
677 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
678 SmallVectorImpl<MCFixup> &Fixups) const {
679 // {9} 1 == imm8, 0 == Rm
683 const MCOperand &MO = MI.getOperand(OpIdx);
684 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
685 unsigned Imm = MO1.getImm();
686 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
687 bool isImm = MO.getReg() == 0;
688 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
689 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
691 Imm8 = getARMRegisterNumbering(MO.getReg());
692 return Imm8 | (isAdd << 8) | (isImm << 9);
695 uint32_t ARMMCCodeEmitter::
696 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
697 SmallVectorImpl<MCFixup> &Fixups) const {
698 // {13} 1 == imm8, 0 == Rm
703 const MCOperand &MO = MI.getOperand(OpIdx);
704 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
705 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
706 unsigned Rn = getARMRegisterNumbering(MO.getReg());
707 unsigned Imm = MO2.getImm();
708 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
709 bool isImm = MO1.getReg() == 0;
710 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
711 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
713 Imm8 = getARMRegisterNumbering(MO1.getReg());
714 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
717 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
718 uint32_t ARMMCCodeEmitter::
719 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
720 SmallVectorImpl<MCFixup> &Fixups) const {
723 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
724 #if 0 // FIXME: This crashes2003-05-14-initialize-string.c
725 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
726 "Unexpected base register!");
728 // The immediate is already shifted for the implicit zeroes, so no change
730 return MO1.getImm() & 0xff;
733 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
734 uint32_t ARMMCCodeEmitter::
735 getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
736 SmallVectorImpl<MCFixup> &) const {
744 const MCOperand &MO = MI.getOperand(OpIdx);
745 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
746 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
747 unsigned Rn = getARMRegisterNumbering(MO.getReg());
748 unsigned Imm5 = MO1.getImm();
750 if (MO2.getReg() != 0)
752 Imm5 = getARMRegisterNumbering(MO2.getReg());
754 return ((Imm5 & 0x1f) << 3) | Rn;
757 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
758 uint32_t ARMMCCodeEmitter::
759 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
760 SmallVectorImpl<MCFixup> &Fixups) const {
761 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
764 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
765 uint32_t ARMMCCodeEmitter::
766 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
767 SmallVectorImpl<MCFixup> &Fixups) const {
769 // {8} = (U)nsigned (add == '1', sub == '0')
773 // If The first operand isn't a register, we have a label reference.
774 const MCOperand &MO = MI.getOperand(OpIdx);
776 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
778 isAdd = false; // 'U' bit is handled as part of the fixup.
780 assert(MO.isExpr() && "Unexpected machine operand type!");
781 const MCExpr *Expr = MO.getExpr();
783 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
784 if (Subtarget.isThumb2())
785 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
787 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
788 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
790 ++MCNumCPRelocations;
792 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
793 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
796 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
797 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
800 Binary |= (Reg << 9);
804 unsigned ARMMCCodeEmitter::
805 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
806 SmallVectorImpl<MCFixup> &Fixups) const {
807 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
808 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
809 // case the imm contains the amount to shift by.
812 // {4} = 1 if reg shift, 0 if imm shift
820 const MCOperand &MO = MI.getOperand(OpIdx);
821 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
822 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
823 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
826 unsigned Binary = getARMRegisterNumbering(MO.getReg());
828 // Encode the shift opcode.
830 unsigned Rs = MO1.getReg();
832 // Set shift operand (bit[7:4]).
837 // RRX - 0110 and bit[11:8] clear.
839 default: llvm_unreachable("Unknown shift opc!");
840 case ARM_AM::lsl: SBits = 0x1; break;
841 case ARM_AM::lsr: SBits = 0x3; break;
842 case ARM_AM::asr: SBits = 0x5; break;
843 case ARM_AM::ror: SBits = 0x7; break;
844 case ARM_AM::rrx: SBits = 0x6; break;
847 // Set shift operand (bit[6:4]).
853 default: llvm_unreachable("Unknown shift opc!");
854 case ARM_AM::lsl: SBits = 0x0; break;
855 case ARM_AM::lsr: SBits = 0x2; break;
856 case ARM_AM::asr: SBits = 0x4; break;
857 case ARM_AM::ror: SBits = 0x6; break;
861 Binary |= SBits << 4;
862 if (SOpc == ARM_AM::rrx)
865 // Encode the shift operation Rs or shift_imm (except rrx).
867 // Encode Rs bit[11:8].
868 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
869 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
872 // Encode shift_imm bit[11:7].
873 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
876 unsigned ARMMCCodeEmitter::
877 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
878 SmallVectorImpl<MCFixup> &Fixups) const {
879 const MCOperand &MO1 = MI.getOperand(OpNum);
880 const MCOperand &MO2 = MI.getOperand(OpNum+1);
881 const MCOperand &MO3 = MI.getOperand(OpNum+2);
883 // Encoded as [Rn, Rm, imm].
884 // FIXME: Needs fixup support.
885 unsigned Value = getARMRegisterNumbering(MO1.getReg());
887 Value |= getARMRegisterNumbering(MO2.getReg());
889 Value |= MO3.getImm();
894 unsigned ARMMCCodeEmitter::
895 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
896 SmallVectorImpl<MCFixup> &Fixups) const {
897 const MCOperand &MO1 = MI.getOperand(OpNum);
898 const MCOperand &MO2 = MI.getOperand(OpNum+1);
900 // FIXME: Needs fixup support.
901 unsigned Value = getARMRegisterNumbering(MO1.getReg());
903 // Even though the immediate is 8 bits long, we need 9 bits in order
904 // to represent the (inverse of the) sign bit.
906 int32_t tmp = (int32_t)MO2.getImm();
910 Value |= 256; // Set the ADD bit
915 unsigned ARMMCCodeEmitter::
916 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
917 SmallVectorImpl<MCFixup> &Fixups) const {
918 const MCOperand &MO1 = MI.getOperand(OpNum);
920 // FIXME: Needs fixup support.
922 int32_t tmp = (int32_t)MO1.getImm();
926 Value |= 256; // Set the ADD bit
931 unsigned ARMMCCodeEmitter::
932 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
933 SmallVectorImpl<MCFixup> &Fixups) const {
934 const MCOperand &MO1 = MI.getOperand(OpNum);
936 // FIXME: Needs fixup support.
938 int32_t tmp = (int32_t)MO1.getImm();
942 Value |= 4096; // Set the ADD bit
947 unsigned ARMMCCodeEmitter::
948 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
949 SmallVectorImpl<MCFixup> &Fixups) const {
950 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
951 // shifted. The second is the amount to shift by.
958 const MCOperand &MO = MI.getOperand(OpIdx);
959 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
960 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
963 unsigned Binary = getARMRegisterNumbering(MO.getReg());
965 // Encode the shift opcode.
967 // Set shift operand (bit[6:4]).
973 default: llvm_unreachable("Unknown shift opc!");
974 case ARM_AM::lsl: SBits = 0x0; break;
975 case ARM_AM::lsr: SBits = 0x2; break;
976 case ARM_AM::asr: SBits = 0x4; break;
977 case ARM_AM::ror: SBits = 0x6; break;
980 Binary |= SBits << 4;
981 if (SOpc == ARM_AM::rrx)
984 // Encode shift_imm bit[11:7].
985 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
988 unsigned ARMMCCodeEmitter::
989 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
990 SmallVectorImpl<MCFixup> &Fixups) const {
991 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
993 const MCOperand &MO = MI.getOperand(Op);
994 uint32_t v = ~MO.getImm();
995 uint32_t lsb = CountTrailingZeros_32(v);
996 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
997 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
998 return lsb | (msb << 5);
1001 unsigned ARMMCCodeEmitter::
1002 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1003 SmallVectorImpl<MCFixup> &Fixups) const {
1006 // {7-0} = Number of registers
1009 // {15-0} = Bitfield of GPRs.
1010 unsigned Reg = MI.getOperand(Op).getReg();
1011 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1012 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1014 unsigned Binary = 0;
1016 if (SPRRegs || DPRRegs) {
1018 unsigned RegNo = getARMRegisterNumbering(Reg);
1019 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1020 Binary |= (RegNo & 0x1f) << 8;
1024 Binary |= NumRegs * 2;
1026 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1027 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1028 Binary |= 1 << RegNo;
1035 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1036 /// with the alignment operand.
1037 unsigned ARMMCCodeEmitter::
1038 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1039 SmallVectorImpl<MCFixup> &Fixups) const {
1040 const MCOperand &Reg = MI.getOperand(Op);
1041 const MCOperand &Imm = MI.getOperand(Op + 1);
1043 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1046 switch (Imm.getImm()) {
1050 case 8: Align = 0x01; break;
1051 case 16: Align = 0x02; break;
1052 case 32: Align = 0x03; break;
1055 return RegNo | (Align << 4);
1058 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1059 /// alignment operand for use in VLD-dup instructions. This is the same as
1060 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1061 /// different for VLD4-dup.
1062 unsigned ARMMCCodeEmitter::
1063 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1064 SmallVectorImpl<MCFixup> &Fixups) const {
1065 const MCOperand &Reg = MI.getOperand(Op);
1066 const MCOperand &Imm = MI.getOperand(Op + 1);
1068 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1071 switch (Imm.getImm()) {
1075 case 8: Align = 0x01; break;
1076 case 16: Align = 0x03; break;
1079 return RegNo | (Align << 4);
1082 unsigned ARMMCCodeEmitter::
1083 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1084 SmallVectorImpl<MCFixup> &Fixups) const {
1085 const MCOperand &MO = MI.getOperand(Op);
1086 if (MO.getReg() == 0) return 0x0D;
1090 void ARMMCCodeEmitter::
1091 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1092 SmallVectorImpl<MCFixup> &Fixups) const {
1093 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1094 // Pseudo instructions don't get encoded.
1095 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1096 uint64_t TSFlags = Desc.TSFlags;
1097 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1100 // Basic size info comes from the TSFlags field.
1101 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1102 default: llvm_unreachable("Unexpected instruction size!");
1103 case ARMII::Size2Bytes: Size = 2; break;
1104 case ARMII::Size4Bytes: Size = 4; break;
1106 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1107 // Thumb 32-bit wide instructions need to be have the high order halfword
1109 if (Subtarget.isThumb() && Size == 4) {
1110 EmitConstant(Binary >> 16, 2, OS);
1111 EmitConstant(Binary & 0xffff, 2, OS);
1113 EmitConstant(Binary, Size, OS);
1114 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1117 #include "ARMGenMCCodeEmitter.inc"