1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class ARMMCCodeEmitter : public MCCodeEmitter {
29 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
32 const TargetInstrInfo &TII;
36 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
37 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
40 ~ARMMCCodeEmitter() {}
42 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
44 // getBinaryCodeForInstr - TableGen'erated function for getting the
45 // binary encoding for an instruction.
46 unsigned getBinaryCodeForInstr(const MCInst &MI) const;
48 /// getMachineOpValue - Return binary encoding of operand. If the machine
49 /// operand requires relocation, record the relocation and return zero.
50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
52 /// getCCOutOpValue - Return encoding of the 's' bit.
53 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
54 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
56 return MI.getOperand(Op).getReg() == ARM::CPSR;
59 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
60 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const {
61 unsigned SoImm = MI.getOperand(Op).getImm();
62 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
63 assert(SoImmVal != -1 && "Not a valid so_imm value!");
66 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
67 << ARMII::SoRotImmShift;
70 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
74 /// getSORegOpValue - Return an encoded so_reg shifted register value.
75 unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const;
77 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const {
78 switch (MI.getOperand(Op).getImm()) {
79 default: assert (0 && "Not a valid rot_imm value!");
87 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
88 return MI.getOperand(Op).getImm() - 1;
91 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
93 unsigned getNumFixupKinds() const {
94 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
98 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
99 static MCFixupKindInfo rtn;
100 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
104 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
109 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
110 raw_ostream &OS) const {
111 // Output the constant in little endian byte order.
112 for (unsigned i = 0; i != Size; ++i) {
113 EmitByte(Val & 255, CurByte, OS);
118 void EmitImmediate(const MCOperand &Disp,
119 unsigned ImmSize, MCFixupKind FixupKind,
120 unsigned &CurByte, raw_ostream &OS,
121 SmallVectorImpl<MCFixup> &Fixups,
122 int ImmOffset = 0) const;
124 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
125 SmallVectorImpl<MCFixup> &Fixups) const;
128 } // end anonymous namespace
130 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
133 return new ARMMCCodeEmitter(TM, Ctx);
136 void ARMMCCodeEmitter::
137 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
138 unsigned &CurByte, raw_ostream &OS,
139 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
140 assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
143 /// getMachineOpValue - Return binary encoding of operand. If the machine
144 /// operand requires relocation, record the relocation and return zero.
145 unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
146 const MCOperand &MO) const {
148 unsigned regno = getARMRegisterNumbering(MO.getReg());
150 // Q registers are encodes as 2x their register number.
151 switch (MO.getReg()) {
152 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
153 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
154 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
155 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
160 } else if (MO.isImm()) {
161 return static_cast<unsigned>(MO.getImm());
162 } else if (MO.isFPImm()) {
163 return static_cast<unsigned>(APFloat(MO.getFPImm())
164 .bitcastToAPInt().getHiBits(32).getLimitedValue());
174 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
175 unsigned OpIdx) const {
176 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg
177 // to be shifted. The second is either Rs, the amount to shift by, or
178 // reg0 in which case the imm contains the amount to shift by.
180 // {4} = 1 if reg shift, 0 if imm shift
188 const MCOperand &MO = MI.getOperand(OpIdx);
189 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
190 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
191 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
194 unsigned Binary = getARMRegisterNumbering(MO.getReg());
196 // Encode the shift opcode.
198 unsigned Rs = MO1.getReg();
200 // Set shift operand (bit[7:4]).
205 // RRX - 0110 and bit[11:8] clear.
207 default: llvm_unreachable("Unknown shift opc!");
208 case ARM_AM::lsl: SBits = 0x1; break;
209 case ARM_AM::lsr: SBits = 0x3; break;
210 case ARM_AM::asr: SBits = 0x5; break;
211 case ARM_AM::ror: SBits = 0x7; break;
212 case ARM_AM::rrx: SBits = 0x6; break;
215 // Set shift operand (bit[6:4]).
221 default: llvm_unreachable("Unknown shift opc!");
222 case ARM_AM::lsl: SBits = 0x0; break;
223 case ARM_AM::lsr: SBits = 0x2; break;
224 case ARM_AM::asr: SBits = 0x4; break;
225 case ARM_AM::ror: SBits = 0x6; break;
228 Binary |= SBits << 4;
229 if (SOpc == ARM_AM::rrx)
232 // Encode the shift operation Rs or shift_imm (except rrx).
234 // Encode Rs bit[11:8].
235 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
236 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
239 // Encode shift_imm bit[11:7].
240 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
243 unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
245 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
247 const MCOperand &MO = MI.getOperand(Op);
248 uint32_t v = ~MO.getImm();
249 uint32_t lsb = CountTrailingZeros_32(v);
250 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
251 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
252 return lsb | (msb << 5);
255 void ARMMCCodeEmitter::
256 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
257 SmallVectorImpl<MCFixup> &Fixups) const {
258 unsigned Opcode = MI.getOpcode();
259 const TargetInstrDesc &Desc = TII.get(Opcode);
260 uint64_t TSFlags = Desc.TSFlags;
261 // Keep track of the current byte being emitted.
262 unsigned CurByte = 0;
264 // Pseudo instructions don't get encoded.
265 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
268 ++MCNumEmitted; // Keep track of the # of mi's emitted
269 unsigned Value = getBinaryCodeForInstr(MI);
273 EmitConstant(Value, 4, CurByte, OS);
276 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
277 // be able to generate code emitter helpers for either variant, like it
278 // does for the AsmWriter.
279 #define ARMCodeEmitter ARMMCCodeEmitter
280 #define MachineInstr MCInst
281 #include "ARMGenCodeEmitter.inc"
282 #undef ARMCodeEmitter