1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name off bits flags
49 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
51 MCFixupKindInfo::FKF_IsAligned},
52 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
54 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
55 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
56 { "fixup_t2_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
57 MCFixupKindInfo::FKF_IsAligned},
58 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
59 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
60 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
61 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
62 { "fixup_arm_movt_hi16", 0, 16, 0 },
63 { "fixup_arm_movw_lo16", 0, 16, 0 },
66 if (Kind < FirstTargetFixupKind)
67 return MCCodeEmitter::getFixupKindInfo(Kind);
69 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
71 return Infos[Kind - FirstTargetFixupKind];
73 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
75 // getBinaryCodeForInstr - TableGen'erated function for getting the
76 // binary encoding for an instruction.
77 unsigned getBinaryCodeForInstr(const MCInst &MI,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 /// getMachineOpValue - Return binary encoding of operand. If the machine
81 /// operand requires relocation, record the relocation and return zero.
82 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
86 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
87 SmallVectorImpl<MCFixup> &Fixups) const;
89 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
90 unsigned &Reg, unsigned &Imm,
91 SmallVectorImpl<MCFixup> &Fixups) const;
93 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
95 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 SmallVectorImpl<MCFixup> &Fixups) const;
98 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
99 /// BLX branch target.
100 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
113 /// ADR label target.
114 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
119 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
124 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
128 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
129 /// operand as needed by load/store instructions.
130 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
131 SmallVectorImpl<MCFixup> &Fixups) const;
133 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
134 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
135 SmallVectorImpl<MCFixup> &Fixups) const {
136 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
138 default: assert(0 && "Unknown addressing sub-mode!");
139 case ARM_AM::da: return 0;
140 case ARM_AM::ia: return 1;
141 case ARM_AM::db: return 2;
142 case ARM_AM::ib: return 3;
145 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
147 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
149 default: llvm_unreachable("Unknown shift opc!");
150 case ARM_AM::no_shift:
151 case ARM_AM::lsl: return 0;
152 case ARM_AM::lsr: return 1;
153 case ARM_AM::asr: return 2;
155 case ARM_AM::rrx: return 3;
160 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
161 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups) const;
164 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
165 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups) const;
168 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
169 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
170 SmallVectorImpl<MCFixup> &Fixups) const;
172 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
173 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
174 SmallVectorImpl<MCFixup> &Fixups) const;
176 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
178 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
179 SmallVectorImpl<MCFixup> &Fixups) const;
181 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
182 uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &) const;
185 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
186 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
187 SmallVectorImpl<MCFixup> &Fixups) const;
189 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
190 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
191 SmallVectorImpl<MCFixup> &Fixups) const;
193 /// getCCOutOpValue - Return encoding of the 's' bit.
194 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
195 SmallVectorImpl<MCFixup> &Fixups) const {
196 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
198 return MI.getOperand(Op).getReg() == ARM::CPSR;
201 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
202 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
203 SmallVectorImpl<MCFixup> &Fixups) const {
204 unsigned SoImm = MI.getOperand(Op).getImm();
205 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
206 assert(SoImmVal != -1 && "Not a valid so_imm value!");
208 // Encode rotate_imm.
209 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
210 << ARMII::SoRotImmShift;
213 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
217 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
218 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
219 SmallVectorImpl<MCFixup> &Fixups) const {
220 unsigned SoImm = MI.getOperand(Op).getImm();
221 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
222 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
226 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
227 SmallVectorImpl<MCFixup> &Fixups) const;
228 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
229 SmallVectorImpl<MCFixup> &Fixups) const;
230 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
231 SmallVectorImpl<MCFixup> &Fixups) const;
232 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
233 SmallVectorImpl<MCFixup> &Fixups) const;
235 /// getSORegOpValue - Return an encoded so_reg shifted register value.
236 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
237 SmallVectorImpl<MCFixup> &Fixups) const;
238 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
239 SmallVectorImpl<MCFixup> &Fixups) const;
241 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
242 SmallVectorImpl<MCFixup> &Fixups) const {
243 switch (MI.getOperand(Op).getImm()) {
244 default: assert (0 && "Not a valid rot_imm value!");
252 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
253 SmallVectorImpl<MCFixup> &Fixups) const {
254 return MI.getOperand(Op).getImm() - 1;
257 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
258 SmallVectorImpl<MCFixup> &Fixups) const {
259 return 64 - MI.getOperand(Op).getImm();
262 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
263 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
266 SmallVectorImpl<MCFixup> &Fixups) const;
267 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
268 SmallVectorImpl<MCFixup> &Fixups) const;
269 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
270 SmallVectorImpl<MCFixup> &Fixups) const;
271 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
272 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
275 unsigned EncodedValue) const;
276 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
277 unsigned EncodedValue) const;
278 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
279 unsigned EncodedValue) const;
281 unsigned VFPThumb2PostEncoder(const MCInst &MI,
282 unsigned EncodedValue) const;
284 void EmitByte(unsigned char C, raw_ostream &OS) const {
288 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
289 // Output the constant in little endian byte order.
290 for (unsigned i = 0; i != Size; ++i) {
291 EmitByte(Val & 255, OS);
296 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
297 SmallVectorImpl<MCFixup> &Fixups) const;
300 } // end anonymous namespace
302 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
304 return new ARMMCCodeEmitter(TM, Ctx);
307 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
308 /// instructions, and rewrite them to their Thumb2 form if we are currently in
310 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
311 unsigned EncodedValue) const {
312 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
313 if (Subtarget.isThumb2()) {
314 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
315 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
317 unsigned Bit24 = EncodedValue & 0x01000000;
318 unsigned Bit28 = Bit24 << 4;
319 EncodedValue &= 0xEFFFFFFF;
320 EncodedValue |= Bit28;
321 EncodedValue |= 0x0F000000;
327 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
328 /// instructions, and rewrite them to their Thumb2 form if we are currently in
330 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
331 unsigned EncodedValue) const {
332 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
333 if (Subtarget.isThumb2()) {
334 EncodedValue &= 0xF0FFFFFF;
335 EncodedValue |= 0x09000000;
341 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
342 /// instructions, and rewrite them to their Thumb2 form if we are currently in
344 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
345 unsigned EncodedValue) const {
346 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
347 if (Subtarget.isThumb2()) {
348 EncodedValue &= 0x00FFFFFF;
349 EncodedValue |= 0xEE000000;
355 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
356 /// them to their Thumb2 form if we are currently in Thumb2 mode.
357 unsigned ARMMCCodeEmitter::
358 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
359 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
360 EncodedValue &= 0x0FFFFFFF;
361 EncodedValue |= 0xE0000000;
366 /// getMachineOpValue - Return binary encoding of operand. If the machine
367 /// operand requires relocation, record the relocation and return zero.
368 unsigned ARMMCCodeEmitter::
369 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
370 SmallVectorImpl<MCFixup> &Fixups) const {
372 unsigned Reg = MO.getReg();
373 unsigned RegNo = getARMRegisterNumbering(Reg);
375 // Q registers are encoded as 2x their register number.
379 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
380 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
381 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
382 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
385 } else if (MO.isImm()) {
386 return static_cast<unsigned>(MO.getImm());
387 } else if (MO.isFPImm()) {
388 return static_cast<unsigned>(APFloat(MO.getFPImm())
389 .bitcastToAPInt().getHiBits(32).getLimitedValue());
392 llvm_unreachable("Unable to encode MCOperand!");
396 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
397 bool ARMMCCodeEmitter::
398 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
399 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
400 const MCOperand &MO = MI.getOperand(OpIdx);
401 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
403 Reg = getARMRegisterNumbering(MO.getReg());
405 int32_t SImm = MO1.getImm();
408 // Special value for #-0
409 if (SImm == INT32_MIN)
412 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
422 /// getBranchTargetOpValue - Helper function to get the branch target operand,
423 /// which is either an immediate or requires a fixup.
424 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
426 SmallVectorImpl<MCFixup> &Fixups) {
427 const MCOperand &MO = MI.getOperand(OpIdx);
429 // If the destination is an immediate, we have nothing to do.
430 if (MO.isImm()) return MO.getImm();
431 assert(MO.isExpr() && "Unexpected branch target type!");
432 const MCExpr *Expr = MO.getExpr();
433 MCFixupKind Kind = MCFixupKind(FixupKind);
434 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
436 // All of the information is in the fixup.
440 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
441 uint32_t ARMMCCodeEmitter::
442 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
443 SmallVectorImpl<MCFixup> &Fixups) const {
444 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
447 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
448 /// BLX branch target.
449 uint32_t ARMMCCodeEmitter::
450 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
451 SmallVectorImpl<MCFixup> &Fixups) const {
452 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
455 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
456 uint32_t ARMMCCodeEmitter::
457 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
458 SmallVectorImpl<MCFixup> &Fixups) const {
459 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
462 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
464 uint32_t ARMMCCodeEmitter::
465 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
466 SmallVectorImpl<MCFixup> &Fixups) const {
467 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
468 if (Subtarget.isThumb2())
469 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_branch, Fixups);
470 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
473 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
475 uint32_t ARMMCCodeEmitter::
476 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
477 SmallVectorImpl<MCFixup> &Fixups) const {
478 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
479 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
483 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
484 uint32_t ARMMCCodeEmitter::
485 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
486 SmallVectorImpl<MCFixup> &Fixups) const {
488 // {12} = (U)nsigned (add == '1', sub == '0')
492 // If The first operand isn't a register, we have a label reference.
493 const MCOperand &MO = MI.getOperand(OpIdx);
494 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
495 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
496 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
498 isAdd = false ; // 'U' bit is set as part of the fixup.
500 const MCExpr *Expr = 0;
504 Expr = MO2.getExpr();
506 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
508 if (Subtarget.isThumb2())
509 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
511 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
512 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
514 ++MCNumCPRelocations;
516 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
518 uint32_t Binary = Imm12 & 0xfff;
519 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
522 Binary |= (Reg << 13);
526 /// getT2AddrModeImm8s4OpValue - Return encoding info for
527 /// 'reg +/- imm8<<2' operand.
528 uint32_t ARMMCCodeEmitter::
529 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
530 SmallVectorImpl<MCFixup> &Fixups) const {
532 // {12} = (U)nsigned (add == '1', sub == '0')
536 // If The first operand isn't a register, we have a label reference.
537 const MCOperand &MO = MI.getOperand(OpIdx);
539 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
541 isAdd = false ; // 'U' bit is set as part of the fixup.
543 assert(MO.isExpr() && "Unexpected machine operand type!");
544 const MCExpr *Expr = MO.getExpr();
545 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
546 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
548 ++MCNumCPRelocations;
550 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
552 uint32_t Binary = (Imm8 >> 2) & 0xff;
553 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
556 Binary |= (Reg << 9);
560 uint32_t ARMMCCodeEmitter::
561 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
562 SmallVectorImpl<MCFixup> &Fixups) const {
563 // {20-16} = imm{15-12}
564 // {11-0} = imm{11-0}
565 const MCOperand &MO = MI.getOperand(OpIdx);
567 return static_cast<unsigned>(MO.getImm());
568 } else if (const MCSymbolRefExpr *Expr =
569 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
571 switch (Expr->getKind()) {
572 default: assert(0 && "Unsupported ARMFixup");
573 case MCSymbolRefExpr::VK_ARM_HI16:
574 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
576 case MCSymbolRefExpr::VK_ARM_LO16:
577 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
580 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
583 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
587 uint32_t ARMMCCodeEmitter::
588 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
589 SmallVectorImpl<MCFixup> &Fixups) const {
590 const MCOperand &MO = MI.getOperand(OpIdx);
591 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
592 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
593 unsigned Rn = getARMRegisterNumbering(MO.getReg());
594 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
595 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
596 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
597 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
598 unsigned SBits = getShiftOp(ShOp);
607 uint32_t Binary = Rm;
609 Binary |= SBits << 5;
610 Binary |= ShImm << 7;
616 uint32_t ARMMCCodeEmitter::
617 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
618 SmallVectorImpl<MCFixup> &Fixups) const {
620 // {13} 1 == imm12, 0 == Rm
623 const MCOperand &MO = MI.getOperand(OpIdx);
624 unsigned Rn = getARMRegisterNumbering(MO.getReg());
625 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
630 uint32_t ARMMCCodeEmitter::
631 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
632 SmallVectorImpl<MCFixup> &Fixups) const {
633 // {13} 1 == imm12, 0 == Rm
636 const MCOperand &MO = MI.getOperand(OpIdx);
637 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
638 unsigned Imm = MO1.getImm();
639 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
640 bool isReg = MO.getReg() != 0;
641 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
642 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
644 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
645 Binary <<= 7; // Shift amount is bits [11:7]
646 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
647 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
649 return Binary | (isAdd << 12) | (isReg << 13);
652 uint32_t ARMMCCodeEmitter::
653 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
654 SmallVectorImpl<MCFixup> &Fixups) const {
655 // {9} 1 == imm8, 0 == Rm
659 const MCOperand &MO = MI.getOperand(OpIdx);
660 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
661 unsigned Imm = MO1.getImm();
662 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
663 bool isImm = MO.getReg() == 0;
664 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
665 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
667 Imm8 = getARMRegisterNumbering(MO.getReg());
668 return Imm8 | (isAdd << 8) | (isImm << 9);
671 uint32_t ARMMCCodeEmitter::
672 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
673 SmallVectorImpl<MCFixup> &Fixups) const {
674 // {13} 1 == imm8, 0 == Rm
679 const MCOperand &MO = MI.getOperand(OpIdx);
680 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
681 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
682 unsigned Rn = getARMRegisterNumbering(MO.getReg());
683 unsigned Imm = MO2.getImm();
684 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
685 bool isImm = MO1.getReg() == 0;
686 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
687 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
689 Imm8 = getARMRegisterNumbering(MO1.getReg());
690 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
693 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
694 uint32_t ARMMCCodeEmitter::
695 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
696 SmallVectorImpl<MCFixup> &Fixups) const {
699 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
700 #if 0 // FIXME: This crashes2003-05-14-initialize-string.c
701 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
702 "Unexpected base register!");
704 // The immediate is already shifted for the implicit zeroes, so no change
706 return MO1.getImm() & 0xff;
709 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
710 uint32_t ARMMCCodeEmitter::
711 getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
712 SmallVectorImpl<MCFixup> &) const {
720 const MCOperand &MO = MI.getOperand(OpIdx);
721 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
722 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
723 unsigned Rn = getARMRegisterNumbering(MO.getReg());
724 unsigned Imm5 = MO1.getImm();
726 if (MO2.getReg() != 0)
728 Imm5 = getARMRegisterNumbering(MO2.getReg());
730 return ((Imm5 & 0x1f) << 3) | Rn;
733 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
734 uint32_t ARMMCCodeEmitter::
735 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
736 SmallVectorImpl<MCFixup> &Fixups) const {
737 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
740 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
741 uint32_t ARMMCCodeEmitter::
742 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
743 SmallVectorImpl<MCFixup> &Fixups) const {
745 // {8} = (U)nsigned (add == '1', sub == '0')
749 // If The first operand isn't a register, we have a label reference.
750 const MCOperand &MO = MI.getOperand(OpIdx);
752 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
754 isAdd = false; // 'U' bit is handled as part of the fixup.
756 assert(MO.isExpr() && "Unexpected machine operand type!");
757 const MCExpr *Expr = MO.getExpr();
759 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
760 if (Subtarget.isThumb2())
761 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
763 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
764 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
766 ++MCNumCPRelocations;
768 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
769 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
772 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
773 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
776 Binary |= (Reg << 9);
780 unsigned ARMMCCodeEmitter::
781 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
782 SmallVectorImpl<MCFixup> &Fixups) const {
783 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
784 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
785 // case the imm contains the amount to shift by.
788 // {4} = 1 if reg shift, 0 if imm shift
796 const MCOperand &MO = MI.getOperand(OpIdx);
797 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
798 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
799 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
802 unsigned Binary = getARMRegisterNumbering(MO.getReg());
804 // Encode the shift opcode.
806 unsigned Rs = MO1.getReg();
808 // Set shift operand (bit[7:4]).
813 // RRX - 0110 and bit[11:8] clear.
815 default: llvm_unreachable("Unknown shift opc!");
816 case ARM_AM::lsl: SBits = 0x1; break;
817 case ARM_AM::lsr: SBits = 0x3; break;
818 case ARM_AM::asr: SBits = 0x5; break;
819 case ARM_AM::ror: SBits = 0x7; break;
820 case ARM_AM::rrx: SBits = 0x6; break;
823 // Set shift operand (bit[6:4]).
829 default: llvm_unreachable("Unknown shift opc!");
830 case ARM_AM::lsl: SBits = 0x0; break;
831 case ARM_AM::lsr: SBits = 0x2; break;
832 case ARM_AM::asr: SBits = 0x4; break;
833 case ARM_AM::ror: SBits = 0x6; break;
837 Binary |= SBits << 4;
838 if (SOpc == ARM_AM::rrx)
841 // Encode the shift operation Rs or shift_imm (except rrx).
843 // Encode Rs bit[11:8].
844 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
845 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
848 // Encode shift_imm bit[11:7].
849 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
852 unsigned ARMMCCodeEmitter::
853 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
854 SmallVectorImpl<MCFixup> &Fixups) const {
855 const MCOperand &MO1 = MI.getOperand(OpNum);
856 const MCOperand &MO2 = MI.getOperand(OpNum+1);
857 const MCOperand &MO3 = MI.getOperand(OpNum+2);
859 // Encoded as [Rn, Rm, imm].
860 // FIXME: Needs fixup support.
861 unsigned Value = getARMRegisterNumbering(MO1.getReg());
863 Value |= getARMRegisterNumbering(MO2.getReg());
865 Value |= MO3.getImm();
870 unsigned ARMMCCodeEmitter::
871 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
872 SmallVectorImpl<MCFixup> &Fixups) const {
873 const MCOperand &MO1 = MI.getOperand(OpNum);
874 const MCOperand &MO2 = MI.getOperand(OpNum+1);
876 // FIXME: Needs fixup support.
877 unsigned Value = getARMRegisterNumbering(MO1.getReg());
879 // Even though the immediate is 8 bits long, we need 9 bits in order
880 // to represent the (inverse of the) sign bit.
882 int32_t tmp = (int32_t)MO2.getImm();
886 Value |= 256; // Set the ADD bit
891 unsigned ARMMCCodeEmitter::
892 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
893 SmallVectorImpl<MCFixup> &Fixups) const {
894 const MCOperand &MO1 = MI.getOperand(OpNum);
896 // FIXME: Needs fixup support.
898 int32_t tmp = (int32_t)MO1.getImm();
902 Value |= 256; // Set the ADD bit
907 unsigned ARMMCCodeEmitter::
908 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
909 SmallVectorImpl<MCFixup> &Fixups) const {
910 const MCOperand &MO1 = MI.getOperand(OpNum);
912 // FIXME: Needs fixup support.
914 int32_t tmp = (int32_t)MO1.getImm();
918 Value |= 4096; // Set the ADD bit
923 unsigned ARMMCCodeEmitter::
924 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
925 SmallVectorImpl<MCFixup> &Fixups) const {
926 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
927 // shifted. The second is the amount to shift by.
934 const MCOperand &MO = MI.getOperand(OpIdx);
935 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
936 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
939 unsigned Binary = getARMRegisterNumbering(MO.getReg());
941 // Encode the shift opcode.
943 // Set shift operand (bit[6:4]).
949 default: llvm_unreachable("Unknown shift opc!");
950 case ARM_AM::lsl: SBits = 0x0; break;
951 case ARM_AM::lsr: SBits = 0x2; break;
952 case ARM_AM::asr: SBits = 0x4; break;
953 case ARM_AM::ror: SBits = 0x6; break;
956 Binary |= SBits << 4;
957 if (SOpc == ARM_AM::rrx)
960 // Encode shift_imm bit[11:7].
961 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
964 unsigned ARMMCCodeEmitter::
965 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
966 SmallVectorImpl<MCFixup> &Fixups) const {
967 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
969 const MCOperand &MO = MI.getOperand(Op);
970 uint32_t v = ~MO.getImm();
971 uint32_t lsb = CountTrailingZeros_32(v);
972 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
973 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
974 return lsb | (msb << 5);
977 unsigned ARMMCCodeEmitter::
978 getRegisterListOpValue(const MCInst &MI, unsigned Op,
979 SmallVectorImpl<MCFixup> &Fixups) const {
982 // {7-0} = Number of registers
985 // {15-0} = Bitfield of GPRs.
986 unsigned Reg = MI.getOperand(Op).getReg();
987 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
988 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
992 if (SPRRegs || DPRRegs) {
994 unsigned RegNo = getARMRegisterNumbering(Reg);
995 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
996 Binary |= (RegNo & 0x1f) << 8;
1000 Binary |= NumRegs * 2;
1002 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1003 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1004 Binary |= 1 << RegNo;
1011 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1012 /// with the alignment operand.
1013 unsigned ARMMCCodeEmitter::
1014 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1015 SmallVectorImpl<MCFixup> &Fixups) const {
1016 const MCOperand &Reg = MI.getOperand(Op);
1017 const MCOperand &Imm = MI.getOperand(Op + 1);
1019 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1022 switch (Imm.getImm()) {
1026 case 8: Align = 0x01; break;
1027 case 16: Align = 0x02; break;
1028 case 32: Align = 0x03; break;
1031 return RegNo | (Align << 4);
1034 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1035 /// alignment operand for use in VLD-dup instructions. This is the same as
1036 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1037 /// different for VLD4-dup.
1038 unsigned ARMMCCodeEmitter::
1039 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1040 SmallVectorImpl<MCFixup> &Fixups) const {
1041 const MCOperand &Reg = MI.getOperand(Op);
1042 const MCOperand &Imm = MI.getOperand(Op + 1);
1044 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1047 switch (Imm.getImm()) {
1051 case 8: Align = 0x01; break;
1052 case 16: Align = 0x03; break;
1055 return RegNo | (Align << 4);
1058 unsigned ARMMCCodeEmitter::
1059 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1060 SmallVectorImpl<MCFixup> &Fixups) const {
1061 const MCOperand &MO = MI.getOperand(Op);
1062 if (MO.getReg() == 0) return 0x0D;
1066 void ARMMCCodeEmitter::
1067 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1068 SmallVectorImpl<MCFixup> &Fixups) const {
1069 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1070 // Pseudo instructions don't get encoded.
1071 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1072 uint64_t TSFlags = Desc.TSFlags;
1073 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1076 // Basic size info comes from the TSFlags field.
1077 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1078 default: llvm_unreachable("Unexpected instruction size!");
1079 case ARMII::Size2Bytes: Size = 2; break;
1080 case ARMII::Size4Bytes: Size = 4; break;
1082 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1083 // Thumb 32-bit wide instructions need to be have the high order halfword
1085 if (Subtarget.isThumb() && Size == 4) {
1086 EmitConstant(Binary >> 16, 2, OS);
1087 EmitConstant(Binary & 0xffff, 2, OS);
1089 EmitConstant(Binary, Size, OS);
1090 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1093 #include "ARMGenMCCodeEmitter.inc"