1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
74 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
78 unsigned &Reg, unsigned &Imm,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
83 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
88 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
92 /// operand as needed by load/store instructions.
93 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const;
96 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
97 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const {
99 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
101 default: assert(0 && "Unknown addressing sub-mode!");
102 case ARM_AM::da: return 0;
103 case ARM_AM::ia: return 1;
104 case ARM_AM::db: return 2;
105 case ARM_AM::ib: return 3;
108 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
110 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
112 default: llvm_unreachable("Unknown shift opc!");
113 case ARM_AM::no_shift:
114 case ARM_AM::lsl: return 0;
115 case ARM_AM::lsr: return 1;
116 case ARM_AM::asr: return 2;
118 case ARM_AM::rrx: return 3;
123 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
124 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
128 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
132 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
136 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
140 uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
144 uint32_t getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
145 SmallVectorImpl<MCFixup> &Fixups) const;
147 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
148 uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
149 SmallVectorImpl<MCFixup> &Fixups) const;
151 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
152 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups) const;
155 /// getCCOutOpValue - Return encoding of the 's' bit.
156 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
157 SmallVectorImpl<MCFixup> &Fixups) const {
158 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
160 return MI.getOperand(Op).getReg() == ARM::CPSR;
163 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
164 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
165 SmallVectorImpl<MCFixup> &Fixups) const {
166 unsigned SoImm = MI.getOperand(Op).getImm();
167 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
168 assert(SoImmVal != -1 && "Not a valid so_imm value!");
170 // Encode rotate_imm.
171 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
172 << ARMII::SoRotImmShift;
175 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
179 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
180 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
181 SmallVectorImpl<MCFixup> &Fixups) const {
182 unsigned SoImm = MI.getOperand(Op).getImm();
183 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
184 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
188 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
189 SmallVectorImpl<MCFixup> &Fixups) const;
190 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
191 SmallVectorImpl<MCFixup> &Fixups) const;
192 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
193 SmallVectorImpl<MCFixup> &Fixups) const;
194 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
195 SmallVectorImpl<MCFixup> &Fixups) const;
197 /// getSORegOpValue - Return an encoded so_reg shifted register value.
198 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
199 SmallVectorImpl<MCFixup> &Fixups) const;
200 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
201 SmallVectorImpl<MCFixup> &Fixups) const;
203 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
204 SmallVectorImpl<MCFixup> &Fixups) const {
205 switch (MI.getOperand(Op).getImm()) {
206 default: assert (0 && "Not a valid rot_imm value!");
214 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
215 SmallVectorImpl<MCFixup> &Fixups) const {
216 return MI.getOperand(Op).getImm() - 1;
219 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
220 SmallVectorImpl<MCFixup> &Fixups) const {
221 return 64 - MI.getOperand(Op).getImm();
224 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
225 SmallVectorImpl<MCFixup> &Fixups) const;
227 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
228 SmallVectorImpl<MCFixup> &Fixups) const;
229 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
230 SmallVectorImpl<MCFixup> &Fixups) const;
231 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
232 SmallVectorImpl<MCFixup> &Fixups) const;
233 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
234 SmallVectorImpl<MCFixup> &Fixups) const;
236 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
237 unsigned EncodedValue) const;
238 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
239 unsigned EncodedValue) const;
240 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
241 unsigned EncodedValue) const;
243 void EmitByte(unsigned char C, raw_ostream &OS) const {
247 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
248 // Output the constant in little endian byte order.
249 for (unsigned i = 0; i != Size; ++i) {
250 EmitByte(Val & 255, OS);
255 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
256 SmallVectorImpl<MCFixup> &Fixups) const;
259 } // end anonymous namespace
261 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
263 return new ARMMCCodeEmitter(TM, Ctx);
266 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
267 /// instructions, and rewrite them to their Thumb2 form if we are currently in
269 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
270 unsigned EncodedValue) const {
271 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
272 if (Subtarget.isThumb2()) {
273 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
274 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
276 unsigned Bit24 = EncodedValue & 0x01000000;
277 unsigned Bit28 = Bit24 << 4;
278 EncodedValue &= 0xEFFFFFFF;
279 EncodedValue |= Bit28;
280 EncodedValue |= 0x0F000000;
286 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
287 /// instructions, and rewrite them to their Thumb2 form if we are currently in
289 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
290 unsigned EncodedValue) const {
291 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
292 if (Subtarget.isThumb2()) {
293 EncodedValue &= 0xF0FFFFFF;
294 EncodedValue |= 0x09000000;
300 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
301 /// instructions, and rewrite them to their Thumb2 form if we are currently in
303 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
304 unsigned EncodedValue) const {
305 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
306 if (Subtarget.isThumb2()) {
307 EncodedValue &= 0x00FFFFFF;
308 EncodedValue |= 0xEE000000;
316 /// getMachineOpValue - Return binary encoding of operand. If the machine
317 /// operand requires relocation, record the relocation and return zero.
318 unsigned ARMMCCodeEmitter::
319 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
320 SmallVectorImpl<MCFixup> &Fixups) const {
322 unsigned Reg = MO.getReg();
323 unsigned RegNo = getARMRegisterNumbering(Reg);
325 // Q registers are encodes as 2x their register number.
329 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
330 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
331 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
332 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
335 } else if (MO.isImm()) {
336 return static_cast<unsigned>(MO.getImm());
337 } else if (MO.isFPImm()) {
338 return static_cast<unsigned>(APFloat(MO.getFPImm())
339 .bitcastToAPInt().getHiBits(32).getLimitedValue());
342 llvm_unreachable("Unable to encode MCOperand!");
346 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
347 bool ARMMCCodeEmitter::
348 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
349 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
350 const MCOperand &MO = MI.getOperand(OpIdx);
351 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
353 Reg = getARMRegisterNumbering(MO.getReg());
355 int32_t SImm = MO1.getImm();
358 // Special value for #-0
359 if (SImm == INT32_MIN)
362 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
372 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
374 uint32_t ARMMCCodeEmitter::
375 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
376 SmallVectorImpl<MCFixup> &Fixups) const {
377 const MCOperand &MO = MI.getOperand(OpIdx);
379 // If the destination is an immediate, we have nothing to do.
380 if (MO.isImm()) return MO.getImm();
381 assert (MO.isExpr() && "Unexpected branch target type!");
382 const MCExpr *Expr = MO.getExpr();
383 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
384 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
386 // All of the information is in the fixup.
390 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
391 uint32_t ARMMCCodeEmitter::
392 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
393 SmallVectorImpl<MCFixup> &Fixups) const {
395 // {12} = (U)nsigned (add == '1', sub == '0')
399 // If The first operand isn't a register, we have a label reference.
400 const MCOperand &MO = MI.getOperand(OpIdx);
402 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
404 isAdd = false ; // 'U' bit is set as part of the fixup.
406 assert(MO.isExpr() && "Unexpected machine operand type!");
407 const MCExpr *Expr = MO.getExpr();
408 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
409 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
411 ++MCNumCPRelocations;
413 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
415 uint32_t Binary = Imm12 & 0xfff;
416 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
419 Binary |= (Reg << 13);
423 uint32_t ARMMCCodeEmitter::
424 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
425 SmallVectorImpl<MCFixup> &Fixups) const {
426 // {20-16} = imm{15-12}
427 // {11-0} = imm{11-0}
428 const MCOperand &MO = MI.getOperand(OpIdx);
430 return static_cast<unsigned>(MO.getImm());
431 } else if (const MCSymbolRefExpr *Expr =
432 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
434 switch (Expr->getKind()) {
435 default: assert(0 && "Unsupported ARMFixup");
436 case MCSymbolRefExpr::VK_ARM_HI16:
437 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
439 case MCSymbolRefExpr::VK_ARM_LO16:
440 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
443 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
446 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
450 uint32_t ARMMCCodeEmitter::
451 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
452 SmallVectorImpl<MCFixup> &Fixups) const {
453 const MCOperand &MO = MI.getOperand(OpIdx);
454 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
455 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
456 unsigned Rn = getARMRegisterNumbering(MO.getReg());
457 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
458 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
459 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
460 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
461 unsigned SBits = getShiftOp(ShOp);
470 uint32_t Binary = Rm;
472 Binary |= SBits << 5;
473 Binary |= ShImm << 7;
479 uint32_t ARMMCCodeEmitter::
480 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
481 SmallVectorImpl<MCFixup> &Fixups) const {
483 // {13} 1 == imm12, 0 == Rm
486 const MCOperand &MO = MI.getOperand(OpIdx);
487 unsigned Rn = getARMRegisterNumbering(MO.getReg());
488 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
493 uint32_t ARMMCCodeEmitter::
494 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
495 SmallVectorImpl<MCFixup> &Fixups) const {
496 // {13} 1 == imm12, 0 == Rm
499 const MCOperand &MO = MI.getOperand(OpIdx);
500 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
501 unsigned Imm = MO1.getImm();
502 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
503 bool isReg = MO.getReg() != 0;
504 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
505 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
507 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
508 Binary <<= 7; // Shift amount is bits [11:7]
509 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
510 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
512 return Binary | (isAdd << 12) | (isReg << 13);
515 uint32_t ARMMCCodeEmitter::
516 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
517 SmallVectorImpl<MCFixup> &Fixups) const {
518 // {9} 1 == imm8, 0 == Rm
522 const MCOperand &MO = MI.getOperand(OpIdx);
523 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
524 unsigned Imm = MO1.getImm();
525 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
526 bool isImm = MO.getReg() == 0;
527 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
528 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
530 Imm8 = getARMRegisterNumbering(MO.getReg());
531 return Imm8 | (isAdd << 8) | (isImm << 9);
534 uint32_t ARMMCCodeEmitter::
535 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
536 SmallVectorImpl<MCFixup> &Fixups) const {
537 // {13} 1 == imm8, 0 == Rm
542 const MCOperand &MO = MI.getOperand(OpIdx);
543 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
544 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
545 unsigned Rn = getARMRegisterNumbering(MO.getReg());
546 unsigned Imm = MO2.getImm();
547 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
548 bool isImm = MO1.getReg() == 0;
549 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
550 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
552 Imm8 = getARMRegisterNumbering(MO1.getReg());
553 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
556 /// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
557 static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
566 const MCOperand &MO = MI.getOperand(OpIdx);
567 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
568 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
569 unsigned Rn = getARMRegisterNumbering(MO.getReg());
570 unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
571 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
572 return (Rm << 3) | (Imm5 << 3) | Rn;
575 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
576 uint32_t ARMMCCodeEmitter::
577 getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
578 SmallVectorImpl<MCFixup> &) const {
579 return getAddrModeSOpValue(MI, OpIdx, 4);
582 /// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
583 uint32_t ARMMCCodeEmitter::
584 getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
585 SmallVectorImpl<MCFixup> &) const {
586 return getAddrModeSOpValue(MI, OpIdx, 2);
589 /// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
590 uint32_t ARMMCCodeEmitter::
591 getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
592 SmallVectorImpl<MCFixup> &) const {
593 return getAddrModeSOpValue(MI, OpIdx, 1);
596 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
597 uint32_t ARMMCCodeEmitter::
598 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
599 SmallVectorImpl<MCFixup> &Fixups) const {
601 // {8} = (U)nsigned (add == '1', sub == '0')
605 // If The first operand isn't a register, we have a label reference.
606 const MCOperand &MO = MI.getOperand(OpIdx);
608 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
610 isAdd = false; // 'U' bit is handled as part of the fixup.
612 assert(MO.isExpr() && "Unexpected machine operand type!");
613 const MCExpr *Expr = MO.getExpr();
614 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
615 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
617 ++MCNumCPRelocations;
619 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
620 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
623 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
624 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
627 Binary |= (Reg << 9);
631 unsigned ARMMCCodeEmitter::
632 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
633 SmallVectorImpl<MCFixup> &Fixups) const {
634 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
635 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
636 // case the imm contains the amount to shift by.
639 // {4} = 1 if reg shift, 0 if imm shift
647 const MCOperand &MO = MI.getOperand(OpIdx);
648 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
649 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
650 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
653 unsigned Binary = getARMRegisterNumbering(MO.getReg());
655 // Encode the shift opcode.
657 unsigned Rs = MO1.getReg();
659 // Set shift operand (bit[7:4]).
664 // RRX - 0110 and bit[11:8] clear.
666 default: llvm_unreachable("Unknown shift opc!");
667 case ARM_AM::lsl: SBits = 0x1; break;
668 case ARM_AM::lsr: SBits = 0x3; break;
669 case ARM_AM::asr: SBits = 0x5; break;
670 case ARM_AM::ror: SBits = 0x7; break;
671 case ARM_AM::rrx: SBits = 0x6; break;
674 // Set shift operand (bit[6:4]).
680 default: llvm_unreachable("Unknown shift opc!");
681 case ARM_AM::lsl: SBits = 0x0; break;
682 case ARM_AM::lsr: SBits = 0x2; break;
683 case ARM_AM::asr: SBits = 0x4; break;
684 case ARM_AM::ror: SBits = 0x6; break;
688 Binary |= SBits << 4;
689 if (SOpc == ARM_AM::rrx)
692 // Encode the shift operation Rs or shift_imm (except rrx).
694 // Encode Rs bit[11:8].
695 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
696 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
699 // Encode shift_imm bit[11:7].
700 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
703 unsigned ARMMCCodeEmitter::
704 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
705 SmallVectorImpl<MCFixup> &Fixups) const {
706 const MCOperand &MO1 = MI.getOperand(OpNum);
707 const MCOperand &MO2 = MI.getOperand(OpNum+1);
708 const MCOperand &MO3 = MI.getOperand(OpNum+2);
710 // Encoded as [Rn, Rm, imm].
711 // FIXME: Needs fixup support.
712 unsigned Value = getARMRegisterNumbering(MO1.getReg());
714 Value |= getARMRegisterNumbering(MO2.getReg());
716 Value |= MO3.getImm();
721 unsigned ARMMCCodeEmitter::
722 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
723 SmallVectorImpl<MCFixup> &Fixups) const {
724 const MCOperand &MO1 = MI.getOperand(OpNum);
725 const MCOperand &MO2 = MI.getOperand(OpNum+1);
727 // FIXME: Needs fixup support.
728 unsigned Value = getARMRegisterNumbering(MO1.getReg());
730 // Even though the immediate is 8 bits long, we need 9 bits in order
731 // to represent the (inverse of the) sign bit.
733 int32_t tmp = (int32_t)MO2.getImm();
737 Value |= 256; // Set the ADD bit
742 unsigned ARMMCCodeEmitter::
743 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
744 SmallVectorImpl<MCFixup> &Fixups) const {
745 const MCOperand &MO1 = MI.getOperand(OpNum);
747 // FIXME: Needs fixup support.
749 int32_t tmp = (int32_t)MO1.getImm();
753 Value |= 256; // Set the ADD bit
758 unsigned ARMMCCodeEmitter::
759 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
760 SmallVectorImpl<MCFixup> &Fixups) const {
761 const MCOperand &MO1 = MI.getOperand(OpNum);
763 // FIXME: Needs fixup support.
765 int32_t tmp = (int32_t)MO1.getImm();
769 Value |= 4096; // Set the ADD bit
774 unsigned ARMMCCodeEmitter::
775 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
776 SmallVectorImpl<MCFixup> &Fixups) const {
777 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
778 // shifted. The second is the amount to shift by.
785 const MCOperand &MO = MI.getOperand(OpIdx);
786 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
787 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
790 unsigned Binary = getARMRegisterNumbering(MO.getReg());
792 // Encode the shift opcode.
794 // Set shift operand (bit[6:4]).
800 default: llvm_unreachable("Unknown shift opc!");
801 case ARM_AM::lsl: SBits = 0x0; break;
802 case ARM_AM::lsr: SBits = 0x2; break;
803 case ARM_AM::asr: SBits = 0x4; break;
804 case ARM_AM::ror: SBits = 0x6; break;
807 Binary |= SBits << 4;
808 if (SOpc == ARM_AM::rrx)
811 // Encode shift_imm bit[11:7].
812 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
815 unsigned ARMMCCodeEmitter::
816 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
817 SmallVectorImpl<MCFixup> &Fixups) const {
818 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
820 const MCOperand &MO = MI.getOperand(Op);
821 uint32_t v = ~MO.getImm();
822 uint32_t lsb = CountTrailingZeros_32(v);
823 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
824 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
825 return lsb | (msb << 5);
828 unsigned ARMMCCodeEmitter::
829 getRegisterListOpValue(const MCInst &MI, unsigned Op,
830 SmallVectorImpl<MCFixup> &Fixups) const {
833 // {7-0} = Number of registers
836 // {15-0} = Bitfield of GPRs.
837 unsigned Reg = MI.getOperand(Op).getReg();
838 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
839 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
843 if (SPRRegs || DPRRegs) {
845 unsigned RegNo = getARMRegisterNumbering(Reg);
846 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
847 Binary |= (RegNo & 0x1f) << 8;
851 Binary |= NumRegs * 2;
853 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
854 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
855 Binary |= 1 << RegNo;
862 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
863 /// with the alignment operand.
864 unsigned ARMMCCodeEmitter::
865 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
866 SmallVectorImpl<MCFixup> &Fixups) const {
867 const MCOperand &Reg = MI.getOperand(Op);
868 const MCOperand &Imm = MI.getOperand(Op + 1);
870 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
873 switch (Imm.getImm()) {
877 case 8: Align = 0x01; break;
878 case 16: Align = 0x02; break;
879 case 32: Align = 0x03; break;
882 return RegNo | (Align << 4);
885 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
886 /// alignment operand for use in VLD-dup instructions. This is the same as
887 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
888 /// different for VLD4-dup.
889 unsigned ARMMCCodeEmitter::
890 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
891 SmallVectorImpl<MCFixup> &Fixups) const {
892 const MCOperand &Reg = MI.getOperand(Op);
893 const MCOperand &Imm = MI.getOperand(Op + 1);
895 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
898 switch (Imm.getImm()) {
902 case 8: Align = 0x01; break;
903 case 16: Align = 0x03; break;
906 return RegNo | (Align << 4);
909 unsigned ARMMCCodeEmitter::
910 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
911 SmallVectorImpl<MCFixup> &Fixups) const {
912 const MCOperand &MO = MI.getOperand(Op);
913 if (MO.getReg() == 0) return 0x0D;
917 void ARMMCCodeEmitter::
918 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
919 SmallVectorImpl<MCFixup> &Fixups) const {
920 // Pseudo instructions don't get encoded.
921 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
922 uint64_t TSFlags = Desc.TSFlags;
923 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
926 // Basic size info comes from the TSFlags field.
927 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
928 default: llvm_unreachable("Unexpected instruction size!");
929 case ARMII::Size2Bytes: Size = 2; break;
930 case ARMII::Size4Bytes: Size = 4; break;
932 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
933 ++MCNumEmitted; // Keep track of the # of mi's emitted.
936 #include "ARMGenMCCodeEmitter.inc"