1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
74 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
78 unsigned &Reg, unsigned &Imm,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
83 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
88 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
92 /// operand as needed by load/store instructions.
93 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const;
96 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
97 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const {
99 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
101 default: assert(0 && "Unknown addressing sub-mode!");
102 case ARM_AM::da: return 0;
103 case ARM_AM::ia: return 1;
104 case ARM_AM::db: return 2;
105 case ARM_AM::ib: return 3;
108 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
110 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
112 default: llvm_unreachable("Unknown shift opc!");
113 case ARM_AM::no_shift:
114 case ARM_AM::lsl: return 0;
115 case ARM_AM::lsr: return 1;
116 case ARM_AM::asr: return 2;
118 case ARM_AM::rrx: return 3;
123 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
124 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
128 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
132 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
136 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
140 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getCCOutOpValue - Return encoding of the 's' bit.
144 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
145 SmallVectorImpl<MCFixup> &Fixups) const {
146 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
148 return MI.getOperand(Op).getReg() == ARM::CPSR;
151 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
152 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
153 SmallVectorImpl<MCFixup> &Fixups) const {
154 unsigned SoImm = MI.getOperand(Op).getImm();
155 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
156 assert(SoImmVal != -1 && "Not a valid so_imm value!");
158 // Encode rotate_imm.
159 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
160 << ARMII::SoRotImmShift;
163 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
167 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
168 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 unsigned SoImm = MI.getOperand(Op).getImm();
171 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
172 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
176 /// getSORegOpValue - Return an encoded so_reg shifted register value.
177 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
178 SmallVectorImpl<MCFixup> &Fixups) const;
179 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
180 SmallVectorImpl<MCFixup> &Fixups) const;
182 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
183 SmallVectorImpl<MCFixup> &Fixups) const {
184 switch (MI.getOperand(Op).getImm()) {
185 default: assert (0 && "Not a valid rot_imm value!");
193 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
194 SmallVectorImpl<MCFixup> &Fixups) const {
195 return MI.getOperand(Op).getImm() - 1;
198 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
199 SmallVectorImpl<MCFixup> &Fixups) const {
200 return 64 - MI.getOperand(Op).getImm();
203 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
204 SmallVectorImpl<MCFixup> &Fixups) const;
206 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
207 SmallVectorImpl<MCFixup> &Fixups) const;
208 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
209 SmallVectorImpl<MCFixup> &Fixups) const;
210 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
211 SmallVectorImpl<MCFixup> &Fixups) const;
213 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
214 unsigned EncodedValue) const;
215 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
216 unsigned EncodedValue) const;
217 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
218 unsigned EncodedValue) const;
220 void EmitByte(unsigned char C, raw_ostream &OS) const {
224 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
225 // Output the constant in little endian byte order.
226 for (unsigned i = 0; i != Size; ++i) {
227 EmitByte(Val & 255, OS);
232 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
233 SmallVectorImpl<MCFixup> &Fixups) const;
236 } // end anonymous namespace
238 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
240 return new ARMMCCodeEmitter(TM, Ctx);
243 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
244 /// instructions, and rewrite them to their Thumb2 form if we are currently in
246 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
247 unsigned EncodedValue) const {
248 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
249 if (Subtarget.isThumb2()) {
250 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
251 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
253 unsigned Bit24 = EncodedValue & 0x01000000;
254 unsigned Bit28 = Bit24 << 4;
255 EncodedValue &= 0xEFFFFFFF;
256 EncodedValue |= Bit28;
257 EncodedValue |= 0x0F000000;
263 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
264 /// instructions, and rewrite them to their Thumb2 form if we are currently in
266 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
267 unsigned EncodedValue) const {
268 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
269 if (Subtarget.isThumb2()) {
270 EncodedValue &= 0xF0FFFFFF;
271 EncodedValue |= 0x09000000;
277 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
278 /// instructions, and rewrite them to their Thumb2 form if we are currently in
280 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
281 unsigned EncodedValue) const {
282 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
283 if (Subtarget.isThumb2()) {
284 EncodedValue &= 0x00FFFFFF;
285 EncodedValue |= 0xEE000000;
293 /// getMachineOpValue - Return binary encoding of operand. If the machine
294 /// operand requires relocation, record the relocation and return zero.
295 unsigned ARMMCCodeEmitter::
296 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
297 SmallVectorImpl<MCFixup> &Fixups) const {
299 unsigned Reg = MO.getReg();
300 unsigned RegNo = getARMRegisterNumbering(Reg);
302 // Q registers are encodes as 2x their register number.
306 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
307 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
308 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
309 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
312 } else if (MO.isImm()) {
313 return static_cast<unsigned>(MO.getImm());
314 } else if (MO.isFPImm()) {
315 return static_cast<unsigned>(APFloat(MO.getFPImm())
316 .bitcastToAPInt().getHiBits(32).getLimitedValue());
319 llvm_unreachable("Unable to encode MCOperand!");
323 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
324 bool ARMMCCodeEmitter::
325 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
326 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
327 const MCOperand &MO = MI.getOperand(OpIdx);
328 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
330 Reg = getARMRegisterNumbering(MO.getReg());
332 int32_t SImm = MO1.getImm();
335 // Special value for #-0
336 if (SImm == INT32_MIN)
339 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
349 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
351 uint32_t ARMMCCodeEmitter::
352 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
353 SmallVectorImpl<MCFixup> &Fixups) const {
354 const MCOperand &MO = MI.getOperand(OpIdx);
356 // If the destination is an immediate, we have nothing to do.
357 if (MO.isImm()) return MO.getImm();
358 assert (MO.isExpr() && "Unexpected branch target type!");
359 const MCExpr *Expr = MO.getExpr();
360 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
361 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
363 // All of the information is in the fixup.
367 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
368 uint32_t ARMMCCodeEmitter::
369 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
370 SmallVectorImpl<MCFixup> &Fixups) const {
372 // {12} = (U)nsigned (add == '1', sub == '0')
376 // If The first operand isn't a register, we have a label reference.
377 const MCOperand &MO = MI.getOperand(OpIdx);
379 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
382 assert(MO.isExpr() && "Unexpected machine operand type!");
383 const MCExpr *Expr = MO.getExpr();
384 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
385 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
387 ++MCNumCPRelocations;
389 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
391 uint32_t Binary = Imm12 & 0xfff;
392 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
395 Binary |= (Reg << 13);
399 uint32_t ARMMCCodeEmitter::
400 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
401 SmallVectorImpl<MCFixup> &Fixups) const {
402 // {20-16} = imm{15-12}
403 // {11-0} = imm{11-0}
404 const MCOperand &MO = MI.getOperand(OpIdx);
406 return static_cast<unsigned>(MO.getImm());
407 } else if (const MCSymbolRefExpr *Expr =
408 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
410 switch (Expr->getKind()) {
411 default: assert(0 && "Unsupported ARMFixup");
412 case MCSymbolRefExpr::VK_ARM_HI16:
413 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
415 case MCSymbolRefExpr::VK_ARM_LO16:
416 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
419 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
422 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
426 uint32_t ARMMCCodeEmitter::
427 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
428 SmallVectorImpl<MCFixup> &Fixups) const {
429 const MCOperand &MO = MI.getOperand(OpIdx);
430 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
431 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
432 unsigned Rn = getARMRegisterNumbering(MO.getReg());
433 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
434 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
435 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
436 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
437 unsigned SBits = getShiftOp(ShOp);
446 uint32_t Binary = Rm;
448 Binary |= SBits << 5;
449 Binary |= ShImm << 7;
455 uint32_t ARMMCCodeEmitter::
456 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
457 SmallVectorImpl<MCFixup> &Fixups) const {
459 // {13} 1 == imm12, 0 == Rm
462 const MCOperand &MO = MI.getOperand(OpIdx);
463 unsigned Rn = getARMRegisterNumbering(MO.getReg());
464 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
469 uint32_t ARMMCCodeEmitter::
470 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
471 SmallVectorImpl<MCFixup> &Fixups) const {
472 // {13} 1 == imm12, 0 == Rm
475 const MCOperand &MO = MI.getOperand(OpIdx);
476 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
477 unsigned Imm = MO1.getImm();
478 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
479 bool isReg = MO.getReg() != 0;
480 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
481 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
483 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
484 Binary <<= 7; // Shift amount is bits [11:7]
485 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
486 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
488 return Binary | (isAdd << 12) | (isReg << 13);
491 uint32_t ARMMCCodeEmitter::
492 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
493 SmallVectorImpl<MCFixup> &Fixups) const {
494 // {9} 1 == imm8, 0 == Rm
498 const MCOperand &MO = MI.getOperand(OpIdx);
499 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
500 unsigned Imm = MO1.getImm();
501 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
502 bool isImm = MO.getReg() == 0;
503 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
504 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
506 Imm8 = getARMRegisterNumbering(MO.getReg());
507 return Imm8 | (isAdd << 8) | (isImm << 9);
510 uint32_t ARMMCCodeEmitter::
511 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
512 SmallVectorImpl<MCFixup> &Fixups) const {
513 // {13} 1 == imm8, 0 == Rm
518 const MCOperand &MO = MI.getOperand(OpIdx);
519 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
520 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
521 unsigned Rn = getARMRegisterNumbering(MO.getReg());
522 unsigned Imm = MO2.getImm();
523 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
524 bool isImm = MO1.getReg() == 0;
525 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
526 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
528 Imm8 = getARMRegisterNumbering(MO1.getReg());
529 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
532 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
533 uint32_t ARMMCCodeEmitter::
534 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
535 SmallVectorImpl<MCFixup> &Fixups) const {
537 // {8} = (U)nsigned (add == '1', sub == '0')
540 // If The first operand isn't a register, we have a label reference.
541 const MCOperand &MO = MI.getOperand(OpIdx);
543 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
546 assert(MO.isExpr() && "Unexpected machine operand type!");
547 const MCExpr *Expr = MO.getExpr();
548 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
549 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
551 ++MCNumCPRelocations;
553 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
555 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
556 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
557 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
559 Binary |= (Reg << 9);
563 unsigned ARMMCCodeEmitter::
564 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
565 SmallVectorImpl<MCFixup> &Fixups) const {
566 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
567 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
568 // case the imm contains the amount to shift by.
571 // {4} = 1 if reg shift, 0 if imm shift
579 const MCOperand &MO = MI.getOperand(OpIdx);
580 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
581 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
582 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
585 unsigned Binary = getARMRegisterNumbering(MO.getReg());
587 // Encode the shift opcode.
589 unsigned Rs = MO1.getReg();
591 // Set shift operand (bit[7:4]).
596 // RRX - 0110 and bit[11:8] clear.
598 default: llvm_unreachable("Unknown shift opc!");
599 case ARM_AM::lsl: SBits = 0x1; break;
600 case ARM_AM::lsr: SBits = 0x3; break;
601 case ARM_AM::asr: SBits = 0x5; break;
602 case ARM_AM::ror: SBits = 0x7; break;
603 case ARM_AM::rrx: SBits = 0x6; break;
606 // Set shift operand (bit[6:4]).
612 default: llvm_unreachable("Unknown shift opc!");
613 case ARM_AM::lsl: SBits = 0x0; break;
614 case ARM_AM::lsr: SBits = 0x2; break;
615 case ARM_AM::asr: SBits = 0x4; break;
616 case ARM_AM::ror: SBits = 0x6; break;
620 Binary |= SBits << 4;
621 if (SOpc == ARM_AM::rrx)
624 // Encode the shift operation Rs or shift_imm (except rrx).
626 // Encode Rs bit[11:8].
627 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
628 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
631 // Encode shift_imm bit[11:7].
632 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
635 unsigned ARMMCCodeEmitter::
636 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
637 SmallVectorImpl<MCFixup> &Fixups) const {
638 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
639 // shifted. The second is the amount to shift by.
646 const MCOperand &MO = MI.getOperand(OpIdx);
647 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
648 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
651 unsigned Binary = getARMRegisterNumbering(MO.getReg());
653 // Encode the shift opcode.
655 // Set shift operand (bit[6:4]).
661 default: llvm_unreachable("Unknown shift opc!");
662 case ARM_AM::lsl: SBits = 0x0; break;
663 case ARM_AM::lsr: SBits = 0x2; break;
664 case ARM_AM::asr: SBits = 0x4; break;
665 case ARM_AM::ror: SBits = 0x6; break;
668 Binary |= SBits << 4;
669 if (SOpc == ARM_AM::rrx)
672 // Encode shift_imm bit[11:7].
673 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
676 unsigned ARMMCCodeEmitter::
677 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
678 SmallVectorImpl<MCFixup> &Fixups) const {
679 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
681 const MCOperand &MO = MI.getOperand(Op);
682 uint32_t v = ~MO.getImm();
683 uint32_t lsb = CountTrailingZeros_32(v);
684 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
685 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
686 return lsb | (msb << 5);
689 unsigned ARMMCCodeEmitter::
690 getRegisterListOpValue(const MCInst &MI, unsigned Op,
691 SmallVectorImpl<MCFixup> &Fixups) const {
694 // {7-0} = Number of registers
697 // {15-0} = Bitfield of GPRs.
698 unsigned Reg = MI.getOperand(Op).getReg();
699 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
700 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
704 if (SPRRegs || DPRRegs) {
706 unsigned RegNo = getARMRegisterNumbering(Reg);
707 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
708 Binary |= (RegNo & 0x1f) << 8;
712 Binary |= NumRegs * 2;
714 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
715 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
716 Binary |= 1 << RegNo;
723 unsigned ARMMCCodeEmitter::
724 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
725 SmallVectorImpl<MCFixup> &Fixups) const {
726 const MCOperand &Reg = MI.getOperand(Op);
727 const MCOperand &Imm = MI.getOperand(Op + 1);
729 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
732 switch (Imm.getImm()) {
736 case 8: Align = 0x01; break;
737 case 16: Align = 0x02; break;
738 case 32: Align = 0x03; break;
741 return RegNo | (Align << 4);
744 unsigned ARMMCCodeEmitter::
745 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
746 SmallVectorImpl<MCFixup> &Fixups) const {
747 const MCOperand &MO = MI.getOperand(Op);
748 if (MO.getReg() == 0) return 0x0D;
752 void ARMMCCodeEmitter::
753 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
754 SmallVectorImpl<MCFixup> &Fixups) const {
755 // Pseudo instructions don't get encoded.
756 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
757 uint64_t TSFlags = Desc.TSFlags;
758 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
761 // Basic size info comes from the TSFlags field.
762 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
763 default: llvm_unreachable("Unexpected instruction size!");
764 case ARMII::Size2Bytes: Size = 2; break;
765 case ARMII::Size4Bytes: Size = 4; break;
767 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
768 ++MCNumEmitted; // Keep track of the # of mi's emitted.
771 #include "ARMGenMCCodeEmitter.inc"