1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // This table *must* be in the order that the fixup_* kinds are defined in
51 // Name Offset (bits) Size (bits) Flags
52 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
53 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
54 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
55 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
56 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
57 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
58 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
59 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
60 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
61 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
62 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
63 { "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
64 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
65 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
66 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
67 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
68 { "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
69 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
70 { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
71 { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
72 { "fixup_arm_movt_hi16", 0, 16, 0 },
73 { "fixup_arm_movw_lo16", 0, 16, 0 },
76 if (Kind < FirstTargetFixupKind)
77 return MCCodeEmitter::getFixupKindInfo(Kind);
79 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
81 return Infos[Kind - FirstTargetFixupKind];
83 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
85 // getBinaryCodeForInstr - TableGen'erated function for getting the
86 // binary encoding for an instruction.
87 unsigned getBinaryCodeForInstr(const MCInst &MI,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 /// getMachineOpValue - Return binary encoding of operand. If the machine
91 /// operand requires relocation, record the relocation and return zero.
92 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
93 SmallVectorImpl<MCFixup> &Fixups) const;
95 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
96 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
100 unsigned &Reg, unsigned &Imm,
101 SmallVectorImpl<MCFixup> &Fixups) const;
103 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
104 /// BL branch target.
105 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 SmallVectorImpl<MCFixup> &Fixups) const;
108 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109 /// BLX branch target.
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
114 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
118 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 SmallVectorImpl<MCFixup> &Fixups) const;
121 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
122 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
123 SmallVectorImpl<MCFixup> &Fixups) const;
125 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
127 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
128 SmallVectorImpl<MCFixup> &Fixups) const;
130 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
131 /// immediate Thumb2 direct branch target.
132 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
136 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
137 /// ADR label target.
138 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
139 SmallVectorImpl<MCFixup> &Fixups) const;
140 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
142 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
143 SmallVectorImpl<MCFixup> &Fixups) const;
146 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
148 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
149 SmallVectorImpl<MCFixup> &Fixups) const;
151 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
152 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
153 SmallVectorImpl<MCFixup> &Fixups)const;
155 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
157 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
158 SmallVectorImpl<MCFixup> &Fixups) const;
161 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
162 /// operand as needed by load/store instructions.
163 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
164 SmallVectorImpl<MCFixup> &Fixups) const;
166 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
167 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups) const {
169 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
171 default: assert(0 && "Unknown addressing sub-mode!");
172 case ARM_AM::da: return 0;
173 case ARM_AM::ia: return 1;
174 case ARM_AM::db: return 2;
175 case ARM_AM::ib: return 3;
178 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
180 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
182 default: llvm_unreachable("Unknown shift opc!");
183 case ARM_AM::no_shift:
184 case ARM_AM::lsl: return 0;
185 case ARM_AM::lsr: return 1;
186 case ARM_AM::asr: return 2;
188 case ARM_AM::rrx: return 3;
193 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
194 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups) const;
197 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
198 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
199 SmallVectorImpl<MCFixup> &Fixups) const;
201 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
202 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
203 SmallVectorImpl<MCFixup> &Fixups) const;
205 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
206 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
207 SmallVectorImpl<MCFixup> &Fixups) const;
209 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
211 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
212 SmallVectorImpl<MCFixup> &Fixups) const;
214 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
215 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
216 SmallVectorImpl<MCFixup> &Fixups) const;
218 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
219 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
220 SmallVectorImpl<MCFixup> &Fixups) const;
222 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
223 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
224 SmallVectorImpl<MCFixup> &Fixups) const;
226 /// getCCOutOpValue - Return encoding of the 's' bit.
227 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
228 SmallVectorImpl<MCFixup> &Fixups) const {
229 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
231 return MI.getOperand(Op).getReg() == ARM::CPSR;
234 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
235 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
236 SmallVectorImpl<MCFixup> &Fixups) const {
237 unsigned SoImm = MI.getOperand(Op).getImm();
238 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
239 assert(SoImmVal != -1 && "Not a valid so_imm value!");
241 // Encode rotate_imm.
242 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
243 << ARMII::SoRotImmShift;
246 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
250 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
251 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
252 SmallVectorImpl<MCFixup> &Fixups) const {
253 unsigned SoImm = MI.getOperand(Op).getImm();
254 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
255 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
259 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
260 SmallVectorImpl<MCFixup> &Fixups) const;
261 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
262 SmallVectorImpl<MCFixup> &Fixups) const;
263 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
264 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
266 SmallVectorImpl<MCFixup> &Fixups) const;
268 /// getSORegOpValue - Return an encoded so_reg shifted register value.
269 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
270 SmallVectorImpl<MCFixup> &Fixups) const;
271 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
272 SmallVectorImpl<MCFixup> &Fixups) const;
274 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
275 SmallVectorImpl<MCFixup> &Fixups) const {
276 switch (MI.getOperand(Op).getImm()) {
277 default: assert (0 && "Not a valid rot_imm value!");
285 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
286 SmallVectorImpl<MCFixup> &Fixups) const {
287 return MI.getOperand(Op).getImm() - 1;
290 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
291 SmallVectorImpl<MCFixup> &Fixups) const {
292 return 64 - MI.getOperand(Op).getImm();
295 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
296 SmallVectorImpl<MCFixup> &Fixups) const;
298 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
299 SmallVectorImpl<MCFixup> &Fixups) const;
300 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
301 SmallVectorImpl<MCFixup> &Fixups) const;
302 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
303 SmallVectorImpl<MCFixup> &Fixups) const;
304 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
305 SmallVectorImpl<MCFixup> &Fixups) const;
307 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
308 unsigned EncodedValue) const;
309 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
310 unsigned EncodedValue) const;
311 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
312 unsigned EncodedValue) const;
314 unsigned VFPThumb2PostEncoder(const MCInst &MI,
315 unsigned EncodedValue) const;
317 void EmitByte(unsigned char C, raw_ostream &OS) const {
321 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
322 // Output the constant in little endian byte order.
323 for (unsigned i = 0; i != Size; ++i) {
324 EmitByte(Val & 255, OS);
329 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
330 SmallVectorImpl<MCFixup> &Fixups) const;
333 } // end anonymous namespace
335 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
337 return new ARMMCCodeEmitter(TM, Ctx);
340 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
341 /// instructions, and rewrite them to their Thumb2 form if we are currently in
343 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
344 unsigned EncodedValue) const {
345 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
346 if (Subtarget.isThumb2()) {
347 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
348 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
350 unsigned Bit24 = EncodedValue & 0x01000000;
351 unsigned Bit28 = Bit24 << 4;
352 EncodedValue &= 0xEFFFFFFF;
353 EncodedValue |= Bit28;
354 EncodedValue |= 0x0F000000;
360 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
361 /// instructions, and rewrite them to their Thumb2 form if we are currently in
363 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
364 unsigned EncodedValue) const {
365 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
366 if (Subtarget.isThumb2()) {
367 EncodedValue &= 0xF0FFFFFF;
368 EncodedValue |= 0x09000000;
374 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
375 /// instructions, and rewrite them to their Thumb2 form if we are currently in
377 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
378 unsigned EncodedValue) const {
379 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
380 if (Subtarget.isThumb2()) {
381 EncodedValue &= 0x00FFFFFF;
382 EncodedValue |= 0xEE000000;
388 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
389 /// them to their Thumb2 form if we are currently in Thumb2 mode.
390 unsigned ARMMCCodeEmitter::
391 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
392 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
393 EncodedValue &= 0x0FFFFFFF;
394 EncodedValue |= 0xE0000000;
399 /// getMachineOpValue - Return binary encoding of operand. If the machine
400 /// operand requires relocation, record the relocation and return zero.
401 unsigned ARMMCCodeEmitter::
402 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
403 SmallVectorImpl<MCFixup> &Fixups) const {
405 unsigned Reg = MO.getReg();
406 unsigned RegNo = getARMRegisterNumbering(Reg);
408 // Q registers are encoded as 2x their register number.
412 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
413 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
414 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
415 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
418 } else if (MO.isImm()) {
419 return static_cast<unsigned>(MO.getImm());
420 } else if (MO.isFPImm()) {
421 return static_cast<unsigned>(APFloat(MO.getFPImm())
422 .bitcastToAPInt().getHiBits(32).getLimitedValue());
425 llvm_unreachable("Unable to encode MCOperand!");
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
430 bool ARMMCCodeEmitter::
431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
433 const MCOperand &MO = MI.getOperand(OpIdx);
434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
436 Reg = getARMRegisterNumbering(MO.getReg());
438 int32_t SImm = MO1.getImm();
441 // Special value for #-0
442 if (SImm == INT32_MIN)
445 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
455 /// getBranchTargetOpValue - Helper function to get the branch target operand,
456 /// which is either an immediate or requires a fixup.
457 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
459 SmallVectorImpl<MCFixup> &Fixups) {
460 const MCOperand &MO = MI.getOperand(OpIdx);
462 // If the destination is an immediate, we have nothing to do.
463 if (MO.isImm()) return MO.getImm();
464 assert(MO.isExpr() && "Unexpected branch target type!");
465 const MCExpr *Expr = MO.getExpr();
466 MCFixupKind Kind = MCFixupKind(FixupKind);
467 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
469 // All of the information is in the fixup.
473 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
474 uint32_t ARMMCCodeEmitter::
475 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
476 SmallVectorImpl<MCFixup> &Fixups) const {
477 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
480 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
481 /// BLX branch target.
482 uint32_t ARMMCCodeEmitter::
483 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
484 SmallVectorImpl<MCFixup> &Fixups) const {
485 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
488 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
489 uint32_t ARMMCCodeEmitter::
490 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
491 SmallVectorImpl<MCFixup> &Fixups) const {
492 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
495 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
496 uint32_t ARMMCCodeEmitter::
497 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
498 SmallVectorImpl<MCFixup> &Fixups) const {
499 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
502 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
503 uint32_t ARMMCCodeEmitter::
504 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
505 SmallVectorImpl<MCFixup> &Fixups) const {
506 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
509 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
511 uint32_t ARMMCCodeEmitter::
512 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
513 SmallVectorImpl<MCFixup> &Fixups) const {
514 // FIXME: This really, really shouldn't use TargetMachine. We don't want
515 // coupling between MC and TM anywhere we can help it.
516 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
517 if (Subtarget.isThumb2())
519 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
520 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
523 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
524 /// immediate branch target.
525 uint32_t ARMMCCodeEmitter::
526 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
527 SmallVectorImpl<MCFixup> &Fixups) const {
529 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
530 bool I = (Val & 0x800000);
531 bool J1 = (Val & 0x400000);
532 bool J2 = (Val & 0x200000);
546 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
548 uint32_t ARMMCCodeEmitter::
549 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
550 SmallVectorImpl<MCFixup> &Fixups) const {
551 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
552 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
556 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
558 uint32_t ARMMCCodeEmitter::
559 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
560 SmallVectorImpl<MCFixup> &Fixups) const {
561 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
562 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
566 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
568 uint32_t ARMMCCodeEmitter::
569 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
570 SmallVectorImpl<MCFixup> &Fixups) const {
571 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
572 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
576 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
578 uint32_t ARMMCCodeEmitter::
579 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
580 SmallVectorImpl<MCFixup> &) const {
584 const MCOperand &MO1 = MI.getOperand(OpIdx);
585 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
586 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
587 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
588 return (Rm << 3) | Rn;
591 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
592 uint32_t ARMMCCodeEmitter::
593 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
594 SmallVectorImpl<MCFixup> &Fixups) const {
596 // {12} = (U)nsigned (add == '1', sub == '0')
600 // If The first operand isn't a register, we have a label reference.
601 const MCOperand &MO = MI.getOperand(OpIdx);
602 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
603 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
604 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
606 isAdd = false ; // 'U' bit is set as part of the fixup.
608 const MCExpr *Expr = 0;
612 Expr = MO2.getExpr();
614 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
616 if (Subtarget.isThumb2())
617 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
619 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
620 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
622 ++MCNumCPRelocations;
624 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
626 uint32_t Binary = Imm12 & 0xfff;
627 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
630 Binary |= (Reg << 13);
634 /// getT2AddrModeImm8s4OpValue - Return encoding info for
635 /// 'reg +/- imm8<<2' operand.
636 uint32_t ARMMCCodeEmitter::
637 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
638 SmallVectorImpl<MCFixup> &Fixups) const {
640 // {8} = (U)nsigned (add == '1', sub == '0')
644 // If The first operand isn't a register, we have a label reference.
645 const MCOperand &MO = MI.getOperand(OpIdx);
647 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
649 isAdd = false ; // 'U' bit is set as part of the fixup.
651 assert(MO.isExpr() && "Unexpected machine operand type!");
652 const MCExpr *Expr = MO.getExpr();
653 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
654 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
656 ++MCNumCPRelocations;
658 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
660 uint32_t Binary = (Imm8 >> 2) & 0xff;
661 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
664 Binary |= (Reg << 9);
668 uint32_t ARMMCCodeEmitter::
669 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
670 SmallVectorImpl<MCFixup> &Fixups) const {
671 // {20-16} = imm{15-12}
672 // {11-0} = imm{11-0}
673 const MCOperand &MO = MI.getOperand(OpIdx);
675 return static_cast<unsigned>(MO.getImm());
676 } else if (const MCSymbolRefExpr *Expr =
677 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
679 switch (Expr->getKind()) {
680 default: assert(0 && "Unsupported ARMFixup");
681 case MCSymbolRefExpr::VK_ARM_HI16:
682 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
684 case MCSymbolRefExpr::VK_ARM_LO16:
685 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
688 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
691 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
695 uint32_t ARMMCCodeEmitter::
696 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
697 SmallVectorImpl<MCFixup> &Fixups) const {
698 const MCOperand &MO = MI.getOperand(OpIdx);
699 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
700 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
701 unsigned Rn = getARMRegisterNumbering(MO.getReg());
702 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
703 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
704 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
705 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
706 unsigned SBits = getShiftOp(ShOp);
715 uint32_t Binary = Rm;
717 Binary |= SBits << 5;
718 Binary |= ShImm << 7;
724 uint32_t ARMMCCodeEmitter::
725 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
726 SmallVectorImpl<MCFixup> &Fixups) const {
728 // {13} 1 == imm12, 0 == Rm
731 const MCOperand &MO = MI.getOperand(OpIdx);
732 unsigned Rn = getARMRegisterNumbering(MO.getReg());
733 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
738 uint32_t ARMMCCodeEmitter::
739 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
740 SmallVectorImpl<MCFixup> &Fixups) const {
741 // {13} 1 == imm12, 0 == Rm
744 const MCOperand &MO = MI.getOperand(OpIdx);
745 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
746 unsigned Imm = MO1.getImm();
747 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
748 bool isReg = MO.getReg() != 0;
749 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
750 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
752 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
753 Binary <<= 7; // Shift amount is bits [11:7]
754 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
755 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
757 return Binary | (isAdd << 12) | (isReg << 13);
760 uint32_t ARMMCCodeEmitter::
761 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
762 SmallVectorImpl<MCFixup> &Fixups) const {
763 // {9} 1 == imm8, 0 == Rm
767 const MCOperand &MO = MI.getOperand(OpIdx);
768 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
769 unsigned Imm = MO1.getImm();
770 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
771 bool isImm = MO.getReg() == 0;
772 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
773 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
775 Imm8 = getARMRegisterNumbering(MO.getReg());
776 return Imm8 | (isAdd << 8) | (isImm << 9);
779 uint32_t ARMMCCodeEmitter::
780 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
781 SmallVectorImpl<MCFixup> &Fixups) const {
782 // {13} 1 == imm8, 0 == Rm
787 const MCOperand &MO = MI.getOperand(OpIdx);
788 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
789 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
790 unsigned Rn = getARMRegisterNumbering(MO.getReg());
791 unsigned Imm = MO2.getImm();
792 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
793 bool isImm = MO1.getReg() == 0;
794 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
795 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
797 Imm8 = getARMRegisterNumbering(MO1.getReg());
798 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
801 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
802 uint32_t ARMMCCodeEmitter::
803 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
804 SmallVectorImpl<MCFixup> &Fixups) const {
807 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
808 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
809 "Unexpected base register!");
811 // The immediate is already shifted for the implicit zeroes, so no change
813 return MO1.getImm() & 0xff;
816 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
817 uint32_t ARMMCCodeEmitter::
818 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
819 SmallVectorImpl<MCFixup> &Fixups) const {
823 const MCOperand &MO = MI.getOperand(OpIdx);
824 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
825 unsigned Rn = getARMRegisterNumbering(MO.getReg());
826 unsigned Imm5 = MO1.getImm();
827 return ((Imm5 & 0x1f) << 3) | Rn;
830 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
831 uint32_t ARMMCCodeEmitter::
832 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
833 SmallVectorImpl<MCFixup> &Fixups) const {
834 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
837 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
838 uint32_t ARMMCCodeEmitter::
839 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
840 SmallVectorImpl<MCFixup> &Fixups) const {
842 // {8} = (U)nsigned (add == '1', sub == '0')
846 // If The first operand isn't a register, we have a label reference.
847 const MCOperand &MO = MI.getOperand(OpIdx);
849 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
851 isAdd = false; // 'U' bit is handled as part of the fixup.
853 assert(MO.isExpr() && "Unexpected machine operand type!");
854 const MCExpr *Expr = MO.getExpr();
856 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
857 if (Subtarget.isThumb2())
858 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
860 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
861 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
863 ++MCNumCPRelocations;
865 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
866 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
869 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
870 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
873 Binary |= (Reg << 9);
877 unsigned ARMMCCodeEmitter::
878 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
879 SmallVectorImpl<MCFixup> &Fixups) const {
880 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
881 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
882 // case the imm contains the amount to shift by.
885 // {4} = 1 if reg shift, 0 if imm shift
893 const MCOperand &MO = MI.getOperand(OpIdx);
894 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
895 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
896 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
899 unsigned Binary = getARMRegisterNumbering(MO.getReg());
901 // Encode the shift opcode.
903 unsigned Rs = MO1.getReg();
905 // Set shift operand (bit[7:4]).
910 // RRX - 0110 and bit[11:8] clear.
912 default: llvm_unreachable("Unknown shift opc!");
913 case ARM_AM::lsl: SBits = 0x1; break;
914 case ARM_AM::lsr: SBits = 0x3; break;
915 case ARM_AM::asr: SBits = 0x5; break;
916 case ARM_AM::ror: SBits = 0x7; break;
917 case ARM_AM::rrx: SBits = 0x6; break;
920 // Set shift operand (bit[6:4]).
926 default: llvm_unreachable("Unknown shift opc!");
927 case ARM_AM::lsl: SBits = 0x0; break;
928 case ARM_AM::lsr: SBits = 0x2; break;
929 case ARM_AM::asr: SBits = 0x4; break;
930 case ARM_AM::ror: SBits = 0x6; break;
934 Binary |= SBits << 4;
935 if (SOpc == ARM_AM::rrx)
938 // Encode the shift operation Rs or shift_imm (except rrx).
940 // Encode Rs bit[11:8].
941 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
942 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
945 // Encode shift_imm bit[11:7].
946 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
949 unsigned ARMMCCodeEmitter::
950 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
951 SmallVectorImpl<MCFixup> &Fixups) const {
952 const MCOperand &MO1 = MI.getOperand(OpNum);
953 const MCOperand &MO2 = MI.getOperand(OpNum+1);
954 const MCOperand &MO3 = MI.getOperand(OpNum+2);
956 // Encoded as [Rn, Rm, imm].
957 // FIXME: Needs fixup support.
958 unsigned Value = getARMRegisterNumbering(MO1.getReg());
960 Value |= getARMRegisterNumbering(MO2.getReg());
962 Value |= MO3.getImm();
967 unsigned ARMMCCodeEmitter::
968 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
969 SmallVectorImpl<MCFixup> &Fixups) const {
970 const MCOperand &MO1 = MI.getOperand(OpNum);
971 const MCOperand &MO2 = MI.getOperand(OpNum+1);
973 // FIXME: Needs fixup support.
974 unsigned Value = getARMRegisterNumbering(MO1.getReg());
976 // Even though the immediate is 8 bits long, we need 9 bits in order
977 // to represent the (inverse of the) sign bit.
979 int32_t tmp = (int32_t)MO2.getImm();
983 Value |= 256; // Set the ADD bit
988 unsigned ARMMCCodeEmitter::
989 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
990 SmallVectorImpl<MCFixup> &Fixups) const {
991 const MCOperand &MO1 = MI.getOperand(OpNum);
993 // FIXME: Needs fixup support.
995 int32_t tmp = (int32_t)MO1.getImm();
999 Value |= 256; // Set the ADD bit
1004 unsigned ARMMCCodeEmitter::
1005 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1006 SmallVectorImpl<MCFixup> &Fixups) const {
1007 const MCOperand &MO1 = MI.getOperand(OpNum);
1009 // FIXME: Needs fixup support.
1011 int32_t tmp = (int32_t)MO1.getImm();
1015 Value |= 4096; // Set the ADD bit
1016 Value |= tmp & 4095;
1020 unsigned ARMMCCodeEmitter::
1021 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1022 SmallVectorImpl<MCFixup> &Fixups) const {
1023 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1024 // shifted. The second is the amount to shift by.
1031 const MCOperand &MO = MI.getOperand(OpIdx);
1032 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1033 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1036 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1038 // Encode the shift opcode.
1040 // Set shift operand (bit[6:4]).
1046 default: llvm_unreachable("Unknown shift opc!");
1047 case ARM_AM::lsl: SBits = 0x0; break;
1048 case ARM_AM::lsr: SBits = 0x2; break;
1049 case ARM_AM::asr: SBits = 0x4; break;
1050 case ARM_AM::ror: SBits = 0x6; break;
1053 Binary |= SBits << 4;
1054 if (SOpc == ARM_AM::rrx)
1057 // Encode shift_imm bit[11:7].
1058 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1061 unsigned ARMMCCodeEmitter::
1062 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1063 SmallVectorImpl<MCFixup> &Fixups) const {
1064 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1066 const MCOperand &MO = MI.getOperand(Op);
1067 uint32_t v = ~MO.getImm();
1068 uint32_t lsb = CountTrailingZeros_32(v);
1069 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1070 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1071 return lsb | (msb << 5);
1074 unsigned ARMMCCodeEmitter::
1075 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1076 SmallVectorImpl<MCFixup> &Fixups) const {
1079 // {7-0} = Number of registers
1082 // {15-0} = Bitfield of GPRs.
1083 unsigned Reg = MI.getOperand(Op).getReg();
1084 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1085 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1087 unsigned Binary = 0;
1089 if (SPRRegs || DPRRegs) {
1091 unsigned RegNo = getARMRegisterNumbering(Reg);
1092 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1093 Binary |= (RegNo & 0x1f) << 8;
1097 Binary |= NumRegs * 2;
1099 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1100 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1101 Binary |= 1 << RegNo;
1108 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1109 /// with the alignment operand.
1110 unsigned ARMMCCodeEmitter::
1111 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1112 SmallVectorImpl<MCFixup> &Fixups) const {
1113 const MCOperand &Reg = MI.getOperand(Op);
1114 const MCOperand &Imm = MI.getOperand(Op + 1);
1116 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1119 switch (Imm.getImm()) {
1123 case 8: Align = 0x01; break;
1124 case 16: Align = 0x02; break;
1125 case 32: Align = 0x03; break;
1128 return RegNo | (Align << 4);
1131 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1132 /// alignment operand for use in VLD-dup instructions. This is the same as
1133 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1134 /// different for VLD4-dup.
1135 unsigned ARMMCCodeEmitter::
1136 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1137 SmallVectorImpl<MCFixup> &Fixups) const {
1138 const MCOperand &Reg = MI.getOperand(Op);
1139 const MCOperand &Imm = MI.getOperand(Op + 1);
1141 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1144 switch (Imm.getImm()) {
1148 case 8: Align = 0x01; break;
1149 case 16: Align = 0x03; break;
1152 return RegNo | (Align << 4);
1155 unsigned ARMMCCodeEmitter::
1156 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1157 SmallVectorImpl<MCFixup> &Fixups) const {
1158 const MCOperand &MO = MI.getOperand(Op);
1159 if (MO.getReg() == 0) return 0x0D;
1163 void ARMMCCodeEmitter::
1164 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1165 SmallVectorImpl<MCFixup> &Fixups) const {
1166 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1167 // Pseudo instructions don't get encoded.
1168 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1169 uint64_t TSFlags = Desc.TSFlags;
1170 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1173 // Basic size info comes from the TSFlags field.
1174 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1175 default: llvm_unreachable("Unexpected instruction size!");
1176 case ARMII::Size2Bytes: Size = 2; break;
1177 case ARMII::Size4Bytes: Size = 4; break;
1179 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1180 // Thumb 32-bit wide instructions need to be have the high order halfword
1182 if (Subtarget.isThumb() && Size == 4) {
1183 EmitConstant(Binary >> 16, 2, OS);
1184 EmitConstant(Binary & 0xffff, 2, OS);
1186 EmitConstant(Binary, Size, OS);
1187 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1190 #include "ARMGenMCCodeEmitter.inc"