1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMBaseInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
24 class ARMMCCodeEmitter : public MCCodeEmitter {
25 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
26 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
27 const TargetMachine &TM;
28 const TargetInstrInfo &TII;
32 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
33 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
34 assert(0 && "ARMMCCodeEmitter::ARMMCCodeEmitter() not yet implemented.");
37 ~ARMMCCodeEmitter() {}
39 // getBinaryCodeForInstr - TableGen'erated function for getting the
40 // binary encoding for an instruction.
41 unsigned getBinaryCodeForInstr(const MCInst &MI);
43 /// getMachineOpValue - Return binary encoding of operand. If the machine
44 /// operand requires relocation, record the relocation and return zero.
45 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO);
46 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) {
47 return getMachineOpValue(MI, MI.getOperand(OpIdx));
50 unsigned getNumFixupKinds() const {
51 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
55 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
56 static MCFixupKindInfo rtn;
57 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
61 static unsigned GetARMRegNum(const MCOperand &MO) {
62 // FIXME: getARMRegisterNumbering() is sufficient?
63 assert(0 && "ARMMCCodeEmitter::GetARMRegNum() not yet implemented.");
67 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
72 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
73 raw_ostream &OS) const {
74 // Output the constant in little endian byte order.
75 for (unsigned i = 0; i != Size; ++i) {
76 EmitByte(Val & 255, CurByte, OS);
81 void EmitImmediate(const MCOperand &Disp,
82 unsigned ImmSize, MCFixupKind FixupKind,
83 unsigned &CurByte, raw_ostream &OS,
84 SmallVectorImpl<MCFixup> &Fixups,
85 int ImmOffset = 0) const;
87 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
88 SmallVectorImpl<MCFixup> &Fixups) const;
91 } // end anonymous namespace
94 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
97 return new ARMMCCodeEmitter(TM, Ctx);
100 void ARMMCCodeEmitter::
101 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
102 unsigned &CurByte, raw_ostream &OS,
103 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
104 assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
107 void ARMMCCodeEmitter::
108 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
109 SmallVectorImpl<MCFixup> &Fixups) const {
110 assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented.");
113 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
114 // be able to generate code emitter helpers for either variant, like it
115 // does for the AsmWriter.
116 #define ARMCodeEmitter ARMMCCodeEmitter
117 #define MachineInstr MCInst
118 #include "ARMGenCodeEmitter.inc"
119 #undef ARMCodeEmitter