1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addRegOperand(Reg, true);
135 void ARMRegisterInfo::
136 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
137 unsigned SrcReg, int FI,
138 const TargetRegisterClass *RC) const {
139 if (RC == ARM::GPRRegisterClass) {
140 MachineFunction &MF = *MBB.getParent();
141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
142 if (AFI->isThumbFunction())
143 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
144 .addFrameIndex(FI).addImm(0);
146 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
147 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
149 } else if (RC == ARM::DPRRegisterClass) {
150 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
151 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
153 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
154 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
155 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
159 void ARMRegisterInfo::
160 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
161 unsigned DestReg, int FI,
162 const TargetRegisterClass *RC) const {
163 if (RC == ARM::GPRRegisterClass) {
164 MachineFunction &MF = *MBB.getParent();
165 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
166 if (AFI->isThumbFunction())
167 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
168 .addFrameIndex(FI).addImm(0);
170 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
171 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
173 } else if (RC == ARM::DPRRegisterClass) {
174 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
175 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
177 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
178 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
179 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
183 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator I,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *RC) const {
187 if (RC == ARM::GPRRegisterClass) {
188 MachineFunction &MF = *MBB.getParent();
189 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
190 if (AFI->isThumbFunction())
191 BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
193 BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
194 .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0);
195 } else if (RC == ARM::SPRRegisterClass)
196 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
197 .addImm((int64_t)ARMCC::AL).addReg(0);
198 else if (RC == ARM::DPRRegisterClass)
199 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg)
200 .addImm((int64_t)ARMCC::AL).addReg(0);
205 /// emitLoadConstPool - Emits a load from constpool to materialize the
206 /// specified immediate.
207 static void emitLoadConstPool(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator &MBBI,
209 unsigned DestReg, int Val,
210 ARMCC::CondCodes Pred, unsigned PredReg,
211 const TargetInstrInfo &TII, bool isThumb) {
212 MachineFunction &MF = *MBB.getParent();
213 MachineConstantPool *ConstantPool = MF.getConstantPool();
214 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
215 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
217 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
219 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
220 .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
223 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator I,
226 const MachineInstr *Orig) const {
227 if (Orig->getOpcode() == ARM::MOVi2pieces) {
228 emitLoadConstPool(MBB, I, DestReg,
229 Orig->getOperand(1).getImmedValue(),
230 (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
231 Orig->getOperand(3).getReg(),
236 MachineInstr *MI = Orig->clone();
237 MI->getOperand(0).setReg(DestReg);
241 /// isLowRegister - Returns true if the register is low register r0-r7.
243 static bool isLowRegister(unsigned Reg) {
246 case R0: case R1: case R2: case R3:
247 case R4: case R5: case R6: case R7:
254 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
255 unsigned OpNum, int FI) const {
256 unsigned Opc = MI->getOpcode();
257 MachineInstr *NewMI = NULL;
261 if (MI->getOperand(4).getReg() == ARM::CPSR)
262 // If it is updating CPSR, then it cannot be foled.
264 unsigned Pred = MI->getOperand(2).getImmedValue();
265 unsigned PredReg = MI->getOperand(3).getReg();
266 if (OpNum == 0) { // move -> store
267 unsigned SrcReg = MI->getOperand(1).getReg();
268 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
269 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
270 } else { // move -> load
271 unsigned DstReg = MI->getOperand(0).getReg();
272 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
273 .addImm(0).addImm(Pred).addReg(PredReg);
278 if (OpNum == 0) { // move -> store
279 unsigned SrcReg = MI->getOperand(1).getReg();
280 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
281 // tSpill cannot take a high register operand.
283 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
285 } else { // move -> load
286 unsigned DstReg = MI->getOperand(0).getReg();
287 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
288 // tRestore cannot target a high register operand.
290 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
296 unsigned Pred = MI->getOperand(2).getImmedValue();
297 unsigned PredReg = MI->getOperand(3).getReg();
298 if (OpNum == 0) { // move -> store
299 unsigned SrcReg = MI->getOperand(1).getReg();
300 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
301 .addImm(0).addImm(Pred).addReg(PredReg);
302 } else { // move -> load
303 unsigned DstReg = MI->getOperand(0).getReg();
304 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
305 .addImm(0).addImm(Pred).addReg(PredReg);
310 unsigned Pred = MI->getOperand(2).getImmedValue();
311 unsigned PredReg = MI->getOperand(3).getReg();
312 if (OpNum == 0) { // move -> store
313 unsigned SrcReg = MI->getOperand(1).getReg();
314 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
315 .addImm(0).addImm(Pred).addReg(PredReg);
316 } else { // move -> load
317 unsigned DstReg = MI->getOperand(0).getReg();
318 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
319 .addImm(0).addImm(Pred).addReg(PredReg);
326 NewMI->copyKillDeadInfo(MI);
330 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
331 static const unsigned CalleeSavedRegs[] = {
332 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
333 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
335 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
336 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
340 static const unsigned DarwinCalleeSavedRegs[] = {
341 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
342 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
344 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
345 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
348 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
351 const TargetRegisterClass* const *
352 ARMRegisterInfo::getCalleeSavedRegClasses() const {
353 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
354 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
355 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
356 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
358 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
359 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
362 return CalleeSavedRegClasses;
365 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
366 // FIXME: avoid re-calculating this everytime.
367 BitVector Reserved(getNumRegs());
368 Reserved.set(ARM::SP);
369 Reserved.set(ARM::PC);
370 if (STI.isTargetDarwin() || hasFP(MF))
371 Reserved.set(FramePtr);
372 // Some targets reserve R9.
373 if (STI.isR9Reserved())
374 Reserved.set(ARM::R9);
379 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
387 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
391 return STI.isR9Reserved();
398 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
399 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
400 return ThumbRegScavenging || !AFI->isThumbFunction();
403 /// hasFP - Return true if the specified function should have a dedicated frame
404 /// pointer register. This is true if the function has variable sized allocas
405 /// or if frame pointer elimination is disabled.
407 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
408 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
411 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
412 // not required, we reserve argument space for call sites in the function
413 // immediately on entry to the current function. This eliminates the need for
414 // add/sub sp brackets around call sites. Returns true if the call frame is
415 // included as part of the stack frame.
416 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
417 const MachineFrameInfo *FFI = MF.getFrameInfo();
418 unsigned CFSize = FFI->getMaxCallFrameSize();
419 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
420 // It's not always a good idea to include the call frame as part of the
421 // stack frame. ARM (especially Thumb) has small immediate offset to
422 // address the stack frame. So a large call frame can cause poor codegen
423 // and may even makes it impossible to scavenge a register.
424 if (AFI->isThumbFunction()) {
425 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
428 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
434 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
435 /// a destreg = basereg + immediate in ARM code.
437 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
438 MachineBasicBlock::iterator &MBBI,
439 unsigned DestReg, unsigned BaseReg, int NumBytes,
440 ARMCC::CondCodes Pred, unsigned PredReg,
441 const TargetInstrInfo &TII) {
442 bool isSub = NumBytes < 0;
443 if (isSub) NumBytes = -NumBytes;
446 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
447 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
448 assert(ThisVal && "Didn't extract field correctly");
450 // We will handle these bits from offset, clear them.
451 NumBytes &= ~ThisVal;
453 // Get the properly encoded SOImmVal field.
454 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
455 assert(SOImmVal != -1 && "Bit extraction didn't work?");
457 // Build the new ADD / SUB.
458 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
459 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
460 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
465 /// calcNumMI - Returns the number of instructions required to materialize
466 /// the specific add / sub r, c instruction.
467 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
468 unsigned NumBits, unsigned Scale) {
470 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
472 if (Opc == ARM::tADDrSPi) {
473 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
477 Scale = 1; // Followed by a number of tADDi8.
478 Chunk = ((1 << NumBits) - 1) * Scale;
481 NumMIs += Bytes / Chunk;
482 if ((Bytes % Chunk) != 0)
489 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
490 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
491 /// in a register using mov / mvn sequences or load the immediate from a
494 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
495 MachineBasicBlock::iterator &MBBI,
496 unsigned DestReg, unsigned BaseReg,
497 int NumBytes, bool CanChangeCC,
498 const TargetInstrInfo &TII) {
499 bool isHigh = !isLowRegister(DestReg) ||
500 (BaseReg != 0 && !isLowRegister(BaseReg));
502 // Subtract doesn't have high register version. Load the negative value
503 // if either base or dest register is a high register. Also, if do not
504 // issue sub as part of the sequence if condition register is to be
506 if (NumBytes < 0 && !isHigh && CanChangeCC) {
508 NumBytes = -NumBytes;
510 unsigned LdReg = DestReg;
511 if (DestReg == ARM::SP) {
512 assert(BaseReg == ARM::SP && "Unexpected!");
514 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
515 .addReg(ARM::R3, false, false, true);
518 if (NumBytes <= 255 && NumBytes >= 0)
519 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
520 else if (NumBytes < 0 && NumBytes >= -255) {
521 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
522 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
523 .addReg(LdReg, false, false, true);
525 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
528 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
529 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
530 if (DestReg == ARM::SP || isSub)
531 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
533 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
534 if (DestReg == ARM::SP)
535 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
536 .addReg(ARM::R12, false, false, true);
539 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
540 /// a destreg = basereg + immediate in Thumb code.
542 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator &MBBI,
544 unsigned DestReg, unsigned BaseReg,
545 int NumBytes, const TargetInstrInfo &TII) {
546 bool isSub = NumBytes < 0;
547 unsigned Bytes = (unsigned)NumBytes;
548 if (isSub) Bytes = -NumBytes;
549 bool isMul4 = (Bytes & 3) == 0;
550 bool isTwoAddr = false;
551 bool DstNotEqBase = false;
552 unsigned NumBits = 1;
557 if (DestReg == BaseReg && BaseReg == ARM::SP) {
558 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
561 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
563 } else if (!isSub && BaseReg == ARM::SP) {
566 // r1 = add sp, 100 * 4
570 ExtraOpc = ARM::tADDi3;
579 if (DestReg != BaseReg)
582 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
586 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
587 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
588 if (NumMIs > Threshold) {
589 // This will expand into too many instructions. Load the immediate from a
591 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
596 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
597 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
598 unsigned Chunk = (1 << 3) - 1;
599 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
601 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
602 .addReg(BaseReg, false, false, true).addImm(ThisVal);
604 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
605 .addReg(BaseReg, false, false, true);
610 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
612 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
615 // Build the new tADD / tSUB.
617 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
619 bool isKill = BaseReg != ARM::SP;
620 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
621 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
624 if (Opc == ARM::tADDrSPi) {
630 Chunk = ((1 << NumBits) - 1) * Scale;
631 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
638 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
639 .addReg(DestReg, false, false, true)
640 .addImm(((unsigned)NumBytes) & 3);
644 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
645 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
646 bool isThumb, const TargetInstrInfo &TII) {
648 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
650 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
654 void ARMRegisterInfo::
655 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
656 MachineBasicBlock::iterator I) const {
657 if (!hasReservedCallFrame(MF)) {
658 // If we have alloca, convert as follows:
659 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
660 // ADJCALLSTACKUP -> add, sp, sp, amount
661 MachineInstr *Old = I;
662 unsigned Amount = Old->getOperand(0).getImmedValue();
664 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
665 // We need to keep the stack aligned properly. To do this, we round the
666 // amount of space needed for the outgoing arguments up to the next
667 // alignment boundary.
668 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
669 Amount = (Amount+Align-1)/Align*Align;
671 // Replace the pseudo instruction with a new instruction...
672 unsigned Opc = Old->getOpcode();
673 bool isThumb = AFI->isThumbFunction();
674 ARMCC::CondCodes Pred = isThumb
675 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
676 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
677 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
678 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
680 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
681 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
688 /// emitThumbConstant - Emit a series of instructions to materialize a
690 static void emitThumbConstant(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator &MBBI,
692 unsigned DestReg, int Imm,
693 const TargetInstrInfo &TII) {
694 bool isSub = Imm < 0;
695 if (isSub) Imm = -Imm;
697 int Chunk = (1 << 8) - 1;
698 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
700 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
702 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
704 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
705 .addReg(DestReg, false, false, true);
708 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
709 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
710 /// register first and then a spilled callee-saved register if that fails.
712 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
713 ARMFunctionInfo *AFI) {
714 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
716 // Try a already spilled CS register.
717 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
722 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
723 int SPAdj, RegScavenger *RS) const{
725 MachineInstr &MI = *II;
726 MachineBasicBlock &MBB = *MI.getParent();
727 MachineFunction &MF = *MBB.getParent();
728 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
729 bool isThumb = AFI->isThumbFunction();
731 while (!MI.getOperand(i).isFrameIndex()) {
733 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
736 unsigned FrameReg = ARM::SP;
737 int FrameIndex = MI.getOperand(i).getFrameIndex();
738 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
739 MF.getFrameInfo()->getStackSize() + SPAdj;
741 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
742 Offset -= AFI->getGPRCalleeSavedArea1Offset();
743 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
744 Offset -= AFI->getGPRCalleeSavedArea2Offset();
745 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
746 Offset -= AFI->getDPRCalleeSavedAreaOffset();
747 else if (hasFP(MF)) {
748 assert(SPAdj == 0 && "Unexpected");
749 // There is alloca()'s in this function, must reference off the frame
751 FrameReg = getFrameRegister(MF);
752 Offset -= AFI->getFramePtrSpillOffset();
755 unsigned Opcode = MI.getOpcode();
756 const TargetInstrDescriptor &Desc = TII.get(Opcode);
757 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
760 if (Opcode == ARM::ADDri) {
761 Offset += MI.getOperand(i+1).getImm();
763 // Turn it into a move.
764 MI.setInstrDescriptor(TII.get(ARM::MOVr));
765 MI.getOperand(i).ChangeToRegister(FrameReg, false);
766 MI.RemoveOperand(i+1);
768 } else if (Offset < 0) {
771 MI.setInstrDescriptor(TII.get(ARM::SUBri));
774 // Common case: small offset, fits into instruction.
775 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
776 if (ImmedOffset != -1) {
777 // Replace the FrameIndex with sp / fp
778 MI.getOperand(i).ChangeToRegister(FrameReg, false);
779 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
783 // Otherwise, we fallback to common code below to form the imm offset with
784 // a sequence of ADDri instructions. First though, pull as much of the imm
785 // into this ADDri as possible.
786 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
787 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
789 // We will handle these bits from offset, clear them.
790 Offset &= ~ThisImmVal;
792 // Get the properly encoded SOImmVal field.
793 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
794 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
795 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
796 } else if (Opcode == ARM::tADDrSPi) {
797 Offset += MI.getOperand(i+1).getImm();
799 // Can't use tADDrSPi if it's based off the frame pointer.
800 unsigned NumBits = 0;
802 if (FrameReg != ARM::SP) {
803 Opcode = ARM::tADDi3;
804 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
809 assert((Offset & 3) == 0 &&
810 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
814 // Turn it into a move.
815 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
816 MI.getOperand(i).ChangeToRegister(FrameReg, false);
817 MI.RemoveOperand(i+1);
821 // Common case: small offset, fits into instruction.
822 unsigned Mask = (1 << NumBits) - 1;
823 if (((Offset / Scale) & ~Mask) == 0) {
824 // Replace the FrameIndex with sp / fp
825 MI.getOperand(i).ChangeToRegister(FrameReg, false);
826 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
830 unsigned DestReg = MI.getOperand(0).getReg();
831 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
832 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
833 // MI would expand into a large number of instructions. Don't try to
834 // simplify the immediate.
836 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
842 // Translate r0 = add sp, imm to
843 // r0 = add sp, 255*4
844 // r0 = add r0, (imm - 255*4)
845 MI.getOperand(i).ChangeToRegister(FrameReg, false);
846 MI.getOperand(i+1).ChangeToImmediate(Mask);
847 Offset = (Offset - Mask * Scale);
848 MachineBasicBlock::iterator NII = next(II);
849 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
851 // Translate r0 = add sp, -imm to
852 // r0 = -imm (this is then translated into a series of instructons)
854 emitThumbConstant(MBB, II, DestReg, Offset, TII);
855 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
856 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
857 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
863 unsigned NumBits = 0;
866 case ARMII::AddrMode2: {
868 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
869 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
874 case ARMII::AddrMode3: {
876 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
877 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
882 case ARMII::AddrMode5: {
884 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
885 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
891 case ARMII::AddrModeTs: {
893 InstrOffs = MI.getOperand(ImmIdx).getImm();
894 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
899 assert(0 && "Unsupported addressing mode!");
904 Offset += InstrOffs * Scale;
905 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
906 if (Offset < 0 && !isThumb) {
911 // Common case: small offset, fits into instruction.
912 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
913 int ImmedOffset = Offset / Scale;
914 unsigned Mask = (1 << NumBits) - 1;
915 if ((unsigned)Offset <= Mask * Scale) {
916 // Replace the FrameIndex with sp
917 MI.getOperand(i).ChangeToRegister(FrameReg, false);
919 ImmedOffset |= 1 << NumBits;
920 ImmOp.ChangeToImmediate(ImmedOffset);
924 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
925 if (AddrMode == ARMII::AddrModeTs) {
926 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
927 // a different base register.
929 Mask = (1 << NumBits) - 1;
931 // If this is a thumb spill / restore, we will be using a constpool load to
932 // materialize the offset.
933 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
934 ImmOp.ChangeToImmediate(0);
936 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
937 ImmedOffset = ImmedOffset & Mask;
939 ImmedOffset |= 1 << NumBits;
940 ImmOp.ChangeToImmediate(ImmedOffset);
941 Offset &= ~(Mask*Scale);
945 // If we get here, the immediate doesn't fit into the instruction. We folded
946 // as much as possible above, handle the rest, providing a register that is
948 assert(Offset && "This code isn't needed if offset already handled!");
951 if (TII.isLoad(Opcode)) {
952 // Use the destination register to materialize sp + offset.
953 unsigned TmpReg = MI.getOperand(0).getReg();
955 if (Opcode == ARM::tRestore) {
956 if (FrameReg == ARM::SP)
957 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
959 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
963 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
964 MI.setInstrDescriptor(TII.get(ARM::tLDR));
965 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
967 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
969 MI.addRegOperand(0, false); // tLDR has an extra register operand.
970 } else if (TII.isStore(Opcode)) {
971 // FIXME! This is horrific!!! We need register scavenging.
972 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
973 // also a ABI register so it's possible that is is the register that is
974 // being storing here. If that's the case, we do the following:
976 // Use r2 to materialize sp + offset
979 unsigned ValReg = MI.getOperand(0).getReg();
980 unsigned TmpReg = ARM::R3;
982 if (ValReg == ARM::R3) {
983 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
984 .addReg(ARM::R2, false, false, true);
987 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
988 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
989 .addReg(ARM::R3, false, false, true);
990 if (Opcode == ARM::tSpill) {
991 if (FrameReg == ARM::SP)
992 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
994 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
998 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
999 MI.setInstrDescriptor(TII.get(ARM::tSTR));
1000 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1002 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
1004 MI.addRegOperand(0, false); // tSTR has an extra register operand.
1006 MachineBasicBlock::iterator NII = next(II);
1007 if (ValReg == ARM::R3)
1008 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
1009 .addReg(ARM::R12, false, false, true);
1010 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1011 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
1012 .addReg(ARM::R12, false, false, true);
1014 assert(false && "Unexpected opcode!");
1016 // Insert a set of r12 with the full address: r12 = sp + offset
1017 // If the offset we have is too large to fit into the instruction, we need
1018 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1020 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1021 if (ScratchReg == 0)
1022 // No register is "free". Scavenge a register.
1023 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1024 int PIdx = MI.findFirstPredOperandIdx();
1025 ARMCC::CondCodes Pred = (PIdx == -1)
1026 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
1027 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1028 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1029 isSub ? -Offset : Offset, Pred, PredReg, TII);
1030 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1034 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1035 const MachineFrameInfo *FFI = MF.getFrameInfo();
1037 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1038 int FixedOff = -FFI->getObjectOffset(i);
1039 if (FixedOff > Offset) Offset = FixedOff;
1041 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1042 Offset += FFI->getObjectSize(i);
1043 unsigned Align = FFI->getObjectAlignment(i);
1044 // Adjust to alignment boundary
1045 Offset = (Offset+Align-1)/Align*Align;
1047 return (unsigned)Offset;
1051 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1052 RegScavenger *RS) const {
1053 // This tells PEI to spill the FP as if it is any other callee-save register
1054 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1055 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1056 // to combine multiple loads / stores.
1057 bool CanEliminateFrame = true;
1058 bool CS1Spilled = false;
1059 bool LRSpilled = false;
1060 unsigned NumGPRSpills = 0;
1061 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1062 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1063 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1065 // Don't spill FP if the frame can be eliminated. This is determined
1066 // by scanning the callee-save registers to see if any is used.
1067 const unsigned *CSRegs = getCalleeSavedRegs();
1068 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1069 for (unsigned i = 0; CSRegs[i]; ++i) {
1070 unsigned Reg = CSRegs[i];
1071 bool Spilled = false;
1072 if (MF.isPhysRegUsed(Reg)) {
1073 AFI->setCSRegisterIsSpilled(Reg);
1075 CanEliminateFrame = false;
1077 // Check alias registers too.
1078 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1079 if (MF.isPhysRegUsed(*Aliases)) {
1081 CanEliminateFrame = false;
1086 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1090 if (!STI.isTargetDarwin()) {
1097 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1112 if (!STI.isTargetDarwin()) {
1113 UnspilledCS1GPRs.push_back(Reg);
1123 UnspilledCS1GPRs.push_back(Reg);
1126 UnspilledCS2GPRs.push_back(Reg);
1133 bool ForceLRSpill = false;
1134 if (!LRSpilled && AFI->isThumbFunction()) {
1135 unsigned FnSize = ARM::GetFunctionSize(MF);
1136 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1137 // use of BL to implement far jump. If it turns out that it's not needed
1138 // then the branch fix up path will undo it.
1139 if (FnSize >= (1 << 11)) {
1140 CanEliminateFrame = false;
1141 ForceLRSpill = true;
1145 bool ExtraCSSpill = false;
1146 if (!CanEliminateFrame || hasFP(MF)) {
1147 AFI->setHasStackFrame(true);
1149 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1150 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1151 if (!LRSpilled && CS1Spilled) {
1152 MF.setPhysRegUsed(ARM::LR);
1153 AFI->setCSRegisterIsSpilled(ARM::LR);
1155 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1156 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1157 ForceLRSpill = false;
1158 ExtraCSSpill = true;
1161 // Darwin ABI requires FP to point to the stack slot that contains the
1163 if (STI.isTargetDarwin() || hasFP(MF)) {
1164 MF.setPhysRegUsed(FramePtr);
1168 // If stack and double are 8-byte aligned and we are spilling an odd number
1169 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1170 // the integer and double callee save areas.
1171 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1172 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1173 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1174 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1175 unsigned Reg = UnspilledCS1GPRs[i];
1176 // Don't spiil high register if the function is thumb
1177 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1178 MF.setPhysRegUsed(Reg);
1179 AFI->setCSRegisterIsSpilled(Reg);
1180 if (!isReservedReg(MF, Reg))
1181 ExtraCSSpill = true;
1185 } else if (!UnspilledCS2GPRs.empty() &&
1186 !AFI->isThumbFunction()) {
1187 unsigned Reg = UnspilledCS2GPRs.front();
1188 MF.setPhysRegUsed(Reg);
1189 AFI->setCSRegisterIsSpilled(Reg);
1190 if (!isReservedReg(MF, Reg))
1191 ExtraCSSpill = true;
1195 // Estimate if we might need to scavenge a register at some point in order
1196 // to materialize a stack offset. If so, either spill one additiona
1197 // callee-saved register or reserve a special spill slot to facilitate
1198 // register scavenging.
1199 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1200 MachineFrameInfo *MFI = MF.getFrameInfo();
1201 unsigned Size = estimateStackSize(MF, MFI);
1202 unsigned Limit = (1 << 12) - 1;
1203 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1204 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1205 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1206 if (I->getOperand(i).isFrameIndex()) {
1207 unsigned Opcode = I->getOpcode();
1208 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1209 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1210 if (AddrMode == ARMII::AddrMode3) {
1211 Limit = (1 << 8) - 1;
1212 goto DoneEstimating;
1213 } else if (AddrMode == ARMII::AddrMode5) {
1214 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1215 if (ThisLimit < Limit)
1221 if (Size >= Limit) {
1222 // If any non-reserved CS register isn't spilled, just spill one or two
1223 // extra. That should take care of it!
1224 unsigned NumExtras = TargetAlign / 4;
1225 SmallVector<unsigned, 2> Extras;
1226 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1227 unsigned Reg = UnspilledCS1GPRs.back();
1228 UnspilledCS1GPRs.pop_back();
1229 if (!isReservedReg(MF, Reg)) {
1230 Extras.push_back(Reg);
1234 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1235 unsigned Reg = UnspilledCS2GPRs.back();
1236 UnspilledCS2GPRs.pop_back();
1237 if (!isReservedReg(MF, Reg)) {
1238 Extras.push_back(Reg);
1242 if (Extras.size() && NumExtras == 0) {
1243 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1244 MF.setPhysRegUsed(Extras[i]);
1245 AFI->setCSRegisterIsSpilled(Extras[i]);
1248 // Reserve a slot closest to SP or frame pointer.
1249 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1250 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1251 RC->getAlignment()));
1258 MF.setPhysRegUsed(ARM::LR);
1259 AFI->setCSRegisterIsSpilled(ARM::LR);
1260 AFI->setLRIsSpilledForFarJump(true);
1264 /// Move iterator pass the next bunch of callee save load / store ops for
1265 /// the particular spill area (1: integer area 1, 2: integer area 2,
1266 /// 3: fp area, 0: don't care).
1267 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1268 MachineBasicBlock::iterator &MBBI,
1269 int Opc, unsigned Area,
1270 const ARMSubtarget &STI) {
1271 while (MBBI != MBB.end() &&
1272 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1275 unsigned Category = 0;
1276 switch (MBBI->getOperand(0).getReg()) {
1277 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1281 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1282 Category = STI.isTargetDarwin() ? 2 : 1;
1284 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1285 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1292 if (Done || Category != Area)
1300 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1301 MachineBasicBlock &MBB = MF.front();
1302 MachineBasicBlock::iterator MBBI = MBB.begin();
1303 MachineFrameInfo *MFI = MF.getFrameInfo();
1304 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1305 bool isThumb = AFI->isThumbFunction();
1306 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1307 unsigned NumBytes = MFI->getStackSize();
1308 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1311 // Check if R3 is live in. It might have to be used as a scratch register.
1312 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1314 if ((*I).first == ARM::R3) {
1315 AFI->setR3IsLiveIn(true);
1320 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1321 NumBytes = (NumBytes + 3) & ~3;
1322 MFI->setStackSize(NumBytes);
1325 // Determine the sizes of each callee-save spill areas and record which frame
1326 // belongs to which callee-save spill areas.
1327 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1328 int FramePtrSpillFI = 0;
1331 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1333 if (!AFI->hasStackFrame()) {
1335 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1339 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1340 unsigned Reg = CSI[i].getReg();
1341 int FI = CSI[i].getFrameIdx();
1348 if (Reg == FramePtr)
1349 FramePtrSpillFI = FI;
1350 AFI->addGPRCalleeSavedArea1Frame(FI);
1357 if (Reg == FramePtr)
1358 FramePtrSpillFI = FI;
1359 if (STI.isTargetDarwin()) {
1360 AFI->addGPRCalleeSavedArea2Frame(FI);
1363 AFI->addGPRCalleeSavedArea1Frame(FI);
1368 AFI->addDPRCalleeSavedAreaFrame(FI);
1374 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1375 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
1376 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1377 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1380 // Darwin ABI requires FP to point to the stack slot that contains the
1382 if (STI.isTargetDarwin() || hasFP(MF)) {
1383 MachineInstrBuilder MIB =
1384 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1385 .addFrameIndex(FramePtrSpillFI).addImm(0);
1386 if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0).addReg(0);
1390 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1391 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
1393 // Build the new SUBri to adjust SP for FP callee-save spill area.
1394 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1395 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
1398 // Determine starting offsets of spill areas.
1399 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1400 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1401 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1402 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1403 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1404 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1405 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1407 NumBytes = DPRCSOffset;
1409 // Insert it after all the callee-save spills.
1411 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1412 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1415 if(STI.isTargetELF() && hasFP(MF)) {
1416 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1417 AFI->getFramePtrSpillOffset());
1420 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1421 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1422 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1425 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1426 for (unsigned i = 0; CSRegs[i]; ++i)
1427 if (Reg == CSRegs[i])
1432 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1433 return ((MI->getOpcode() == ARM::FLDD ||
1434 MI->getOpcode() == ARM::LDR ||
1435 MI->getOpcode() == ARM::tRestore) &&
1436 MI->getOperand(1).isFrameIndex() &&
1437 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1440 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1441 MachineBasicBlock &MBB) const {
1442 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1443 assert((MBBI->getOpcode() == ARM::BX_RET ||
1444 MBBI->getOpcode() == ARM::tBX_RET ||
1445 MBBI->getOpcode() == ARM::tPOP_RET) &&
1446 "Can only insert epilog into returning blocks");
1448 MachineFrameInfo *MFI = MF.getFrameInfo();
1449 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1450 bool isThumb = AFI->isThumbFunction();
1451 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1452 int NumBytes = (int)MFI->getStackSize();
1453 if (!AFI->hasStackFrame()) {
1455 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1457 // Unwind MBBI to point to first LDR / FLDD.
1458 const unsigned *CSRegs = getCalleeSavedRegs();
1459 if (MBBI != MBB.begin()) {
1462 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1463 if (!isCSRestore(MBBI, CSRegs))
1467 // Move SP to start of FP callee save spill area.
1468 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1469 AFI->getGPRCalleeSavedArea2Size() +
1470 AFI->getDPRCalleeSavedAreaSize());
1473 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1474 // Reset SP based on frame pointer only if the stack frame extends beyond
1475 // frame pointer stack slot or target is ELF and the function has FP.
1477 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1479 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1481 if (MBBI->getOpcode() == ARM::tBX_RET &&
1482 &MBB.front() != MBBI &&
1483 prior(MBBI)->getOpcode() == ARM::tPOP) {
1484 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1485 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1487 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1490 // Darwin ABI requires FP to point to the stack slot that contains the
1492 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1493 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1494 // Reset SP based on frame pointer only if the stack frame extends beyond
1495 // frame pointer stack slot or target is ELF and the function has FP.
1496 if (AFI->getGPRCalleeSavedArea2Size() ||
1497 AFI->getDPRCalleeSavedAreaSize() ||
1498 AFI->getDPRCalleeSavedAreaOffset()||
1501 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1503 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1505 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1506 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1507 } else if (NumBytes) {
1508 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
1511 // Move SP to start of integer callee save spill area 2.
1512 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1513 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1516 // Move SP to start of integer callee save spill area 1.
1517 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1518 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1521 // Move SP to SP upon entry to the function.
1522 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1523 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1528 if (VARegSaveSize) {
1530 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1531 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1532 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1534 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1537 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1543 unsigned ARMRegisterInfo::getRARegister() const {
1547 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1548 if (STI.isTargetDarwin() || hasFP(MF))
1549 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1554 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1555 assert(0 && "What is the exception register");
1559 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1560 assert(0 && "What is the exception handler register");
1564 #include "ARMGenRegisterInfo.inc"