1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Type.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/STLExtras.h"
35 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
38 case R0: case S0: case D0: return 0;
39 case R1: case S1: case D1: return 1;
40 case R2: case S2: case D2: return 2;
41 case R3: case S3: case D3: return 3;
42 case R4: case S4: case D4: return 4;
43 case R5: case S5: case D5: return 5;
44 case R6: case S6: case D6: return 6;
45 case R7: case S7: case D7: return 7;
46 case R8: case S8: case D8: return 8;
47 case R9: case S9: case D9: return 9;
48 case R10: case S10: case D10: return 10;
49 case R11: case S11: case D11: return 11;
50 case R12: case S12: case D12: return 12;
51 case SP: case S13: case D13: return 13;
52 case LR: case S14: case D14: return 14;
53 case PC: case S15: case D15: return 15;
71 std::cerr << "Unknown ARM register!\n";
76 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
77 const ARMSubtarget &sti)
78 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
80 FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
83 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 const std::vector<CalleeSavedInfo> &CSI) const {
86 MachineFunction &MF = *MBB.getParent();
87 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
88 if (!AFI->isThumbFunction() || CSI.empty())
91 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
92 for (unsigned i = CSI.size(); i != 0; --i)
93 MIB.addReg(CSI[i-1].getReg());
97 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 const std::vector<CalleeSavedInfo> &CSI) const {
100 MachineFunction &MF = *MBB.getParent();
101 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
102 if (!AFI->isThumbFunction() || CSI.empty())
105 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
106 MBB.insert(MI, PopMI);
107 for (unsigned i = CSI.size(); i != 0; --i) {
108 unsigned Reg = CSI[i-1].getReg();
109 if (Reg == ARM::LR) {
111 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
114 PopMI->addRegOperand(Reg, true);
119 void ARMRegisterInfo::
120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121 unsigned SrcReg, int FI,
122 const TargetRegisterClass *RC) const {
123 if (RC == ARM::GPRRegisterClass) {
124 MachineFunction &MF = *MBB.getParent();
125 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
126 if (AFI->isThumbFunction())
127 BuildMI(MBB, I, TII.get(ARM::tSTRspi)).addReg(SrcReg)
128 .addFrameIndex(FI).addImm(0);
130 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
131 .addFrameIndex(FI).addReg(0).addImm(0);
132 } else if (RC == ARM::DPRRegisterClass) {
133 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
134 .addFrameIndex(FI).addImm(0);
136 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
137 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
138 .addFrameIndex(FI).addImm(0);
142 void ARMRegisterInfo::
143 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
144 unsigned DestReg, int FI,
145 const TargetRegisterClass *RC) const {
146 if (RC == ARM::GPRRegisterClass) {
147 MachineFunction &MF = *MBB.getParent();
148 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
149 if (AFI->isThumbFunction())
150 BuildMI(MBB, I, TII.get(ARM::tLDRspi), DestReg)
151 .addFrameIndex(FI).addImm(0);
153 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
154 .addFrameIndex(FI).addReg(0).addImm(0);
155 } else if (RC == ARM::DPRRegisterClass) {
156 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
157 .addFrameIndex(FI).addImm(0);
159 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
160 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
161 .addFrameIndex(FI).addImm(0);
165 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator I,
167 unsigned DestReg, unsigned SrcReg,
168 const TargetRegisterClass *RC) const {
169 if (RC == ARM::GPRRegisterClass) {
170 MachineFunction &MF = *MBB.getParent();
171 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
172 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr),
173 DestReg).addReg(SrcReg);
174 } else if (RC == ARM::SPRRegisterClass)
175 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
176 else if (RC == ARM::DPRRegisterClass)
177 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
182 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
183 unsigned OpNum, int FI) const {
184 unsigned Opc = MI->getOpcode();
185 MachineInstr *NewMI = NULL;
189 if (OpNum == 0) { // move -> store
190 unsigned SrcReg = MI->getOperand(1).getReg();
191 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
192 .addReg(0).addImm(0);
193 } else { // move -> load
194 unsigned DstReg = MI->getOperand(0).getReg();
195 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
201 if (OpNum == 0) { // move -> store
202 unsigned SrcReg = MI->getOperand(1).getReg();
203 NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI)
205 } else { // move -> load
206 unsigned DstReg = MI->getOperand(0).getReg();
207 NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI)
213 if (OpNum == 0) { // move -> store
214 unsigned SrcReg = MI->getOperand(1).getReg();
215 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
217 } else { // move -> load
218 unsigned DstReg = MI->getOperand(0).getReg();
219 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
224 if (OpNum == 0) { // move -> store
225 unsigned SrcReg = MI->getOperand(1).getReg();
226 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
228 } else { // move -> load
229 unsigned DstReg = MI->getOperand(0).getReg();
230 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
237 NewMI->copyKillDeadInfo(MI);
241 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
242 static const unsigned CalleeSavedRegs[] = {
243 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
244 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
246 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
247 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
251 static const unsigned DarwinCalleeSavedRegs[] = {
252 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
253 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
255 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
256 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
259 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
262 const TargetRegisterClass* const *
263 ARMRegisterInfo::getCalleeSavedRegClasses() const {
264 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
265 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
266 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
267 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
269 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
270 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
273 return CalleeSavedRegClasses;
276 /// hasFP - Return true if the specified function should have a dedicated frame
277 /// pointer register. This is true if the function has variable sized allocas
278 /// or if frame pointer elimination is disabled.
280 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
281 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
284 /// emitARMRegPlusImmediate - Emit a series of instructions to materialize
285 /// a destreg = basereg + immediate in ARM code.
287 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator &MBBI,
289 unsigned DestReg, unsigned BaseReg,
290 int NumBytes, const TargetInstrInfo &TII) {
291 bool isSub = NumBytes < 0;
292 if (isSub) NumBytes = -NumBytes;
295 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
296 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
297 assert(ThisVal && "Didn't extract field correctly");
299 // We will handle these bits from offset, clear them.
300 NumBytes &= ~ThisVal;
302 // Get the properly encoded SOImmVal field.
303 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
304 assert(SOImmVal != -1 && "Bit extraction didn't work?");
306 // Build the new ADD / SUB.
307 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
308 .addReg(BaseReg).addImm(SOImmVal);
313 /// isLowRegister - Returns true if the register is low register r0-r7.
315 static bool isLowRegister(unsigned Reg) {
318 case R0: case R1: case R2: case R3:
319 case R4: case R5: case R6: case R7:
326 /// emitThumbRegPlusImmediate - Emit a series of instructions to materialize
327 /// a destreg = basereg + immediate in Thumb code.
329 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator &MBBI,
331 unsigned DestReg, unsigned BaseReg,
332 int NumBytes, const TargetInstrInfo &TII) {
333 bool isSub = NumBytes < 0;
334 unsigned Bytes = (unsigned)NumBytes;
335 if (isSub) Bytes = -NumBytes;
336 bool isMul4 = (Bytes & 3) == 0;
337 bool isTwoAddr = false;
338 unsigned NumBits = 1;
340 unsigned ExtraOpc = 0;
342 if (DestReg == BaseReg && BaseReg == ARM::SP) {
343 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
344 Bytes >>= 2; // Implicitly multiplied by 4.
346 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
348 } else if (!isSub && BaseReg == ARM::SP) {
351 ExtraOpc = ARM::tADDi3;
353 Bytes >>= 2; // Implicitly multiplied by 4.
357 if (DestReg != BaseReg) {
358 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
359 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
360 unsigned Chunk = (1 << 3) - 1;
361 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
363 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
364 .addReg(BaseReg).addImm(ThisVal);
366 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
371 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
375 unsigned Chunk = (1 << NumBits) - 1;
377 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
379 // Build the new tADD / tSUB.
381 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
383 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
386 if (Opc == ARM::tADDrSPi) {
391 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
398 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
399 .addImm(((unsigned)NumBytes) & 3);
403 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
404 int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
406 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
408 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
411 void ARMRegisterInfo::
412 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator I) const {
415 // If we have alloca, convert as follows:
416 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
417 // ADJCALLSTACKUP -> add, sp, sp, amount
418 MachineInstr *Old = I;
419 unsigned Amount = Old->getOperand(0).getImmedValue();
421 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
422 // We need to keep the stack aligned properly. To do this, we round the
423 // amount of space needed for the outgoing arguments up to the next
424 // alignment boundary.
425 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
426 Amount = (Amount+Align-1)/Align*Align;
428 // Replace the pseudo instruction with a new instruction...
429 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
430 emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
432 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
433 emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
440 /// emitThumbConstant - Emit a series of instructions to materialize a
442 static void emitThumbConstant(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator &MBBI,
444 unsigned DestReg, int Imm,
445 const TargetInstrInfo &TII) {
446 bool isSub = Imm < 0;
447 if (isSub) Imm = -Imm;
449 int Chunk = (1 << 8) - 1;
450 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
452 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal);
454 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
456 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg);
459 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
461 MachineInstr &MI = *II;
462 MachineBasicBlock &MBB = *MI.getParent();
463 MachineFunction &MF = *MBB.getParent();
464 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
465 bool isThumb = AFI->isThumbFunction();
467 while (!MI.getOperand(i).isFrameIndex()) {
469 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
472 unsigned FrameReg = ARM::SP;
473 int FrameIndex = MI.getOperand(i).getFrameIndex();
474 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
475 MF.getFrameInfo()->getStackSize();
477 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
478 Offset -= AFI->getGPRCalleeSavedArea1Offset();
479 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
480 Offset -= AFI->getGPRCalleeSavedArea2Offset();
481 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
482 Offset -= AFI->getDPRCalleeSavedAreaOffset();
483 else if (hasFP(MF)) {
484 // There is alloca()'s in this function, must reference off the frame
486 FrameReg = getFrameRegister(MF);
487 if (STI.isTargetDarwin())
488 Offset -= AFI->getFramePtrSpillOffset();
491 unsigned Opcode = MI.getOpcode();
492 const TargetInstrDescriptor &Desc = TII.get(Opcode);
493 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
496 if (Opcode == ARM::ADDri) {
497 Offset += MI.getOperand(i+1).getImm();
499 // Turn it into a move.
500 MI.setInstrDescriptor(TII.get(ARM::MOVrr));
501 MI.getOperand(i).ChangeToRegister(FrameReg, false);
502 MI.RemoveOperand(i+1);
504 } else if (Offset < 0) {
507 MI.setInstrDescriptor(TII.get(ARM::SUBri));
510 // Common case: small offset, fits into instruction.
511 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
512 if (ImmedOffset != -1) {
513 // Replace the FrameIndex with sp / fp
514 MI.getOperand(i).ChangeToRegister(FrameReg, false);
515 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
519 // Otherwise, we fallback to common code below to form the imm offset with
520 // a sequence of ADDri instructions. First though, pull as much of the imm
521 // into this ADDri as possible.
522 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
523 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31);
525 // We will handle these bits from offset, clear them.
526 Offset &= ~ThisImmVal;
528 // Get the properly encoded SOImmVal field.
529 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
530 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
531 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
532 } else if (Opcode == ARM::tADDrSPi) {
533 Offset += MI.getOperand(i+1).getImm();
534 assert((Offset & 3) == 0 &&
535 "add/sub sp, #imm immediate must be multiple of 4!");
538 // Turn it into a move.
539 MI.setInstrDescriptor(TII.get(ARM::tMOVrr));
540 MI.getOperand(i).ChangeToRegister(FrameReg, false);
541 MI.RemoveOperand(i+1);
545 // Common case: small offset, fits into instruction.
546 if ((Offset & ~255U) == 0) {
547 // Replace the FrameIndex with sp / fp
548 MI.getOperand(i).ChangeToRegister(FrameReg, false);
549 MI.getOperand(i+1).ChangeToImmediate(Offset);
553 unsigned DestReg = MI.getOperand(0).getReg();
555 // Translate r0 = add sp, imm to
556 // r0 = add sp, 255*4
557 // r0 = add r0, (imm - 255*4)
558 MI.getOperand(i).ChangeToRegister(FrameReg, false);
559 MI.getOperand(i+1).ChangeToImmediate(255);
560 Offset = (Offset - 255) << 2;
561 MachineBasicBlock::iterator NII = next(II);
562 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
564 // Translate r0 = add sp, -imm to
565 // r0 = -imm (this is then translated into a series of instructons)
568 emitThumbConstant(MBB, II, DestReg, Offset, TII);
569 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
570 MI.getOperand(i).ChangeToRegister(DestReg, false);
571 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
577 unsigned NumBits = 0;
580 case ARMII::AddrMode2: {
582 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
583 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
588 case ARMII::AddrMode3: {
590 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
591 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
596 case ARMII::AddrMode5: {
598 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
599 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
605 case ARMII::AddrModeTs: {
607 InstrOffs = MI.getOperand(ImmIdx).getImm();
613 std::cerr << "Unsupported addressing mode!\n";
618 Offset += InstrOffs * Scale;
619 assert((Scale == 1 || (Offset & (Scale-1)) == 0) &&
620 "Can't encode this offset!");
626 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
627 int ImmedOffset = Offset / Scale;
628 unsigned Mask = (1 << NumBits) - 1;
629 if ((unsigned)Offset <= Mask * Scale) {
630 // Replace the FrameIndex with sp
631 MI.getOperand(i).ChangeToRegister(FrameReg, false);
633 ImmedOffset |= 1 << NumBits;
634 ImmOp.ChangeToImmediate(ImmedOffset);
638 // Otherwise, it didn't fit. Pull in what we can to simplify the immediate.
639 ImmedOffset = ImmedOffset & Mask;
641 ImmedOffset |= 1 << NumBits;
642 ImmOp.ChangeToImmediate(ImmedOffset);
643 Offset &= ~(Mask*Scale);
646 // If we get here, the immediate doesn't fit into the instruction. We folded
647 // as much as possible above, handle the rest, providing a register that is
649 assert(Offset && "This code isn't needed if offset already handled!");
652 if (TII.isLoad(Opcode)) {
653 // Use the destination register to materialize sp + offset.
654 unsigned TmpReg = MI.getOperand(0).getReg();
655 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
656 isSub ? -Offset : Offset, TII);
657 MI.getOperand(i).ChangeToRegister(TmpReg, false);
658 } else if (TII.isStore(Opcode)) {
659 // FIXME! This is horrific!!! We need register scavenging.
660 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
661 // also a ABI register so it's possible that is is the register that is
662 // being storing here. If that's the case, we do the following:
664 // Use r2 to materialize sp + offset
667 unsigned DestReg = MI.getOperand(0).getReg();
668 unsigned TmpReg = ARM::R3;
669 if (DestReg == ARM::R3) {
670 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
673 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
674 isSub ? -Offset : Offset, TII);
675 MI.getOperand(i).ChangeToRegister(DestReg, false);
676 if (DestReg == ARM::R3)
677 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
679 assert(false && "Unexpected opcode!");
681 // Insert a set of r12 with the full address: r12 = sp + offset
682 // If the offset we have is too large to fit into the instruction, we need
683 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
685 emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
686 isSub ? -Offset : Offset, TII);
687 MI.getOperand(i).ChangeToRegister(ARM::R12, false);
691 void ARMRegisterInfo::
692 processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
693 // This tells PEI to spill the FP as if it is any other callee-save register
694 // to take advantage the eliminateFrameIndex machinery. This also ensures it
695 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
696 // to combine multiple loads / stores.
697 bool CanEliminateFrame = true;
698 bool CS1Spilled = false;
699 bool LRSpilled = false;
700 unsigned NumGPRSpills = 0;
701 SmallVector<unsigned, 4> UnspilledCS1GPRs;
702 SmallVector<unsigned, 4> UnspilledCS2GPRs;
704 // Don't spill FP if the frame can be eliminated. This is determined
705 // by scanning the callee-save registers to see if any is used.
706 const unsigned *CSRegs = getCalleeSavedRegs();
707 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
708 for (unsigned i = 0; CSRegs[i]; ++i) {
709 unsigned Reg = CSRegs[i];
710 bool Spilled = false;
711 if (MF.isPhysRegUsed(Reg)) {
713 CanEliminateFrame = false;
715 // Check alias registers too.
716 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
717 if (MF.isPhysRegUsed(*Aliases)) {
719 CanEliminateFrame = false;
724 if (CSRegClasses[i] == &ARM::GPRRegClass) {
728 if (!STI.isTargetDarwin()) {
736 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
751 if (!STI.isTargetDarwin()) {
752 UnspilledCS1GPRs.push_back(Reg);
762 UnspilledCS1GPRs.push_back(Reg);
765 UnspilledCS2GPRs.push_back(Reg);
772 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
773 bool ForceLRSpill = false;
774 if (!LRSpilled && AFI->isThumbFunction()) {
775 unsigned FnSize = ARM::GetFunctionSize(MF);
776 // Force LR spill if the Thumb function size is > 2048. This enables the
777 // use of BL to implement far jump. If it turns out that it's not needed
778 // the branch fix up path will undo it.
779 if (FnSize >= (1 << 11)) {
780 CanEliminateFrame = false;
785 if (!CanEliminateFrame) {
786 AFI->setHasStackFrame(true);
788 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
789 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
790 if (!LRSpilled && CS1Spilled) {
791 MF.changePhyRegUsed(ARM::LR, true);
793 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
794 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
795 ForceLRSpill = false;
798 if (STI.isTargetDarwin()) {
799 MF.changePhyRegUsed(FramePtr, true);
803 // If stack and double are 8-byte aligned and we are spilling an odd number
804 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
805 // the integer and double callee save areas.
806 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
807 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
808 if (CS1Spilled && !UnspilledCS1GPRs.empty())
809 MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true);
810 else if (!UnspilledCS2GPRs.empty())
811 MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true);
816 MF.changePhyRegUsed(ARM::LR, true);
817 AFI->setLRIsForceSpilled(true);
821 /// Move iterator pass the next bunch of callee save load / store ops for
822 /// the particular spill area (1: integer area 1, 2: integer area 2,
823 /// 3: fp area, 0: don't care).
824 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
825 MachineBasicBlock::iterator &MBBI,
826 int Opc, unsigned Area,
827 const ARMSubtarget &STI) {
828 while (MBBI != MBB.end() &&
829 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
832 unsigned Category = 0;
833 switch (MBBI->getOperand(0).getReg()) {
834 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
838 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
839 Category = STI.isTargetDarwin() ? 2 : 1;
841 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
842 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
849 if (Done || Category != Area)
857 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
858 MachineBasicBlock &MBB = MF.front();
859 MachineBasicBlock::iterator MBBI = MBB.begin();
860 MachineFrameInfo *MFI = MF.getFrameInfo();
861 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
862 bool isThumb = AFI->isThumbFunction();
863 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
864 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
865 unsigned NumBytes = MFI->getStackSize();
866 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
868 // Determine the sizes of each callee-save spill areas and record which frame
869 // belongs to which callee-save spill areas.
870 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
871 int FramePtrSpillFI = 0;
872 if (AFI->hasStackFrame()) {
874 emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
876 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
877 unsigned Reg = CSI[i].getReg();
878 int FI = CSI[i].getFrameIdx();
886 FramePtrSpillFI = FI;
887 AFI->addGPRCalleeSavedArea1Frame(FI);
895 FramePtrSpillFI = FI;
896 if (STI.isTargetDarwin()) {
897 AFI->addGPRCalleeSavedArea2Frame(FI);
900 AFI->addGPRCalleeSavedArea1Frame(FI);
905 AFI->addDPRCalleeSavedAreaFrame(FI);
910 if (Align == 8 && (GPRCS1Size & 7) != 0)
911 // Pad CS1 to ensure proper alignment.
915 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
916 emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
917 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
918 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
921 // Point FP to the stack slot that contains the previous FP.
922 if (STI.isTargetDarwin())
923 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
924 .addFrameIndex(FramePtrSpillFI).addImm(0);
927 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
928 emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
930 // Build the new SUBri to adjust SP for FP callee-save spill area.
931 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
932 emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
936 // Determine starting offsets of spill areas.
937 if (AFI->hasStackFrame()) {
938 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
939 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
940 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
941 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
942 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
943 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
944 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
946 NumBytes = DPRCSOffset;
948 // Insert it after all the callee-save spills.
950 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
951 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
954 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
956 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
957 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
958 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
961 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
962 for (unsigned i = 0; CSRegs[i]; ++i)
963 if (Reg == CSRegs[i])
968 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
969 return ((MI->getOpcode() == ARM::FLDD ||
970 MI->getOpcode() == ARM::LDR ||
971 MI->getOpcode() == ARM::tLDRspi) &&
972 MI->getOperand(1).isFrameIndex() &&
973 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
976 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
977 MachineBasicBlock &MBB) const {
978 MachineBasicBlock::iterator MBBI = prior(MBB.end());
979 assert((MBBI->getOpcode() == ARM::BX_RET ||
980 MBBI->getOpcode() == ARM::tBX_RET ||
981 MBBI->getOpcode() == ARM::tPOP_RET) &&
982 "Can only insert epilog into returning blocks");
984 MachineFrameInfo *MFI = MF.getFrameInfo();
985 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
986 bool isThumb = AFI->isThumbFunction();
987 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
988 int NumBytes = (int)MFI->getStackSize();
989 if (AFI->hasStackFrame()) {
990 // Unwind MBBI to point to first LDR / FLDD.
991 const unsigned *CSRegs = getCalleeSavedRegs();
992 if (MBBI != MBB.begin()) {
995 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
996 if (!isCSRestore(MBBI, CSRegs))
1000 // Move SP to start of FP callee save spill area.
1001 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1002 AFI->getGPRCalleeSavedArea2Size() +
1003 AFI->getDPRCalleeSavedAreaSize());
1005 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1007 if (STI.isTargetDarwin()) {
1008 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1009 // Reset SP based on frame pointer only if the stack frame extends beyond
1010 // frame pointer stack slot.
1011 if (AFI->getGPRCalleeSavedArea2Size() ||
1012 AFI->getDPRCalleeSavedAreaSize() ||
1013 AFI->getDPRCalleeSavedAreaOffset())
1015 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1018 BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr);
1019 } else if (NumBytes) {
1020 emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
1023 // Move SP to start of integer callee save spill area 2.
1024 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1025 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
1027 // Move SP to start of integer callee save spill area 1.
1028 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1029 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
1031 // Move SP to SP upon entry to the function.
1032 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1033 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
1037 emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
1038 } else if (NumBytes != 0) {
1039 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1043 unsigned ARMRegisterInfo::getRARegister() const {
1047 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1048 return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
1051 #include "ARMGenRegisterInfo.inc"