1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
92 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
93 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
97 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
101 /// emitLoadConstPool - Emits a load from constpool to materialize the
102 /// specified immediate.
103 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator &MBBI,
105 unsigned DestReg, int Val,
106 unsigned Pred, unsigned PredReg,
107 const TargetInstrInfo *TII,
108 bool isThumb) const {
109 MachineFunction &MF = *MBB.getParent();
110 MachineConstantPool *ConstantPool = MF.getConstantPool();
111 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
112 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
114 BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
116 BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
117 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
120 /// isLowRegister - Returns true if the register is low register r0-r7.
122 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
125 case R0: case R1: case R2: case R3:
126 case R4: case R5: case R6: case R7:
134 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
135 static const unsigned CalleeSavedRegs[] = {
136 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
137 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
139 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
140 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
144 static const unsigned DarwinCalleeSavedRegs[] = {
145 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
146 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
148 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
149 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
152 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
155 const TargetRegisterClass* const *
156 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
157 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
158 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
159 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
160 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
162 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
163 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
166 return CalleeSavedRegClasses;
169 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
170 // FIXME: avoid re-calculating this everytime.
171 BitVector Reserved(getNumRegs());
172 Reserved.set(ARM::SP);
173 Reserved.set(ARM::PC);
174 if (STI.isTargetDarwin() || hasFP(MF))
175 Reserved.set(FramePtr);
176 // Some targets reserve R9.
177 if (STI.isR9Reserved())
178 Reserved.set(ARM::R9);
183 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
191 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
195 return STI.isR9Reserved();
202 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
203 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
204 return ThumbRegScavenging || !AFI->isThumbFunction();
207 /// hasFP - Return true if the specified function should have a dedicated frame
208 /// pointer register. This is true if the function has variable sized allocas
209 /// or if frame pointer elimination is disabled.
211 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
212 const MachineFrameInfo *MFI = MF.getFrameInfo();
213 return NoFramePointerElim || MFI->hasVarSizedObjects();
216 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
217 // not required, we reserve argument space for call sites in the function
218 // immediately on entry to the current function. This eliminates the need for
219 // add/sub sp brackets around call sites. Returns true if the call frame is
220 // included as part of the stack frame.
221 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
222 const MachineFrameInfo *FFI = MF.getFrameInfo();
223 unsigned CFSize = FFI->getMaxCallFrameSize();
224 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
225 // It's not always a good idea to include the call frame as part of the
226 // stack frame. ARM (especially Thumb) has small immediate offset to
227 // address the stack frame. So a large call frame can cause poor codegen
228 // and may even makes it impossible to scavenge a register.
229 if (AFI->isThumbFunction()) {
230 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
233 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
236 return !MF.getFrameInfo()->hasVarSizedObjects();
239 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
240 /// a destreg = basereg + immediate in ARM code.
242 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator &MBBI,
244 unsigned DestReg, unsigned BaseReg, int NumBytes,
245 ARMCC::CondCodes Pred, unsigned PredReg,
246 const TargetInstrInfo &TII) {
247 bool isSub = NumBytes < 0;
248 if (isSub) NumBytes = -NumBytes;
251 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
252 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
253 assert(ThisVal && "Didn't extract field correctly");
255 // We will handle these bits from offset, clear them.
256 NumBytes &= ~ThisVal;
258 // Get the properly encoded SOImmVal field.
259 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
260 assert(SOImmVal != -1 && "Bit extraction didn't work?");
262 // Build the new ADD / SUB.
263 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
264 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
265 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
270 /// calcNumMI - Returns the number of instructions required to materialize
271 /// the specific add / sub r, c instruction.
272 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
273 unsigned NumBits, unsigned Scale) {
275 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
277 if (Opc == ARM::tADDrSPi) {
278 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
282 Scale = 1; // Followed by a number of tADDi8.
283 Chunk = ((1 << NumBits) - 1) * Scale;
286 NumMIs += Bytes / Chunk;
287 if ((Bytes % Chunk) != 0)
294 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
295 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
296 /// in a register using mov / mvn sequences or load the immediate from a
299 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
300 MachineBasicBlock::iterator &MBBI,
301 unsigned DestReg, unsigned BaseReg,
302 int NumBytes, bool CanChangeCC,
303 const TargetInstrInfo &TII,
304 const ARMRegisterInfo& MRI) {
305 bool isHigh = !MRI.isLowRegister(DestReg) ||
306 (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
308 // Subtract doesn't have high register version. Load the negative value
309 // if either base or dest register is a high register. Also, if do not
310 // issue sub as part of the sequence if condition register is to be
312 if (NumBytes < 0 && !isHigh && CanChangeCC) {
314 NumBytes = -NumBytes;
316 unsigned LdReg = DestReg;
317 if (DestReg == ARM::SP) {
318 assert(BaseReg == ARM::SP && "Unexpected!");
320 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
321 .addReg(ARM::R3, false, false, true);
324 if (NumBytes <= 255 && NumBytes >= 0)
325 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
326 else if (NumBytes < 0 && NumBytes >= -255) {
327 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
328 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
329 .addReg(LdReg, false, false, true);
331 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true);
334 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
335 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
336 if (DestReg == ARM::SP || isSub)
337 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
339 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
340 if (DestReg == ARM::SP)
341 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
342 .addReg(ARM::R12, false, false, true);
345 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
346 /// a destreg = basereg + immediate in Thumb code.
348 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
349 MachineBasicBlock::iterator &MBBI,
350 unsigned DestReg, unsigned BaseReg,
351 int NumBytes, const TargetInstrInfo &TII,
352 const ARMRegisterInfo& MRI) {
353 bool isSub = NumBytes < 0;
354 unsigned Bytes = (unsigned)NumBytes;
355 if (isSub) Bytes = -NumBytes;
356 bool isMul4 = (Bytes & 3) == 0;
357 bool isTwoAddr = false;
358 bool DstNotEqBase = false;
359 unsigned NumBits = 1;
364 if (DestReg == BaseReg && BaseReg == ARM::SP) {
365 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
368 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
370 } else if (!isSub && BaseReg == ARM::SP) {
373 // r1 = add sp, 100 * 4
377 ExtraOpc = ARM::tADDi3;
386 if (DestReg != BaseReg)
389 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
393 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
394 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
395 if (NumMIs > Threshold) {
396 // This will expand into too many instructions. Load the immediate from a
398 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI);
403 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
404 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
405 unsigned Chunk = (1 << 3) - 1;
406 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
408 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
409 .addReg(BaseReg, false, false, true).addImm(ThisVal);
411 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
412 .addReg(BaseReg, false, false, true);
417 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
419 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
422 // Build the new tADD / tSUB.
424 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
426 bool isKill = BaseReg != ARM::SP;
427 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
428 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
431 if (Opc == ARM::tADDrSPi) {
437 Chunk = ((1 << NumBits) - 1) * Scale;
438 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
445 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
446 .addReg(DestReg, false, false, true)
447 .addImm(((unsigned)NumBytes) & 3);
451 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
452 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
453 bool isThumb, const TargetInstrInfo &TII,
454 const ARMRegisterInfo& MRI) {
456 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI);
458 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
462 void ARMRegisterInfo::
463 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator I) const {
465 if (!hasReservedCallFrame(MF)) {
466 // If we have alloca, convert as follows:
467 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
468 // ADJCALLSTACKUP -> add, sp, sp, amount
469 MachineInstr *Old = I;
470 unsigned Amount = Old->getOperand(0).getImm();
472 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
473 // We need to keep the stack aligned properly. To do this, we round the
474 // amount of space needed for the outgoing arguments up to the next
475 // alignment boundary.
476 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
477 Amount = (Amount+Align-1)/Align*Align;
479 // Replace the pseudo instruction with a new instruction...
480 unsigned Opc = Old->getOpcode();
481 bool isThumb = AFI->isThumbFunction();
482 ARMCC::CondCodes Pred = isThumb
483 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
484 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
485 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
486 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
487 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this);
489 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
490 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
491 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
492 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this);
499 /// emitThumbConstant - Emit a series of instructions to materialize a
501 static void emitThumbConstant(MachineBasicBlock &MBB,
502 MachineBasicBlock::iterator &MBBI,
503 unsigned DestReg, int Imm,
504 const TargetInstrInfo &TII,
505 const ARMRegisterInfo& MRI) {
506 bool isSub = Imm < 0;
507 if (isSub) Imm = -Imm;
509 int Chunk = (1 << 8) - 1;
510 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
512 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
514 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI);
516 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
517 .addReg(DestReg, false, false, true);
520 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
521 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
522 /// register first and then a spilled callee-saved register if that fails.
524 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
525 ARMFunctionInfo *AFI) {
526 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
528 // Try a already spilled CS register.
529 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
534 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
535 int SPAdj, RegScavenger *RS) const{
537 MachineInstr &MI = *II;
538 MachineBasicBlock &MBB = *MI.getParent();
539 MachineFunction &MF = *MBB.getParent();
540 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
541 bool isThumb = AFI->isThumbFunction();
543 while (!MI.getOperand(i).isFI()) {
545 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
548 unsigned FrameReg = ARM::SP;
549 int FrameIndex = MI.getOperand(i).getIndex();
550 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
551 MF.getFrameInfo()->getStackSize() + SPAdj;
553 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
554 Offset -= AFI->getGPRCalleeSavedArea1Offset();
555 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
556 Offset -= AFI->getGPRCalleeSavedArea2Offset();
557 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
558 Offset -= AFI->getDPRCalleeSavedAreaOffset();
559 else if (hasFP(MF)) {
560 assert(SPAdj == 0 && "Unexpected");
561 // There is alloca()'s in this function, must reference off the frame
563 FrameReg = getFrameRegister(MF);
564 Offset -= AFI->getFramePtrSpillOffset();
567 unsigned Opcode = MI.getOpcode();
568 const TargetInstrDesc &Desc = MI.getDesc();
569 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
572 if (Opcode == ARM::ADDri) {
573 Offset += MI.getOperand(i+1).getImm();
575 // Turn it into a move.
576 MI.setDesc(TII.get(ARM::MOVr));
577 MI.getOperand(i).ChangeToRegister(FrameReg, false);
578 MI.RemoveOperand(i+1);
580 } else if (Offset < 0) {
583 MI.setDesc(TII.get(ARM::SUBri));
586 // Common case: small offset, fits into instruction.
587 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
588 if (ImmedOffset != -1) {
589 // Replace the FrameIndex with sp / fp
590 MI.getOperand(i).ChangeToRegister(FrameReg, false);
591 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
595 // Otherwise, we fallback to common code below to form the imm offset with
596 // a sequence of ADDri instructions. First though, pull as much of the imm
597 // into this ADDri as possible.
598 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
599 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
601 // We will handle these bits from offset, clear them.
602 Offset &= ~ThisImmVal;
604 // Get the properly encoded SOImmVal field.
605 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
606 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
607 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
608 } else if (Opcode == ARM::tADDrSPi) {
609 Offset += MI.getOperand(i+1).getImm();
611 // Can't use tADDrSPi if it's based off the frame pointer.
612 unsigned NumBits = 0;
614 if (FrameReg != ARM::SP) {
615 Opcode = ARM::tADDi3;
616 MI.setDesc(TII.get(ARM::tADDi3));
621 assert((Offset & 3) == 0 &&
622 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
626 // Turn it into a move.
627 MI.setDesc(TII.get(ARM::tMOVr));
628 MI.getOperand(i).ChangeToRegister(FrameReg, false);
629 MI.RemoveOperand(i+1);
633 // Common case: small offset, fits into instruction.
634 unsigned Mask = (1 << NumBits) - 1;
635 if (((Offset / Scale) & ~Mask) == 0) {
636 // Replace the FrameIndex with sp / fp
637 MI.getOperand(i).ChangeToRegister(FrameReg, false);
638 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
642 unsigned DestReg = MI.getOperand(0).getReg();
643 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
644 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
645 // MI would expand into a large number of instructions. Don't try to
646 // simplify the immediate.
648 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this);
654 // Translate r0 = add sp, imm to
655 // r0 = add sp, 255*4
656 // r0 = add r0, (imm - 255*4)
657 MI.getOperand(i).ChangeToRegister(FrameReg, false);
658 MI.getOperand(i+1).ChangeToImmediate(Mask);
659 Offset = (Offset - Mask * Scale);
660 MachineBasicBlock::iterator NII = next(II);
661 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this);
663 // Translate r0 = add sp, -imm to
664 // r0 = -imm (this is then translated into a series of instructons)
666 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this);
667 MI.setDesc(TII.get(ARM::tADDhirr));
668 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
669 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
675 unsigned NumBits = 0;
678 case ARMII::AddrMode2: {
680 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
681 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
686 case ARMII::AddrMode3: {
688 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
689 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
694 case ARMII::AddrMode5: {
696 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
697 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
703 case ARMII::AddrModeTs: {
705 InstrOffs = MI.getOperand(ImmIdx).getImm();
706 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
711 assert(0 && "Unsupported addressing mode!");
716 Offset += InstrOffs * Scale;
717 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
718 if (Offset < 0 && !isThumb) {
723 // Common case: small offset, fits into instruction.
724 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
725 int ImmedOffset = Offset / Scale;
726 unsigned Mask = (1 << NumBits) - 1;
727 if ((unsigned)Offset <= Mask * Scale) {
728 // Replace the FrameIndex with sp
729 MI.getOperand(i).ChangeToRegister(FrameReg, false);
731 ImmedOffset |= 1 << NumBits;
732 ImmOp.ChangeToImmediate(ImmedOffset);
736 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
737 if (AddrMode == ARMII::AddrModeTs) {
738 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
739 // a different base register.
741 Mask = (1 << NumBits) - 1;
743 // If this is a thumb spill / restore, we will be using a constpool load to
744 // materialize the offset.
745 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
746 ImmOp.ChangeToImmediate(0);
748 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
749 ImmedOffset = ImmedOffset & Mask;
751 ImmedOffset |= 1 << NumBits;
752 ImmOp.ChangeToImmediate(ImmedOffset);
753 Offset &= ~(Mask*Scale);
757 // If we get here, the immediate doesn't fit into the instruction. We folded
758 // as much as possible above, handle the rest, providing a register that is
760 assert(Offset && "This code isn't needed if offset already handled!");
763 if (Desc.isSimpleLoad()) {
764 // Use the destination register to materialize sp + offset.
765 unsigned TmpReg = MI.getOperand(0).getReg();
767 if (Opcode == ARM::tRestore) {
768 if (FrameReg == ARM::SP)
769 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
770 Offset, false, TII, *this);
772 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
776 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
777 MI.setDesc(TII.get(ARM::tLDR));
778 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
780 // Use [reg, reg] addrmode.
781 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
782 else // tLDR has an extra register operand.
783 MI.addOperand(MachineOperand::CreateReg(0, false));
784 } else if (Desc.mayStore()) {
785 // FIXME! This is horrific!!! We need register scavenging.
786 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
787 // also a ABI register so it's possible that is is the register that is
788 // being storing here. If that's the case, we do the following:
790 // Use r2 to materialize sp + offset
793 unsigned ValReg = MI.getOperand(0).getReg();
794 unsigned TmpReg = ARM::R3;
796 if (ValReg == ARM::R3) {
797 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
798 .addReg(ARM::R2, false, false, true);
801 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
802 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
803 .addReg(ARM::R3, false, false, true);
804 if (Opcode == ARM::tSpill) {
805 if (FrameReg == ARM::SP)
806 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
807 Offset, false, TII, *this);
809 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
813 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
814 MI.setDesc(TII.get(ARM::tSTR));
815 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
816 if (UseRR) // Use [reg, reg] addrmode.
817 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
818 else // tSTR has an extra register operand.
819 MI.addOperand(MachineOperand::CreateReg(0, false));
821 MachineBasicBlock::iterator NII = next(II);
822 if (ValReg == ARM::R3)
823 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
824 .addReg(ARM::R12, false, false, true);
825 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
826 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
827 .addReg(ARM::R12, false, false, true);
829 assert(false && "Unexpected opcode!");
831 // Insert a set of r12 with the full address: r12 = sp + offset
832 // If the offset we have is too large to fit into the instruction, we need
833 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
835 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
837 // No register is "free". Scavenge a register.
838 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
839 int PIdx = MI.findFirstPredOperandIdx();
840 ARMCC::CondCodes Pred = (PIdx == -1)
841 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
842 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
843 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
844 isSub ? -Offset : Offset, Pred, PredReg, TII);
845 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
849 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
850 const MachineFrameInfo *FFI = MF.getFrameInfo();
852 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
853 int FixedOff = -FFI->getObjectOffset(i);
854 if (FixedOff > Offset) Offset = FixedOff;
856 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
857 if (FFI->isDeadObjectIndex(i))
859 Offset += FFI->getObjectSize(i);
860 unsigned Align = FFI->getObjectAlignment(i);
861 // Adjust to alignment boundary
862 Offset = (Offset+Align-1)/Align*Align;
864 return (unsigned)Offset;
868 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
869 RegScavenger *RS) const {
870 // This tells PEI to spill the FP as if it is any other callee-save register
871 // to take advantage the eliminateFrameIndex machinery. This also ensures it
872 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
873 // to combine multiple loads / stores.
874 bool CanEliminateFrame = true;
875 bool CS1Spilled = false;
876 bool LRSpilled = false;
877 unsigned NumGPRSpills = 0;
878 SmallVector<unsigned, 4> UnspilledCS1GPRs;
879 SmallVector<unsigned, 4> UnspilledCS2GPRs;
880 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
882 // Don't spill FP if the frame can be eliminated. This is determined
883 // by scanning the callee-save registers to see if any is used.
884 const unsigned *CSRegs = getCalleeSavedRegs();
885 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
886 for (unsigned i = 0; CSRegs[i]; ++i) {
887 unsigned Reg = CSRegs[i];
888 bool Spilled = false;
889 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
890 AFI->setCSRegisterIsSpilled(Reg);
892 CanEliminateFrame = false;
894 // Check alias registers too.
895 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
896 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
898 CanEliminateFrame = false;
903 if (CSRegClasses[i] == &ARM::GPRRegClass) {
907 if (!STI.isTargetDarwin()) {
914 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
929 if (!STI.isTargetDarwin()) {
930 UnspilledCS1GPRs.push_back(Reg);
940 UnspilledCS1GPRs.push_back(Reg);
943 UnspilledCS2GPRs.push_back(Reg);
950 bool ForceLRSpill = false;
951 if (!LRSpilled && AFI->isThumbFunction()) {
952 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
953 // Force LR to be spilled if the Thumb function size is > 2048. This enables
954 // use of BL to implement far jump. If it turns out that it's not needed
955 // then the branch fix up path will undo it.
956 if (FnSize >= (1 << 11)) {
957 CanEliminateFrame = false;
962 bool ExtraCSSpill = false;
963 if (!CanEliminateFrame || hasFP(MF)) {
964 AFI->setHasStackFrame(true);
966 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
967 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
968 if (!LRSpilled && CS1Spilled) {
969 MF.getRegInfo().setPhysRegUsed(ARM::LR);
970 AFI->setCSRegisterIsSpilled(ARM::LR);
972 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
973 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
974 ForceLRSpill = false;
978 // Darwin ABI requires FP to point to the stack slot that contains the
980 if (STI.isTargetDarwin() || hasFP(MF)) {
981 MF.getRegInfo().setPhysRegUsed(FramePtr);
985 // If stack and double are 8-byte aligned and we are spilling an odd number
986 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
987 // the integer and double callee save areas.
988 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
989 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
990 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
991 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
992 unsigned Reg = UnspilledCS1GPRs[i];
993 // Don't spiil high register if the function is thumb
994 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
995 MF.getRegInfo().setPhysRegUsed(Reg);
996 AFI->setCSRegisterIsSpilled(Reg);
997 if (!isReservedReg(MF, Reg))
1002 } else if (!UnspilledCS2GPRs.empty() &&
1003 !AFI->isThumbFunction()) {
1004 unsigned Reg = UnspilledCS2GPRs.front();
1005 MF.getRegInfo().setPhysRegUsed(Reg);
1006 AFI->setCSRegisterIsSpilled(Reg);
1007 if (!isReservedReg(MF, Reg))
1008 ExtraCSSpill = true;
1012 // Estimate if we might need to scavenge a register at some point in order
1013 // to materialize a stack offset. If so, either spill one additiona
1014 // callee-saved register or reserve a special spill slot to facilitate
1015 // register scavenging.
1016 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1017 MachineFrameInfo *MFI = MF.getFrameInfo();
1018 unsigned Size = estimateStackSize(MF, MFI);
1019 unsigned Limit = (1 << 12) - 1;
1020 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1021 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1022 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1023 if (I->getOperand(i).isFI()) {
1024 unsigned Opcode = I->getOpcode();
1025 const TargetInstrDesc &Desc = TII.get(Opcode);
1026 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1027 if (AddrMode == ARMII::AddrMode3) {
1028 Limit = (1 << 8) - 1;
1029 goto DoneEstimating;
1030 } else if (AddrMode == ARMII::AddrMode5) {
1031 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1032 if (ThisLimit < Limit)
1038 if (Size >= Limit) {
1039 // If any non-reserved CS register isn't spilled, just spill one or two
1040 // extra. That should take care of it!
1041 unsigned NumExtras = TargetAlign / 4;
1042 SmallVector<unsigned, 2> Extras;
1043 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1044 unsigned Reg = UnspilledCS1GPRs.back();
1045 UnspilledCS1GPRs.pop_back();
1046 if (!isReservedReg(MF, Reg)) {
1047 Extras.push_back(Reg);
1051 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1052 unsigned Reg = UnspilledCS2GPRs.back();
1053 UnspilledCS2GPRs.pop_back();
1054 if (!isReservedReg(MF, Reg)) {
1055 Extras.push_back(Reg);
1059 if (Extras.size() && NumExtras == 0) {
1060 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1061 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1062 AFI->setCSRegisterIsSpilled(Extras[i]);
1065 // Reserve a slot closest to SP or frame pointer.
1066 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1067 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1068 RC->getAlignment()));
1075 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1076 AFI->setCSRegisterIsSpilled(ARM::LR);
1077 AFI->setLRIsSpilledForFarJump(true);
1081 /// Move iterator pass the next bunch of callee save load / store ops for
1082 /// the particular spill area (1: integer area 1, 2: integer area 2,
1083 /// 3: fp area, 0: don't care).
1084 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1085 MachineBasicBlock::iterator &MBBI,
1086 int Opc, unsigned Area,
1087 const ARMSubtarget &STI) {
1088 while (MBBI != MBB.end() &&
1089 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1092 unsigned Category = 0;
1093 switch (MBBI->getOperand(0).getReg()) {
1094 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1098 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1099 Category = STI.isTargetDarwin() ? 2 : 1;
1101 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1102 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1109 if (Done || Category != Area)
1117 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1118 MachineBasicBlock &MBB = MF.front();
1119 MachineBasicBlock::iterator MBBI = MBB.begin();
1120 MachineFrameInfo *MFI = MF.getFrameInfo();
1121 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1122 bool isThumb = AFI->isThumbFunction();
1123 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1124 unsigned NumBytes = MFI->getStackSize();
1125 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1128 // Check if R3 is live in. It might have to be used as a scratch register.
1129 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1130 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1131 if (I->first == ARM::R3) {
1132 AFI->setR3IsLiveIn(true);
1137 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1138 NumBytes = (NumBytes + 3) & ~3;
1139 MFI->setStackSize(NumBytes);
1142 // Determine the sizes of each callee-save spill areas and record which frame
1143 // belongs to which callee-save spill areas.
1144 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1145 int FramePtrSpillFI = 0;
1148 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
1150 if (!AFI->hasStackFrame()) {
1152 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1156 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1157 unsigned Reg = CSI[i].getReg();
1158 int FI = CSI[i].getFrameIdx();
1165 if (Reg == FramePtr)
1166 FramePtrSpillFI = FI;
1167 AFI->addGPRCalleeSavedArea1Frame(FI);
1174 if (Reg == FramePtr)
1175 FramePtrSpillFI = FI;
1176 if (STI.isTargetDarwin()) {
1177 AFI->addGPRCalleeSavedArea2Frame(FI);
1180 AFI->addGPRCalleeSavedArea1Frame(FI);
1185 AFI->addDPRCalleeSavedAreaFrame(FI);
1191 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1192 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this);
1193 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1194 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1197 // Darwin ABI requires FP to point to the stack slot that contains the
1199 if (STI.isTargetDarwin() || hasFP(MF)) {
1200 MachineInstrBuilder MIB =
1201 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1202 .addFrameIndex(FramePtrSpillFI).addImm(0);
1203 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1207 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1208 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this);
1210 // Build the new SUBri to adjust SP for FP callee-save spill area.
1211 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1212 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this);
1215 // Determine starting offsets of spill areas.
1216 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1217 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1218 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1219 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1220 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1221 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1222 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1224 NumBytes = DPRCSOffset;
1226 // Insert it after all the callee-save spills.
1228 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1229 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1232 if(STI.isTargetELF() && hasFP(MF)) {
1233 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1234 AFI->getFramePtrSpillOffset());
1237 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1238 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1239 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1242 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1243 for (unsigned i = 0; CSRegs[i]; ++i)
1244 if (Reg == CSRegs[i])
1249 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1250 return ((MI->getOpcode() == ARM::FLDD ||
1251 MI->getOpcode() == ARM::LDR ||
1252 MI->getOpcode() == ARM::tRestore) &&
1253 MI->getOperand(1).isFI() &&
1254 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1257 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1258 MachineBasicBlock &MBB) const {
1259 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1260 assert((MBBI->getOpcode() == ARM::BX_RET ||
1261 MBBI->getOpcode() == ARM::tBX_RET ||
1262 MBBI->getOpcode() == ARM::tPOP_RET) &&
1263 "Can only insert epilog into returning blocks");
1265 MachineFrameInfo *MFI = MF.getFrameInfo();
1266 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1267 bool isThumb = AFI->isThumbFunction();
1268 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1269 int NumBytes = (int)MFI->getStackSize();
1270 if (!AFI->hasStackFrame()) {
1272 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1274 // Unwind MBBI to point to first LDR / FLDD.
1275 const unsigned *CSRegs = getCalleeSavedRegs();
1276 if (MBBI != MBB.begin()) {
1279 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1280 if (!isCSRestore(MBBI, CSRegs))
1284 // Move SP to start of FP callee save spill area.
1285 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1286 AFI->getGPRCalleeSavedArea2Size() +
1287 AFI->getDPRCalleeSavedAreaSize());
1290 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1291 // Reset SP based on frame pointer only if the stack frame extends beyond
1292 // frame pointer stack slot or target is ELF and the function has FP.
1294 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1297 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1299 if (MBBI->getOpcode() == ARM::tBX_RET &&
1300 &MBB.front() != MBBI &&
1301 prior(MBBI)->getOpcode() == ARM::tPOP) {
1302 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1303 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1305 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
1308 // Darwin ABI requires FP to point to the stack slot that contains the
1310 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1311 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1312 // Reset SP based on frame pointer only if the stack frame extends beyond
1313 // frame pointer stack slot or target is ELF and the function has FP.
1314 if (AFI->getGPRCalleeSavedArea2Size() ||
1315 AFI->getDPRCalleeSavedAreaSize() ||
1316 AFI->getDPRCalleeSavedAreaOffset()||
1319 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1321 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1323 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1324 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1326 } else if (NumBytes) {
1327 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
1330 // Move SP to start of integer callee save spill area 2.
1331 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1332 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1335 // Move SP to start of integer callee save spill area 1.
1336 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1337 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1340 // Move SP to SP upon entry to the function.
1341 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1342 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1347 if (VARegSaveSize) {
1349 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1350 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1351 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1353 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
1356 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1362 unsigned ARMRegisterInfo::getRARegister() const {
1366 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1367 if (STI.isTargetDarwin() || hasFP(MF))
1368 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1373 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1374 assert(0 && "What is the exception register");
1378 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1379 assert(0 && "What is the exception handler register");
1383 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1384 assert(0 && "What is the dwarf register number");
1388 #include "ARMGenRegisterInfo.inc"