1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMRegisterInfo.h"
17 #include "ARMCommon.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineLocation.h"
22 #include "llvm/Type.h"
23 #include "llvm/Target/TargetFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/ADT/STLExtras.h"
30 // hasFP - Return true if the specified function should have a dedicated frame
31 // pointer register. This is true if the function has variable sized allocas or
32 // if frame pointer elimination is disabled.
34 static bool hasFP(const MachineFunction &MF) {
35 const MachineFrameInfo *MFI = MF.getFrameInfo();
36 return NoFramePointerElim || MFI->hasVarSizedObjects();
39 static void splitInstructionWithImmediate(MachineBasicBlock &BB,
40 MachineBasicBlock::iterator I,
41 const TargetInstrDescriptor &TID,
45 std::vector<unsigned> immediatePieces = splitImmediate(immediate);
46 std::vector<unsigned>::iterator it;
47 for (it=immediatePieces.begin(); it != immediatePieces.end(); ++it){
48 BuildMI(BB, I, TID, DestReg).addReg(OrigReg)
49 .addImm(*it).addImm(0).addImm(ARMShift::LSL);
53 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
54 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
58 void ARMRegisterInfo::
59 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
60 unsigned SrcReg, int FI,
61 const TargetRegisterClass *RC) const {
62 assert (RC == ARM::IntRegsRegisterClass);
63 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
66 void ARMRegisterInfo::
67 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
68 unsigned DestReg, int FI,
69 const TargetRegisterClass *RC) const {
70 assert (RC == ARM::IntRegsRegisterClass);
71 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
74 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator I,
76 unsigned DestReg, unsigned SrcReg,
77 const TargetRegisterClass *RC) const {
78 assert(RC == ARM::IntRegsRegisterClass ||
79 RC == ARM::FPRegsRegisterClass ||
80 RC == ARM::DFPRegsRegisterClass);
82 if (RC == ARM::IntRegsRegisterClass)
83 BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
84 .addImm(ARMShift::LSL);
85 else if (RC == ARM::FPRegsRegisterClass)
86 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
88 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
91 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
97 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
98 static const unsigned CalleeSavedRegs[] = {
99 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
100 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
103 return CalleeSavedRegs;
106 const TargetRegisterClass* const *
107 ARMRegisterInfo::getCalleeSavedRegClasses() const {
108 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
109 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
110 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
111 &ARM::IntRegsRegClass, 0
113 return CalleeSavedRegClasses;
116 void ARMRegisterInfo::
117 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator I) const {
120 MachineInstr *Old = I;
121 unsigned Amount = Old->getOperand(0).getImmedValue();
123 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
124 Amount = (Amount+Align-1)/Align*Align;
126 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
127 // sub sp, sp, amount
128 splitInstructionWithImmediate(MBB, I, TII.get(ARM::SUB), ARM::R13,
131 // add sp, sp, amount
132 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
133 splitInstructionWithImmediate(MBB, I, TII.get(ARM::ADD), ARM::R13,
142 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
143 MachineInstr &MI = *II;
144 MachineBasicBlock &MBB = *MI.getParent();
145 MachineFunction &MF = *MBB.getParent();
147 assert (MI.getOpcode() == ARM::LDR ||
148 MI.getOpcode() == ARM::STR ||
149 MI.getOpcode() == ARM::ADD);
151 unsigned FrameIdx = 1;
154 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
156 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
157 MI.getOperand(OffIdx).getImmedValue();
159 unsigned StackSize = MF.getFrameInfo()->getStackSize();
163 assert (Offset >= 0);
164 unsigned BaseRegister = hasFP(MF) ? ARM::R11 : ARM::R13;
166 // Replace the FrameIndex with r13
167 MI.getOperand(FrameIdx).ChangeToRegister(BaseRegister, false);
168 // Replace the ldr offset with Offset
169 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
171 // Insert a set of r12 with the full address
172 // r12 = r13 + offset
173 MachineBasicBlock *MBB2 = MI.getParent();
174 splitInstructionWithImmediate(*MBB2, II, TII.get(ARM::ADD), ARM::R12,
175 BaseRegister, Offset);
177 // Replace the FrameIndex with r12
178 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
182 void ARMRegisterInfo::
183 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
185 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
186 MachineBasicBlock &MBB = MF.front();
187 MachineBasicBlock::iterator MBBI = MBB.begin();
188 MachineFrameInfo *MFI = MF.getFrameInfo();
189 int NumBytes = (int) MFI->getStackSize();
191 bool HasFP = hasFP(MF);
193 if (MFI->hasCalls()) {
194 // We reserve argument space for call sites in the function immediately on
195 // entry to the current function. This eliminates the need for add/sub
196 // brackets around call sites.
197 NumBytes += MFI->getMaxCallFrameSize();
201 // Add space for storing the FP
205 NumBytes = ((NumBytes + 7) / 8) * 8;
207 MFI->setStackSize(NumBytes);
209 //sub sp, sp, #NumBytes
210 splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
215 BuildMI(MBB, MBBI, TII.get(ARM::STR))
216 .addReg(ARM::R11).addReg(ARM::R13).addImm(0);
217 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
218 addImm(ARMShift::LSL);
222 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
223 MachineBasicBlock &MBB) const {
224 MachineBasicBlock::iterator MBBI = prior(MBB.end());
225 assert(MBBI->getOpcode() == ARM::bx &&
226 "Can only insert epilog into returning blocks");
228 MachineFrameInfo *MFI = MF.getFrameInfo();
229 int NumBytes = (int) MFI->getStackSize();
232 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
233 addImm(ARMShift::LSL);
234 BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
237 //add sp, sp, #NumBytes
238 splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
243 unsigned ARMRegisterInfo::getRARegister() const {
247 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
248 return hasFP(MF) ? ARM::R11 : ARM::R13;
251 #include "ARMGenRegisterInfo.inc"