1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum,
91 assert(0 && "Unknown ARM register!");
93 case R0: case D0: return 0;
94 case R1: case D1: return 1;
95 case R2: case D2: return 2;
96 case R3: case D3: return 3;
97 case R4: case D4: return 4;
98 case R5: case D5: return 5;
99 case R6: case D6: return 6;
100 case R7: case D7: return 7;
101 case R8: case D8: return 8;
102 case R9: case D9: return 9;
103 case R10: case D10: return 10;
104 case R11: case D11: return 11;
105 case R12: case D12: return 12;
106 case SP: case D13: return 13;
107 case LR: case D14: return 14;
108 case PC: case D15: return 15;
110 case S0: case S1: case S2: case S3:
111 case S4: case S5: case S6: case S7:
112 case S8: case S9: case S10: case S11:
113 case S12: case S13: case S14: case S15:
114 case S16: case S17: case S18: case S19:
115 case S20: case S21: case S22: case S23:
116 case S24: case S25: case S26: case S27:
117 case S28: case S29: case S30: case S31: {
120 default: return 0; // Avoid compile time warning.
158 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
159 const ARMSubtarget &sti)
160 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
162 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
166 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
167 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
171 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
172 return MIB.addReg(0);
175 /// emitLoadConstPool - Emits a load from constpool to materialize the
176 /// specified immediate.
177 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator &MBBI,
179 unsigned DestReg, int Val,
180 unsigned Pred, unsigned PredReg,
181 const TargetInstrInfo *TII,
184 MachineFunction &MF = *MBB.getParent();
185 MachineConstantPool *ConstantPool = MF.getConstantPool();
186 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
187 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
189 BuildMI(MBB, MBBI, dl,
190 TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
192 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
193 .addConstantPoolIndex(Idx)
194 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
197 /// isLowRegister - Returns true if the register is low register r0-r7.
199 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
202 case R0: case R1: case R2: case R3:
203 case R4: case R5: case R6: case R7:
210 const TargetRegisterClass*
211 ARMRegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
213 if (isLowRegister(Reg))
214 return ARM::tGPRRegisterClass;
218 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
219 case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
220 return ARM::GPRRegisterClass;
223 return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
227 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
228 static const unsigned CalleeSavedRegs[] = {
229 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
230 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
232 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
233 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
237 static const unsigned DarwinCalleeSavedRegs[] = {
238 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
239 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
241 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
242 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
245 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
248 const TargetRegisterClass* const *
249 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
250 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
251 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
252 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
253 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
255 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
256 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
259 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
260 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
261 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
262 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
264 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
265 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
268 return STI.isThumb() ? ThumbCalleeSavedRegClasses : CalleeSavedRegClasses;
271 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272 // FIXME: avoid re-calculating this everytime.
273 BitVector Reserved(getNumRegs());
274 Reserved.set(ARM::SP);
275 Reserved.set(ARM::PC);
276 if (STI.isTargetDarwin() || hasFP(MF))
277 Reserved.set(FramePtr);
278 // Some targets reserve R9.
279 if (STI.isR9Reserved())
280 Reserved.set(ARM::R9);
285 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
293 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
297 return STI.isR9Reserved();
303 const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
304 return &ARM::GPRRegClass;
307 /// getAllocationOrder - Returns the register allocation order for a specified
308 /// register class in the form of a pair of TargetRegisterClass iterators.
309 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
310 ARMRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
311 unsigned HintType, unsigned HintReg,
312 const MachineFunction &MF) const {
313 // Alternative register allocation orders when favoring even / odd registers
314 // of register pairs.
316 // No FP, R9 is available.
317 static const unsigned GPREven1[] = {
318 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
322 static const unsigned GPROdd1[] = {
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
328 // FP is R7, R9 is available.
329 static const unsigned GPREven2[] = {
330 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
334 static const unsigned GPROdd2[] = {
335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
340 // FP is R11, R9 is available.
341 static const unsigned GPREven3[] = {
342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
346 static const unsigned GPROdd3[] = {
347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
352 // No FP, R9 is not available.
353 static const unsigned GPREven4[] = {
354 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
358 static const unsigned GPROdd4[] = {
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
364 // FP is R7, R9 is not available.
365 static const unsigned GPREven5[] = {
366 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
370 static const unsigned GPROdd5[] = {
371 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
372 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
376 // FP is R11, R9 is not available.
377 static const unsigned GPREven6[] = {
378 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
379 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
381 static const unsigned GPROdd6[] = {
382 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
383 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
387 if (HintType == ARMRI::RegPairEven) {
388 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
389 // It's no longer possible to fulfill this hint. Return the default
391 return std::make_pair(RC->allocation_order_begin(MF),
392 RC->allocation_order_end(MF));
394 if (!STI.isTargetDarwin() && !hasFP(MF)) {
395 if (!STI.isR9Reserved())
396 return std::make_pair(GPREven1,
397 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
399 return std::make_pair(GPREven4,
400 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
401 } else if (FramePtr == ARM::R7) {
402 if (!STI.isR9Reserved())
403 return std::make_pair(GPREven2,
404 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
406 return std::make_pair(GPREven5,
407 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
408 } else { // FramePtr == ARM::R11
409 if (!STI.isR9Reserved())
410 return std::make_pair(GPREven3,
411 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
413 return std::make_pair(GPREven6,
414 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
416 } else if (HintType == ARMRI::RegPairOdd) {
417 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
418 // It's no longer possible to fulfill this hint. Return the default
420 return std::make_pair(RC->allocation_order_begin(MF),
421 RC->allocation_order_end(MF));
423 if (!STI.isTargetDarwin() && !hasFP(MF)) {
424 if (!STI.isR9Reserved())
425 return std::make_pair(GPROdd1,
426 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
428 return std::make_pair(GPROdd4,
429 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
430 } else if (FramePtr == ARM::R7) {
431 if (!STI.isR9Reserved())
432 return std::make_pair(GPROdd2,
433 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
435 return std::make_pair(GPROdd5,
436 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
437 } else { // FramePtr == ARM::R11
438 if (!STI.isR9Reserved())
439 return std::make_pair(GPROdd3,
440 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
442 return std::make_pair(GPROdd6,
443 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
446 return std::make_pair(RC->allocation_order_begin(MF),
447 RC->allocation_order_end(MF));
450 /// ResolveRegAllocHint - Resolves the specified register allocation hint
451 /// to a physical register. Returns the physical register if it is successful.
453 ARMRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
454 const MachineFunction &MF) const {
455 if (Reg == 0 || !isPhysicalRegister(Reg))
459 else if (Type == (unsigned)ARMRI::RegPairOdd)
461 return getRegisterPairOdd(Reg, MF);
462 else if (Type == (unsigned)ARMRI::RegPairEven)
464 return getRegisterPairEven(Reg, MF);
469 ARMRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
470 MachineFunction &MF) const {
471 MachineRegisterInfo *MRI = &MF.getRegInfo();
472 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
473 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
474 Hint.first == (unsigned)ARMRI::RegPairEven) &&
475 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
476 // If 'Reg' is one of the even / odd register pair and it's now changed
477 // (e.g. coalesced) into a different register. The other register of the
478 // pair allocation hint must be updated to reflect the relationship
480 unsigned OtherReg = Hint.second;
481 Hint = MRI->getRegAllocationHint(OtherReg);
482 if (Hint.second == Reg)
483 // Make sure the pair has not already divorced.
484 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
489 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
490 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
491 return ThumbRegScavenging || !AFI->isThumbFunction();
494 /// hasFP - Return true if the specified function should have a dedicated frame
495 /// pointer register. This is true if the function has variable sized allocas
496 /// or if frame pointer elimination is disabled.
498 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
499 const MachineFrameInfo *MFI = MF.getFrameInfo();
500 return NoFramePointerElim || MFI->hasVarSizedObjects();
503 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
504 // not required, we reserve argument space for call sites in the function
505 // immediately on entry to the current function. This eliminates the need for
506 // add/sub sp brackets around call sites. Returns true if the call frame is
507 // included as part of the stack frame.
508 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
509 const MachineFrameInfo *FFI = MF.getFrameInfo();
510 unsigned CFSize = FFI->getMaxCallFrameSize();
511 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
512 // It's not always a good idea to include the call frame as part of the
513 // stack frame. ARM (especially Thumb) has small immediate offset to
514 // address the stack frame. So a large call frame can cause poor codegen
515 // and may even makes it impossible to scavenge a register.
516 if (AFI->isThumbFunction()) {
517 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
520 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
523 return !MF.getFrameInfo()->hasVarSizedObjects();
526 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
527 /// a destreg = basereg + immediate in ARM code.
529 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
530 MachineBasicBlock::iterator &MBBI,
531 unsigned DestReg, unsigned BaseReg, int NumBytes,
532 ARMCC::CondCodes Pred, unsigned PredReg,
533 const TargetInstrInfo &TII,
535 bool isSub = NumBytes < 0;
536 if (isSub) NumBytes = -NumBytes;
539 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
540 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
541 assert(ThisVal && "Didn't extract field correctly");
543 // We will handle these bits from offset, clear them.
544 NumBytes &= ~ThisVal;
546 // Get the properly encoded SOImmVal field.
547 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
548 assert(SOImmVal != -1 && "Bit extraction didn't work?");
550 // Build the new ADD / SUB.
551 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
552 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
553 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
558 /// calcNumMI - Returns the number of instructions required to materialize
559 /// the specific add / sub r, c instruction.
560 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
561 unsigned NumBits, unsigned Scale) {
563 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
565 if (Opc == ARM::tADDrSPi) {
566 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
570 Scale = 1; // Followed by a number of tADDi8.
571 Chunk = ((1 << NumBits) - 1) * Scale;
574 NumMIs += Bytes / Chunk;
575 if ((Bytes % Chunk) != 0)
582 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
583 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
584 /// in a register using mov / mvn sequences or load the immediate from a
587 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
588 MachineBasicBlock::iterator &MBBI,
589 unsigned DestReg, unsigned BaseReg,
590 int NumBytes, bool CanChangeCC,
591 const TargetInstrInfo &TII,
592 const ARMRegisterInfo& MRI,
594 bool isHigh = !MRI.isLowRegister(DestReg) ||
595 (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
597 // Subtract doesn't have high register version. Load the negative value
598 // if either base or dest register is a high register. Also, if do not
599 // issue sub as part of the sequence if condition register is to be
601 if (NumBytes < 0 && !isHigh && CanChangeCC) {
603 NumBytes = -NumBytes;
605 unsigned LdReg = DestReg;
606 if (DestReg == ARM::SP) {
607 assert(BaseReg == ARM::SP && "Unexpected!");
609 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
610 .addReg(ARM::R3, RegState::Kill);
613 if (NumBytes <= 255 && NumBytes >= 0)
614 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
615 else if (NumBytes < 0 && NumBytes >= -255) {
616 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
617 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
618 .addReg(LdReg, RegState::Kill);
620 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
624 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
625 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
626 TII.get(Opc), DestReg);
627 if (DestReg == ARM::SP || isSub)
628 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
630 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
631 if (DestReg == ARM::SP)
632 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
633 .addReg(ARM::R12, RegState::Kill);
636 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
637 /// a destreg = basereg + immediate in Thumb code.
639 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
640 MachineBasicBlock::iterator &MBBI,
641 unsigned DestReg, unsigned BaseReg,
642 int NumBytes, const TargetInstrInfo &TII,
643 const ARMRegisterInfo& MRI,
645 bool isSub = NumBytes < 0;
646 unsigned Bytes = (unsigned)NumBytes;
647 if (isSub) Bytes = -NumBytes;
648 bool isMul4 = (Bytes & 3) == 0;
649 bool isTwoAddr = false;
650 bool DstNotEqBase = false;
651 unsigned NumBits = 1;
656 if (DestReg == BaseReg && BaseReg == ARM::SP) {
657 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
660 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
662 } else if (!isSub && BaseReg == ARM::SP) {
665 // r1 = add sp, 100 * 4
669 ExtraOpc = ARM::tADDi3;
678 if (DestReg != BaseReg)
681 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
685 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
686 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
687 if (NumMIs > Threshold) {
688 // This will expand into too many instructions. Load the immediate from a
690 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
696 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
697 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
698 unsigned Chunk = (1 << 3) - 1;
699 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
701 BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
702 .addReg(BaseReg, RegState::Kill).addImm(ThisVal);
704 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
705 .addReg(BaseReg, RegState::Kill);
710 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
712 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
715 // Build the new tADD / tSUB.
717 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
718 .addReg(DestReg).addImm(ThisVal);
720 bool isKill = BaseReg != ARM::SP;
721 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
722 .addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
725 if (Opc == ARM::tADDrSPi) {
731 Chunk = ((1 << NumBits) - 1) * Scale;
732 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
739 BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
740 .addReg(DestReg, RegState::Kill)
741 .addImm(((unsigned)NumBytes) & 3);
745 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
746 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
747 bool isThumb, const TargetInstrInfo &TII,
748 const ARMRegisterInfo& MRI,
751 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
754 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
755 Pred, PredReg, TII, dl);
758 void ARMRegisterInfo::
759 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
760 MachineBasicBlock::iterator I) const {
761 if (!hasReservedCallFrame(MF)) {
762 // If we have alloca, convert as follows:
763 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
764 // ADJCALLSTACKUP -> add, sp, sp, amount
765 MachineInstr *Old = I;
766 DebugLoc dl = Old->getDebugLoc();
767 unsigned Amount = Old->getOperand(0).getImm();
769 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
770 // We need to keep the stack aligned properly. To do this, we round the
771 // amount of space needed for the outgoing arguments up to the next
772 // alignment boundary.
773 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
774 Amount = (Amount+Align-1)/Align*Align;
776 // Replace the pseudo instruction with a new instruction...
777 unsigned Opc = Old->getOpcode();
778 bool isThumb = AFI->isThumbFunction();
779 ARMCC::CondCodes Pred = isThumb
780 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
781 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
782 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
783 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
784 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl);
786 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
787 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
788 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
789 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl);
796 /// emitThumbConstant - Emit a series of instructions to materialize a
798 static void emitThumbConstant(MachineBasicBlock &MBB,
799 MachineBasicBlock::iterator &MBBI,
800 unsigned DestReg, int Imm,
801 const TargetInstrInfo &TII,
802 const ARMRegisterInfo& MRI,
804 bool isSub = Imm < 0;
805 if (isSub) Imm = -Imm;
807 int Chunk = (1 << 8) - 1;
808 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
810 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
812 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
814 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
815 .addReg(DestReg, RegState::Kill);
818 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
819 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
820 /// register first and then a spilled callee-saved register if that fails.
822 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
823 ARMFunctionInfo *AFI) {
824 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
825 assert (!AFI->isThumbFunction());
827 // Try a already spilled CS register.
828 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
833 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
834 int SPAdj, RegScavenger *RS) const{
836 MachineInstr &MI = *II;
837 MachineBasicBlock &MBB = *MI.getParent();
838 MachineFunction &MF = *MBB.getParent();
839 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
840 bool isThumb = AFI->isThumbFunction();
841 DebugLoc dl = MI.getDebugLoc();
843 while (!MI.getOperand(i).isFI()) {
845 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
848 unsigned FrameReg = ARM::SP;
849 int FrameIndex = MI.getOperand(i).getIndex();
850 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
851 MF.getFrameInfo()->getStackSize() + SPAdj;
853 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
854 Offset -= AFI->getGPRCalleeSavedArea1Offset();
855 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
856 Offset -= AFI->getGPRCalleeSavedArea2Offset();
857 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
858 Offset -= AFI->getDPRCalleeSavedAreaOffset();
859 else if (hasFP(MF)) {
860 assert(SPAdj == 0 && "Unexpected");
861 // There is alloca()'s in this function, must reference off the frame
863 FrameReg = getFrameRegister(MF);
864 Offset -= AFI->getFramePtrSpillOffset();
867 unsigned Opcode = MI.getOpcode();
868 const TargetInstrDesc &Desc = MI.getDesc();
869 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
872 // Memory operands in inline assembly always use AddrMode2.
873 if (Opcode == ARM::INLINEASM)
874 AddrMode = ARMII::AddrMode2;
876 if (Opcode == ARM::ADDri) {
877 Offset += MI.getOperand(i+1).getImm();
879 // Turn it into a move.
880 MI.setDesc(TII.get(ARM::MOVr));
881 MI.getOperand(i).ChangeToRegister(FrameReg, false);
882 MI.RemoveOperand(i+1);
884 } else if (Offset < 0) {
887 MI.setDesc(TII.get(ARM::SUBri));
890 // Common case: small offset, fits into instruction.
891 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
892 if (ImmedOffset != -1) {
893 // Replace the FrameIndex with sp / fp
894 MI.getOperand(i).ChangeToRegister(FrameReg, false);
895 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
899 // Otherwise, we fallback to common code below to form the imm offset with
900 // a sequence of ADDri instructions. First though, pull as much of the imm
901 // into this ADDri as possible.
902 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
903 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
905 // We will handle these bits from offset, clear them.
906 Offset &= ~ThisImmVal;
908 // Get the properly encoded SOImmVal field.
909 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
910 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
911 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
912 } else if (Opcode == ARM::tADDrSPi) {
913 Offset += MI.getOperand(i+1).getImm();
915 // Can't use tADDrSPi if it's based off the frame pointer.
916 unsigned NumBits = 0;
918 if (FrameReg != ARM::SP) {
919 Opcode = ARM::tADDi3;
920 MI.setDesc(TII.get(ARM::tADDi3));
925 assert((Offset & 3) == 0 &&
926 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
930 // Turn it into a move.
931 MI.setDesc(TII.get(ARM::tMOVhir2lor));
932 MI.getOperand(i).ChangeToRegister(FrameReg, false);
933 MI.RemoveOperand(i+1);
937 // Common case: small offset, fits into instruction.
938 unsigned Mask = (1 << NumBits) - 1;
939 if (((Offset / Scale) & ~Mask) == 0) {
940 // Replace the FrameIndex with sp / fp
941 MI.getOperand(i).ChangeToRegister(FrameReg, false);
942 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
946 unsigned DestReg = MI.getOperand(0).getReg();
947 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
948 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
949 // MI would expand into a large number of instructions. Don't try to
950 // simplify the immediate.
952 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
959 // Translate r0 = add sp, imm to
960 // r0 = add sp, 255*4
961 // r0 = add r0, (imm - 255*4)
962 MI.getOperand(i).ChangeToRegister(FrameReg, false);
963 MI.getOperand(i+1).ChangeToImmediate(Mask);
964 Offset = (Offset - Mask * Scale);
965 MachineBasicBlock::iterator NII = next(II);
966 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
969 // Translate r0 = add sp, -imm to
970 // r0 = -imm (this is then translated into a series of instructons)
972 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
973 MI.setDesc(TII.get(ARM::tADDhirr));
974 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
975 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
981 unsigned NumBits = 0;
984 case ARMII::AddrMode2: {
986 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
987 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
992 case ARMII::AddrMode3: {
994 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
995 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1000 case ARMII::AddrMode5: {
1002 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1003 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1009 case ARMII::AddrModeTs: {
1011 InstrOffs = MI.getOperand(ImmIdx).getImm();
1012 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
1017 assert(0 && "Unsupported addressing mode!");
1022 Offset += InstrOffs * Scale;
1023 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1024 if (Offset < 0 && !isThumb) {
1029 // Common case: small offset, fits into instruction.
1030 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1031 int ImmedOffset = Offset / Scale;
1032 unsigned Mask = (1 << NumBits) - 1;
1033 if ((unsigned)Offset <= Mask * Scale) {
1034 // Replace the FrameIndex with sp
1035 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1037 ImmedOffset |= 1 << NumBits;
1038 ImmOp.ChangeToImmediate(ImmedOffset);
1042 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
1043 if (AddrMode == ARMII::AddrModeTs) {
1044 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
1045 // a different base register.
1047 Mask = (1 << NumBits) - 1;
1049 // If this is a thumb spill / restore, we will be using a constpool load to
1050 // materialize the offset.
1051 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
1052 ImmOp.ChangeToImmediate(0);
1054 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1055 ImmedOffset = ImmedOffset & Mask;
1057 ImmedOffset |= 1 << NumBits;
1058 ImmOp.ChangeToImmediate(ImmedOffset);
1059 Offset &= ~(Mask*Scale);
1063 // If we get here, the immediate doesn't fit into the instruction. We folded
1064 // as much as possible above, handle the rest, providing a register that is
1066 assert(Offset && "This code isn't needed if offset already handled!");
1069 if (Desc.mayLoad()) {
1070 // Use the destination register to materialize sp + offset.
1071 unsigned TmpReg = MI.getOperand(0).getReg();
1073 if (Opcode == ARM::tRestore) {
1074 if (FrameReg == ARM::SP)
1075 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
1076 Offset, false, TII, *this, dl);
1078 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
1083 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
1085 MI.setDesc(TII.get(ARM::tLDR));
1086 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1088 // Use [reg, reg] addrmode.
1089 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
1090 else // tLDR has an extra register operand.
1091 MI.addOperand(MachineOperand::CreateReg(0, false));
1092 } else if (Desc.mayStore()) {
1093 // FIXME! This is horrific!!! We need register scavenging.
1094 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
1095 // also a ABI register so it's possible that is is the register that is
1096 // being storing here. If that's the case, we do the following:
1098 // Use r2 to materialize sp + offset
1101 unsigned ValReg = MI.getOperand(0).getReg();
1102 unsigned TmpReg = ARM::R3;
1104 if (ValReg == ARM::R3) {
1105 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
1106 .addReg(ARM::R2, RegState::Kill);
1109 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1110 BuildMI(MBB, II, dl, TII.get(ARM::tMOVlor2hir), ARM::R12)
1111 .addReg(ARM::R3, RegState::Kill);
1112 if (Opcode == ARM::tSpill) {
1113 if (FrameReg == ARM::SP)
1114 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
1115 Offset, false, TII, *this, dl);
1117 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
1122 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
1124 MI.setDesc(TII.get(ARM::tSTR));
1125 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1126 if (UseRR) // Use [reg, reg] addrmode.
1127 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
1128 else // tSTR has an extra register operand.
1129 MI.addOperand(MachineOperand::CreateReg(0, false));
1131 MachineBasicBlock::iterator NII = next(II);
1132 if (ValReg == ARM::R3)
1133 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R2)
1134 .addReg(ARM::R12, RegState::Kill);
1135 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1136 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVhir2lor), ARM::R3)
1137 .addReg(ARM::R12, RegState::Kill);
1139 assert(false && "Unexpected opcode!");
1141 // Insert a set of r12 with the full address: r12 = sp + offset
1142 // If the offset we have is too large to fit into the instruction, we need
1143 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1145 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1146 if (ScratchReg == 0)
1147 // No register is "free". Scavenge a register.
1148 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1149 int PIdx = MI.findFirstPredOperandIdx();
1150 ARMCC::CondCodes Pred = (PIdx == -1)
1151 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1152 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1153 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1154 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
1155 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1159 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1160 const MachineFrameInfo *FFI = MF.getFrameInfo();
1162 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1163 int FixedOff = -FFI->getObjectOffset(i);
1164 if (FixedOff > Offset) Offset = FixedOff;
1166 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1167 if (FFI->isDeadObjectIndex(i))
1169 Offset += FFI->getObjectSize(i);
1170 unsigned Align = FFI->getObjectAlignment(i);
1171 // Adjust to alignment boundary
1172 Offset = (Offset+Align-1)/Align*Align;
1174 return (unsigned)Offset;
1178 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1179 RegScavenger *RS) const {
1180 // This tells PEI to spill the FP as if it is any other callee-save register
1181 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1182 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1183 // to combine multiple loads / stores.
1184 bool CanEliminateFrame = true;
1185 bool CS1Spilled = false;
1186 bool LRSpilled = false;
1187 unsigned NumGPRSpills = 0;
1188 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1189 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1190 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1192 // Don't spill FP if the frame can be eliminated. This is determined
1193 // by scanning the callee-save registers to see if any is used.
1194 const unsigned *CSRegs = getCalleeSavedRegs();
1195 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1196 for (unsigned i = 0; CSRegs[i]; ++i) {
1197 unsigned Reg = CSRegs[i];
1198 bool Spilled = false;
1199 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
1200 AFI->setCSRegisterIsSpilled(Reg);
1202 CanEliminateFrame = false;
1204 // Check alias registers too.
1205 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1206 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
1208 CanEliminateFrame = false;
1213 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1217 if (!STI.isTargetDarwin()) {
1224 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1239 if (!STI.isTargetDarwin()) {
1240 UnspilledCS1GPRs.push_back(Reg);
1250 UnspilledCS1GPRs.push_back(Reg);
1253 UnspilledCS2GPRs.push_back(Reg);
1260 bool ForceLRSpill = false;
1261 if (!LRSpilled && AFI->isThumbFunction()) {
1262 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
1263 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1264 // use of BL to implement far jump. If it turns out that it's not needed
1265 // then the branch fix up path will undo it.
1266 if (FnSize >= (1 << 11)) {
1267 CanEliminateFrame = false;
1268 ForceLRSpill = true;
1272 bool ExtraCSSpill = false;
1273 if (!CanEliminateFrame || hasFP(MF)) {
1274 AFI->setHasStackFrame(true);
1276 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1277 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1278 if (!LRSpilled && CS1Spilled) {
1279 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1280 AFI->setCSRegisterIsSpilled(ARM::LR);
1282 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1283 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1284 ForceLRSpill = false;
1285 ExtraCSSpill = true;
1288 // Darwin ABI requires FP to point to the stack slot that contains the
1290 if (STI.isTargetDarwin() || hasFP(MF)) {
1291 MF.getRegInfo().setPhysRegUsed(FramePtr);
1295 // If stack and double are 8-byte aligned and we are spilling an odd number
1296 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1297 // the integer and double callee save areas.
1298 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1299 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1300 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1301 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1302 unsigned Reg = UnspilledCS1GPRs[i];
1303 // Don't spiil high register if the function is thumb
1304 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1305 MF.getRegInfo().setPhysRegUsed(Reg);
1306 AFI->setCSRegisterIsSpilled(Reg);
1307 if (!isReservedReg(MF, Reg))
1308 ExtraCSSpill = true;
1312 } else if (!UnspilledCS2GPRs.empty() &&
1313 !AFI->isThumbFunction()) {
1314 unsigned Reg = UnspilledCS2GPRs.front();
1315 MF.getRegInfo().setPhysRegUsed(Reg);
1316 AFI->setCSRegisterIsSpilled(Reg);
1317 if (!isReservedReg(MF, Reg))
1318 ExtraCSSpill = true;
1322 // Estimate if we might need to scavenge a register at some point in order
1323 // to materialize a stack offset. If so, either spill one additiona
1324 // callee-saved register or reserve a special spill slot to facilitate
1325 // register scavenging.
1326 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1327 MachineFrameInfo *MFI = MF.getFrameInfo();
1328 unsigned Size = estimateStackSize(MF, MFI);
1329 unsigned Limit = (1 << 12) - 1;
1330 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1331 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1332 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1333 if (I->getOperand(i).isFI()) {
1334 unsigned Opcode = I->getOpcode();
1335 const TargetInstrDesc &Desc = TII.get(Opcode);
1336 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1337 if (AddrMode == ARMII::AddrMode3) {
1338 Limit = (1 << 8) - 1;
1339 goto DoneEstimating;
1340 } else if (AddrMode == ARMII::AddrMode5) {
1341 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1342 if (ThisLimit < Limit)
1348 if (Size >= Limit) {
1349 // If any non-reserved CS register isn't spilled, just spill one or two
1350 // extra. That should take care of it!
1351 unsigned NumExtras = TargetAlign / 4;
1352 SmallVector<unsigned, 2> Extras;
1353 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1354 unsigned Reg = UnspilledCS1GPRs.back();
1355 UnspilledCS1GPRs.pop_back();
1356 if (!isReservedReg(MF, Reg)) {
1357 Extras.push_back(Reg);
1361 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1362 unsigned Reg = UnspilledCS2GPRs.back();
1363 UnspilledCS2GPRs.pop_back();
1364 if (!isReservedReg(MF, Reg)) {
1365 Extras.push_back(Reg);
1369 if (Extras.size() && NumExtras == 0) {
1370 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1371 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1372 AFI->setCSRegisterIsSpilled(Extras[i]);
1375 // Reserve a slot closest to SP or frame pointer.
1376 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1377 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1378 RC->getAlignment()));
1385 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1386 AFI->setCSRegisterIsSpilled(ARM::LR);
1387 AFI->setLRIsSpilledForFarJump(true);
1391 /// Move iterator pass the next bunch of callee save load / store ops for
1392 /// the particular spill area (1: integer area 1, 2: integer area 2,
1393 /// 3: fp area, 0: don't care).
1394 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1395 MachineBasicBlock::iterator &MBBI,
1396 int Opc, unsigned Area,
1397 const ARMSubtarget &STI) {
1398 while (MBBI != MBB.end() &&
1399 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1402 unsigned Category = 0;
1403 switch (MBBI->getOperand(0).getReg()) {
1404 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1408 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1409 Category = STI.isTargetDarwin() ? 2 : 1;
1411 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1412 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1419 if (Done || Category != Area)
1427 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1428 MachineBasicBlock &MBB = MF.front();
1429 MachineBasicBlock::iterator MBBI = MBB.begin();
1430 MachineFrameInfo *MFI = MF.getFrameInfo();
1431 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1432 bool isThumb = AFI->isThumbFunction();
1433 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1434 unsigned NumBytes = MFI->getStackSize();
1435 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1436 DebugLoc dl = (MBBI != MBB.end() ?
1437 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1440 // Check if R3 is live in. It might have to be used as a scratch register.
1441 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1442 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1443 if (I->first == ARM::R3) {
1444 AFI->setR3IsLiveIn(true);
1449 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1450 NumBytes = (NumBytes + 3) & ~3;
1451 MFI->setStackSize(NumBytes);
1454 // Determine the sizes of each callee-save spill areas and record which frame
1455 // belongs to which callee-save spill areas.
1456 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1457 int FramePtrSpillFI = 0;
1460 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1463 if (!AFI->hasStackFrame()) {
1465 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1469 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1470 unsigned Reg = CSI[i].getReg();
1471 int FI = CSI[i].getFrameIdx();
1478 if (Reg == FramePtr)
1479 FramePtrSpillFI = FI;
1480 AFI->addGPRCalleeSavedArea1Frame(FI);
1487 if (Reg == FramePtr)
1488 FramePtrSpillFI = FI;
1489 if (STI.isTargetDarwin()) {
1490 AFI->addGPRCalleeSavedArea2Frame(FI);
1493 AFI->addGPRCalleeSavedArea1Frame(FI);
1498 AFI->addDPRCalleeSavedAreaFrame(FI);
1504 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1505 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl);
1506 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1507 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
1509 if (MBBI != MBB.end())
1510 dl = MBBI->getDebugLoc();
1513 // Darwin ABI requires FP to point to the stack slot that contains the
1515 if (STI.isTargetDarwin() || hasFP(MF)) {
1516 MachineInstrBuilder MIB =
1517 BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),
1519 .addFrameIndex(FramePtrSpillFI).addImm(0);
1520 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1524 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1525 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl);
1527 // Build the new SUBri to adjust SP for FP callee-save spill area.
1528 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1529 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl);
1532 // Determine starting offsets of spill areas.
1533 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1534 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1535 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1536 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1537 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1538 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1539 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1541 NumBytes = DPRCSOffset;
1543 // Insert it after all the callee-save spills.
1545 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1546 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1549 if(STI.isTargetELF() && hasFP(MF)) {
1550 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1551 AFI->getFramePtrSpillOffset());
1554 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1555 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1556 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1559 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1560 for (unsigned i = 0; CSRegs[i]; ++i)
1561 if (Reg == CSRegs[i])
1566 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1567 return ((MI->getOpcode() == ARM::FLDD ||
1568 MI->getOpcode() == ARM::LDR ||
1569 MI->getOpcode() == ARM::tRestore) &&
1570 MI->getOperand(1).isFI() &&
1571 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1574 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1575 MachineBasicBlock &MBB) const {
1576 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1577 assert((MBBI->getOpcode() == ARM::BX_RET ||
1578 MBBI->getOpcode() == ARM::tBX_RET ||
1579 MBBI->getOpcode() == ARM::tPOP_RET) &&
1580 "Can only insert epilog into returning blocks");
1581 DebugLoc dl = MBBI->getDebugLoc();
1582 MachineFrameInfo *MFI = MF.getFrameInfo();
1583 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1584 bool isThumb = AFI->isThumbFunction();
1585 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1586 int NumBytes = (int)MFI->getStackSize();
1588 if (!AFI->hasStackFrame()) {
1590 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1592 // Unwind MBBI to point to first LDR / FLDD.
1593 const unsigned *CSRegs = getCalleeSavedRegs();
1594 if (MBBI != MBB.begin()) {
1597 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1598 if (!isCSRestore(MBBI, CSRegs))
1602 // Move SP to start of FP callee save spill area.
1603 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1604 AFI->getGPRCalleeSavedArea2Size() +
1605 AFI->getDPRCalleeSavedAreaSize());
1608 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1609 // Reset SP based on frame pointer only if the stack frame extends beyond
1610 // frame pointer stack slot or target is ELF and the function has FP.
1612 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1615 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVlor2hir), ARM::SP)
1618 if (MBBI->getOpcode() == ARM::tBX_RET &&
1619 &MBB.front() != MBBI &&
1620 prior(MBBI)->getOpcode() == ARM::tPOP) {
1621 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1622 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1625 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1629 // Darwin ABI requires FP to point to the stack slot that contains the
1631 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1632 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1633 // Reset SP based on frame pointer only if the stack frame extends beyond
1634 // frame pointer stack slot or target is ELF and the function has FP.
1635 if (AFI->getGPRCalleeSavedArea2Size() ||
1636 AFI->getDPRCalleeSavedAreaSize() ||
1637 AFI->getDPRCalleeSavedAreaOffset()||
1640 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1642 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1644 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1645 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1647 } else if (NumBytes) {
1648 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl);
1651 // Move SP to start of integer callee save spill area 2.
1652 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1653 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1654 false, TII, *this, dl);
1656 // Move SP to start of integer callee save spill area 1.
1657 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1658 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1659 false, TII, *this, dl);
1661 // Move SP to SP upon entry to the function.
1662 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1663 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1664 false, TII, *this, dl);
1668 if (VARegSaveSize) {
1670 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1671 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1672 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
1674 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1678 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1684 unsigned ARMRegisterInfo::getRARegister() const {
1688 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1689 if (STI.isTargetDarwin() || hasFP(MF))
1690 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1695 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1696 assert(0 && "What is the exception register");
1700 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1701 assert(0 && "What is the exception handler register");
1705 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1706 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1709 unsigned ARMRegisterInfo::getRegisterPairEven(unsigned Reg,
1710 const MachineFunction &MF) const {
1713 // Return 0 if either register of the pair is a special register.
1719 return STI.isThumb() ? 0 : ARM::R2;
1723 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
1725 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1727 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1783 unsigned ARMRegisterInfo::getRegisterPairOdd(unsigned Reg,
1784 const MachineFunction &MF) const {
1787 // Return 0 if either register of the pair is a special register.
1793 return STI.isThumb() ? 0 : ARM::R3;
1797 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1799 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1801 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1857 #include "ARMGenRegisterInfo.inc"