1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addRegOperand(Reg, true);
135 void ARMRegisterInfo::
136 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
137 unsigned SrcReg, int FI,
138 const TargetRegisterClass *RC) const {
139 if (RC == ARM::GPRRegisterClass) {
140 MachineFunction &MF = *MBB.getParent();
141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
142 if (AFI->isThumbFunction())
143 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
144 .addFrameIndex(FI).addImm(0);
146 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
147 .addFrameIndex(FI).addReg(0).addImm(0);
148 } else if (RC == ARM::DPRRegisterClass) {
149 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
150 .addFrameIndex(FI).addImm(0);
152 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
153 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
154 .addFrameIndex(FI).addImm(0);
158 void ARMRegisterInfo::
159 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
160 unsigned DestReg, int FI,
161 const TargetRegisterClass *RC) const {
162 if (RC == ARM::GPRRegisterClass) {
163 MachineFunction &MF = *MBB.getParent();
164 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
165 if (AFI->isThumbFunction())
166 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
167 .addFrameIndex(FI).addImm(0);
169 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
170 .addFrameIndex(FI).addReg(0).addImm(0);
171 } else if (RC == ARM::DPRRegisterClass) {
172 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
173 .addFrameIndex(FI).addImm(0);
175 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
176 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
177 .addFrameIndex(FI).addImm(0);
181 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator I,
183 unsigned DestReg, unsigned SrcReg,
184 const TargetRegisterClass *RC) const {
185 if (RC == ARM::GPRRegisterClass) {
186 MachineFunction &MF = *MBB.getParent();
187 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
188 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr),
189 DestReg).addReg(SrcReg);
190 } else if (RC == ARM::SPRRegisterClass)
191 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
192 else if (RC == ARM::DPRRegisterClass)
193 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
198 /// emitLoadConstPool - Emits a load from constpool to materialize the
199 /// specified immediate.
200 static void emitLoadConstPool(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator &MBBI,
202 unsigned DestReg, int Val,
203 const TargetInstrInfo &TII, bool isThumb) {
204 MachineFunction &MF = *MBB.getParent();
205 MachineConstantPool *ConstantPool = MF.getConstantPool();
206 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
207 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
209 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
211 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
212 .addReg(0).addImm(0);
215 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator I,
218 const MachineInstr *Orig) const {
219 if (Orig->getOpcode() == ARM::MOVi2pieces) {
220 emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(),
225 MachineInstr *MI = Orig->clone();
226 MI->getOperand(0).setReg(DestReg);
230 /// isLowRegister - Returns true if the register is low register r0-r7.
232 static bool isLowRegister(unsigned Reg) {
235 case R0: case R1: case R2: case R3:
236 case R4: case R5: case R6: case R7:
243 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
244 unsigned OpNum, int FI) const {
245 unsigned Opc = MI->getOpcode();
246 MachineInstr *NewMI = NULL;
250 if (OpNum == 0) { // move -> store
251 unsigned SrcReg = MI->getOperand(1).getReg();
252 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
253 .addReg(0).addImm(0);
254 } else { // move -> load
255 unsigned DstReg = MI->getOperand(0).getReg();
256 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
262 if (OpNum == 0) { // move -> store
263 unsigned SrcReg = MI->getOperand(1).getReg();
264 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
265 // tSpill cannot take a high register operand.
267 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
269 } else { // move -> load
270 unsigned DstReg = MI->getOperand(0).getReg();
271 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
272 // tRestore cannot target a high register operand.
274 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
280 if (OpNum == 0) { // move -> store
281 unsigned SrcReg = MI->getOperand(1).getReg();
282 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
284 } else { // move -> load
285 unsigned DstReg = MI->getOperand(0).getReg();
286 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
291 if (OpNum == 0) { // move -> store
292 unsigned SrcReg = MI->getOperand(1).getReg();
293 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
295 } else { // move -> load
296 unsigned DstReg = MI->getOperand(0).getReg();
297 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
304 NewMI->copyKillDeadInfo(MI);
308 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
309 static const unsigned CalleeSavedRegs[] = {
310 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
311 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
313 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
314 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
318 static const unsigned DarwinCalleeSavedRegs[] = {
319 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
320 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
322 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
323 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
326 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
329 const TargetRegisterClass* const *
330 ARMRegisterInfo::getCalleeSavedRegClasses() const {
331 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
332 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
333 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
334 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
336 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
337 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
340 return CalleeSavedRegClasses;
343 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344 // FIXME: avoid re-calculating this everytime.
345 BitVector Reserved(getNumRegs());
346 Reserved.set(ARM::SP);
347 Reserved.set(ARM::PC);
348 if (STI.isTargetDarwin() || hasFP(MF))
349 Reserved.set(FramePtr);
350 // Some targets reserve R9.
351 if (STI.isR9Reserved())
352 Reserved.set(ARM::R9);
353 // At PEI time, if LR is used, it will be spilled upon entry.
354 if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
355 Reserved.set(ARM::LR);
360 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
368 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
372 return STI.isR9Reserved();
379 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
380 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
381 return ThumbRegScavenging || !AFI->isThumbFunction();
384 /// hasFP - Return true if the specified function should have a dedicated frame
385 /// pointer register. This is true if the function has variable sized allocas
386 /// or if frame pointer elimination is disabled.
388 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
389 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
392 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
393 /// a destreg = basereg + immediate in ARM code.
395 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator &MBBI,
397 unsigned DestReg, unsigned BaseReg,
398 int NumBytes, const TargetInstrInfo &TII) {
399 bool isSub = NumBytes < 0;
400 if (isSub) NumBytes = -NumBytes;
403 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
404 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
405 assert(ThisVal && "Didn't extract field correctly");
407 // We will handle these bits from offset, clear them.
408 NumBytes &= ~ThisVal;
410 // Get the properly encoded SOImmVal field.
411 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
412 assert(SOImmVal != -1 && "Bit extraction didn't work?");
414 // Build the new ADD / SUB.
415 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
416 .addReg(BaseReg, false, false, true).addImm(SOImmVal);
421 /// calcNumMI - Returns the number of instructions required to materialize
422 /// the specific add / sub r, c instruction.
423 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
424 unsigned NumBits, unsigned Scale) {
426 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
428 if (Opc == ARM::tADDrSPi) {
429 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
433 Scale = 1; // Followed by a number of tADDi8.
434 Chunk = ((1 << NumBits) - 1) * Scale;
437 NumMIs += Bytes / Chunk;
438 if ((Bytes % Chunk) != 0)
445 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
446 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
447 /// in a register using mov / mvn sequences or load the immediate from a
450 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
451 MachineBasicBlock::iterator &MBBI,
452 unsigned DestReg, unsigned BaseReg,
453 int NumBytes, bool CanChangeCC,
454 const TargetInstrInfo &TII) {
455 bool isHigh = !isLowRegister(DestReg) ||
456 (BaseReg != 0 && !isLowRegister(BaseReg));
458 // Subtract doesn't have high register version. Load the negative value
459 // if either base or dest register is a high register. Also, if do not
460 // issue sub as part of the sequence if condition register is to be
462 if (NumBytes < 0 && !isHigh && CanChangeCC) {
464 NumBytes = -NumBytes;
466 unsigned LdReg = DestReg;
467 if (DestReg == ARM::SP) {
468 assert(BaseReg == ARM::SP && "Unexpected!");
470 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
471 .addReg(ARM::R3, false, false, true);
474 if (NumBytes <= 255 && NumBytes >= 0)
475 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
476 else if (NumBytes < 0 && NumBytes >= -255) {
477 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
478 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
479 .addReg(LdReg, false, false, true);
481 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true);
484 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
485 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
486 if (DestReg == ARM::SP || isSub)
487 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
489 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
490 if (DestReg == ARM::SP)
491 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
492 .addReg(ARM::R12, false, false, true);
495 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
496 /// a destreg = basereg + immediate in Thumb code.
498 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator &MBBI,
500 unsigned DestReg, unsigned BaseReg,
501 int NumBytes, const TargetInstrInfo &TII) {
502 bool isSub = NumBytes < 0;
503 unsigned Bytes = (unsigned)NumBytes;
504 if (isSub) Bytes = -NumBytes;
505 bool isMul4 = (Bytes & 3) == 0;
506 bool isTwoAddr = false;
507 bool DstNotEqBase = false;
508 unsigned NumBits = 1;
513 if (DestReg == BaseReg && BaseReg == ARM::SP) {
514 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
517 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
519 } else if (!isSub && BaseReg == ARM::SP) {
522 // r1 = add sp, 100 * 4
526 ExtraOpc = ARM::tADDi3;
535 if (DestReg != BaseReg)
538 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
542 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
543 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
544 if (NumMIs > Threshold) {
545 // This will expand into too many instructions. Load the immediate from a
547 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
552 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
553 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
554 unsigned Chunk = (1 << 3) - 1;
555 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
557 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
558 .addReg(BaseReg, false, false, true).addImm(ThisVal);
560 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
561 .addReg(BaseReg, false, false, true);
566 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
568 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
571 // Build the new tADD / tSUB.
573 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
575 bool isKill = BaseReg != ARM::SP;
576 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
577 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
580 if (Opc == ARM::tADDrSPi) {
586 Chunk = ((1 << NumBits) - 1) * Scale;
587 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
594 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
595 .addReg(DestReg, false, false, true)
596 .addImm(((unsigned)NumBytes) & 3);
600 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
601 int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
603 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
605 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
608 void ARMRegisterInfo::
609 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator I) const {
612 // If we have alloca, convert as follows:
613 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
614 // ADJCALLSTACKUP -> add, sp, sp, amount
615 MachineInstr *Old = I;
616 unsigned Amount = Old->getOperand(0).getImmedValue();
618 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619 // We need to keep the stack aligned properly. To do this, we round the
620 // amount of space needed for the outgoing arguments up to the next
621 // alignment boundary.
622 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
623 Amount = (Amount+Align-1)/Align*Align;
625 // Replace the pseudo instruction with a new instruction...
626 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
627 emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
629 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
630 emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
637 /// emitThumbConstant - Emit a series of instructions to materialize a
639 static void emitThumbConstant(MachineBasicBlock &MBB,
640 MachineBasicBlock::iterator &MBBI,
641 unsigned DestReg, int Imm,
642 const TargetInstrInfo &TII) {
643 bool isSub = Imm < 0;
644 if (isSub) Imm = -Imm;
646 int Chunk = (1 << 8) - 1;
647 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
649 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
651 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
653 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
654 .addReg(DestReg, false, false, true);
657 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
658 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
659 /// register first and then a spilled callee-saved register if that fails.
661 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
662 ARMFunctionInfo *AFI) {
663 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
665 // Try a already spilled CS register.
666 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
671 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
672 RegScavenger *RS) const{
674 MachineInstr &MI = *II;
675 MachineBasicBlock &MBB = *MI.getParent();
676 MachineFunction &MF = *MBB.getParent();
677 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
678 bool isThumb = AFI->isThumbFunction();
680 while (!MI.getOperand(i).isFrameIndex()) {
682 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
685 unsigned FrameReg = ARM::SP;
686 int FrameIndex = MI.getOperand(i).getFrameIndex();
687 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
688 MF.getFrameInfo()->getStackSize();
690 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
691 Offset -= AFI->getGPRCalleeSavedArea1Offset();
692 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
693 Offset -= AFI->getGPRCalleeSavedArea2Offset();
694 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
695 Offset -= AFI->getDPRCalleeSavedAreaOffset();
696 else if (hasFP(MF)) {
697 // There is alloca()'s in this function, must reference off the frame
699 FrameReg = getFrameRegister(MF);
700 Offset -= AFI->getFramePtrSpillOffset();
703 unsigned Opcode = MI.getOpcode();
704 const TargetInstrDescriptor &Desc = TII.get(Opcode);
705 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
708 if (Opcode == ARM::ADDri) {
709 Offset += MI.getOperand(i+1).getImm();
711 // Turn it into a move.
712 MI.setInstrDescriptor(TII.get(ARM::MOVr));
713 MI.getOperand(i).ChangeToRegister(FrameReg, false);
714 MI.RemoveOperand(i+1);
716 } else if (Offset < 0) {
719 MI.setInstrDescriptor(TII.get(ARM::SUBri));
722 // Common case: small offset, fits into instruction.
723 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
724 if (ImmedOffset != -1) {
725 // Replace the FrameIndex with sp / fp
726 MI.getOperand(i).ChangeToRegister(FrameReg, false);
727 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
731 // Otherwise, we fallback to common code below to form the imm offset with
732 // a sequence of ADDri instructions. First though, pull as much of the imm
733 // into this ADDri as possible.
734 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
735 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
737 // We will handle these bits from offset, clear them.
738 Offset &= ~ThisImmVal;
740 // Get the properly encoded SOImmVal field.
741 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
742 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
743 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
744 } else if (Opcode == ARM::tADDrSPi) {
745 Offset += MI.getOperand(i+1).getImm();
747 // Can't use tADDrSPi if it's based off the frame pointer.
748 unsigned NumBits = 0;
750 if (FrameReg != ARM::SP) {
751 Opcode = ARM::tADDi3;
752 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
757 assert((Offset & 3) == 0 &&
758 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
762 // Turn it into a move.
763 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
764 MI.getOperand(i).ChangeToRegister(FrameReg, false);
765 MI.RemoveOperand(i+1);
769 // Common case: small offset, fits into instruction.
770 unsigned Mask = (1 << NumBits) - 1;
771 if (((Offset / Scale) & ~Mask) == 0) {
772 // Replace the FrameIndex with sp / fp
773 MI.getOperand(i).ChangeToRegister(FrameReg, false);
774 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
778 unsigned DestReg = MI.getOperand(0).getReg();
779 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
780 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
781 // MI would expand into a large number of instructions. Don't try to
782 // simplify the immediate.
784 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
790 // Translate r0 = add sp, imm to
791 // r0 = add sp, 255*4
792 // r0 = add r0, (imm - 255*4)
793 MI.getOperand(i).ChangeToRegister(FrameReg, false);
794 MI.getOperand(i+1).ChangeToImmediate(Mask);
795 Offset = (Offset - Mask * Scale);
796 MachineBasicBlock::iterator NII = next(II);
797 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
799 // Translate r0 = add sp, -imm to
800 // r0 = -imm (this is then translated into a series of instructons)
802 emitThumbConstant(MBB, II, DestReg, Offset, TII);
803 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
804 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
805 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
811 unsigned NumBits = 0;
814 case ARMII::AddrMode2: {
816 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
817 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
822 case ARMII::AddrMode3: {
824 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
825 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
830 case ARMII::AddrMode5: {
832 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
833 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
839 case ARMII::AddrModeTs: {
841 InstrOffs = MI.getOperand(ImmIdx).getImm();
842 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
847 assert(0 && "Unsupported addressing mode!");
852 Offset += InstrOffs * Scale;
853 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
854 if (Offset < 0 && !isThumb) {
859 // Common case: small offset, fits into instruction.
860 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
861 int ImmedOffset = Offset / Scale;
862 unsigned Mask = (1 << NumBits) - 1;
863 if ((unsigned)Offset <= Mask * Scale) {
864 // Replace the FrameIndex with sp
865 MI.getOperand(i).ChangeToRegister(FrameReg, false);
867 ImmedOffset |= 1 << NumBits;
868 ImmOp.ChangeToImmediate(ImmedOffset);
872 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
873 if (AddrMode == ARMII::AddrModeTs) {
874 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
875 // a different base register.
877 Mask = (1 << NumBits) - 1;
879 // If this is a thumb spill / restore, we will be using a constpool load to
880 // materialize the offset.
881 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
882 ImmOp.ChangeToImmediate(0);
884 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
885 ImmedOffset = ImmedOffset & Mask;
887 ImmedOffset |= 1 << NumBits;
888 ImmOp.ChangeToImmediate(ImmedOffset);
889 Offset &= ~(Mask*Scale);
893 // If we get here, the immediate doesn't fit into the instruction. We folded
894 // as much as possible above, handle the rest, providing a register that is
896 assert(Offset && "This code isn't needed if offset already handled!");
899 if (TII.isLoad(Opcode)) {
900 // Use the destination register to materialize sp + offset.
901 unsigned TmpReg = MI.getOperand(0).getReg();
903 if (Opcode == ARM::tRestore) {
904 if (FrameReg == ARM::SP)
905 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
907 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
911 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
912 MI.setInstrDescriptor(TII.get(ARM::tLDR));
913 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
915 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
917 MI.addRegOperand(0, false); // tLDR has an extra register operand.
918 } else if (TII.isStore(Opcode)) {
919 // FIXME! This is horrific!!! We need register scavenging.
920 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
921 // also a ABI register so it's possible that is is the register that is
922 // being storing here. If that's the case, we do the following:
924 // Use r2 to materialize sp + offset
927 unsigned ValReg = MI.getOperand(0).getReg();
928 unsigned TmpReg = ARM::R3;
930 if (ValReg == ARM::R3) {
931 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
932 .addReg(ARM::R2, false, false, true);
935 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
936 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
937 .addReg(ARM::R3, false, false, true);
938 if (Opcode == ARM::tSpill) {
939 if (FrameReg == ARM::SP)
940 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
942 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
946 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
947 MI.setInstrDescriptor(TII.get(ARM::tSTR));
948 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
950 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
952 MI.addRegOperand(0, false); // tSTR has an extra register operand.
954 MachineBasicBlock::iterator NII = next(II);
955 if (ValReg == ARM::R3)
956 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
957 .addReg(ARM::R12, false, false, true);
958 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
959 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
960 .addReg(ARM::R12, false, false, true);
962 assert(false && "Unexpected opcode!");
964 // Insert a set of r12 with the full address: r12 = sp + offset
965 // If the offset we have is too large to fit into the instruction, we need
966 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
968 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
970 // No register is "free". Scavenge a register.
971 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II);
972 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
973 isSub ? -Offset : Offset, TII);
974 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
978 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
979 const MachineFrameInfo *FFI = MF.getFrameInfo();
981 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
982 int FixedOff = -FFI->getObjectOffset(i);
983 if (FixedOff > Offset) Offset = FixedOff;
985 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
986 Offset += FFI->getObjectSize(i);
987 unsigned Align = FFI->getObjectAlignment(i);
988 // Adjust to alignment boundary
989 Offset = (Offset+Align-1)/Align*Align;
991 return (unsigned)Offset;
995 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
996 RegScavenger *RS) const {
997 // This tells PEI to spill the FP as if it is any other callee-save register
998 // to take advantage the eliminateFrameIndex machinery. This also ensures it
999 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1000 // to combine multiple loads / stores.
1001 bool CanEliminateFrame = true;
1002 bool CS1Spilled = false;
1003 bool LRSpilled = false;
1004 unsigned NumGPRSpills = 0;
1005 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1006 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1009 // Don't spill FP if the frame can be eliminated. This is determined
1010 // by scanning the callee-save registers to see if any is used.
1011 const unsigned *CSRegs = getCalleeSavedRegs();
1012 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1013 for (unsigned i = 0; CSRegs[i]; ++i) {
1014 unsigned Reg = CSRegs[i];
1015 bool Spilled = false;
1016 if (MF.isPhysRegUsed(Reg)) {
1017 AFI->setCSRegisterIsSpilled(Reg);
1019 CanEliminateFrame = false;
1021 // Check alias registers too.
1022 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1023 if (MF.isPhysRegUsed(*Aliases)) {
1025 CanEliminateFrame = false;
1030 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1034 if (!STI.isTargetDarwin()) {
1042 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1057 if (!STI.isTargetDarwin()) {
1058 UnspilledCS1GPRs.push_back(Reg);
1068 UnspilledCS1GPRs.push_back(Reg);
1071 UnspilledCS2GPRs.push_back(Reg);
1078 bool ForceLRSpill = false;
1079 if (!LRSpilled && AFI->isThumbFunction()) {
1080 unsigned FnSize = ARM::GetFunctionSize(MF);
1081 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1082 // use of BL to implement far jump. If it turns out that it's not needed
1083 // then the branch fix up path will undo it.
1084 if (FnSize >= (1 << 11)) {
1085 CanEliminateFrame = false;
1086 ForceLRSpill = true;
1090 bool ExtraCSSpill = false;
1091 if (!CanEliminateFrame || hasFP(MF)) {
1092 AFI->setHasStackFrame(true);
1094 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1095 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1096 if (!LRSpilled && CS1Spilled) {
1097 MF.changePhyRegUsed(ARM::LR, true);
1098 AFI->setCSRegisterIsSpilled(ARM::LR);
1100 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1101 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1102 ForceLRSpill = false;
1103 ExtraCSSpill = true;
1106 // Darwin ABI requires FP to point to the stack slot that contains the
1108 if (STI.isTargetDarwin() || hasFP(MF)) {
1109 MF.changePhyRegUsed(FramePtr, true);
1113 // If stack and double are 8-byte aligned and we are spilling an odd number
1114 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1115 // the integer and double callee save areas.
1116 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1117 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1118 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1119 unsigned Reg = UnspilledCS1GPRs.front();
1120 MF.changePhyRegUsed(Reg, true);
1121 AFI->setCSRegisterIsSpilled(Reg);
1122 if (!isReservedReg(MF, Reg))
1123 ExtraCSSpill = true;
1124 } else if (!UnspilledCS2GPRs.empty()) {
1125 unsigned Reg = UnspilledCS2GPRs.front();
1126 MF.changePhyRegUsed(Reg, true);
1127 AFI->setCSRegisterIsSpilled(Reg);
1128 if (!isReservedReg(MF, Reg))
1129 ExtraCSSpill = true;
1133 // Estimate if we might need to scavenge a register at some point in order
1134 // to materialize a stack offset. If so, either spill one additiona
1135 // callee-saved register or reserve a special spill slot to facilitate
1136 // register scavenging.
1137 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1138 MachineFrameInfo *MFI = MF.getFrameInfo();
1139 unsigned Size = estimateStackSize(MF, MFI);
1140 unsigned Limit = (1 << 12) - 1;
1141 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1142 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1143 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1144 if (I->getOperand(i).isFrameIndex()) {
1145 unsigned Opcode = I->getOpcode();
1146 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1147 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1148 if (AddrMode == ARMII::AddrMode3) {
1149 Limit = (1 << 8) - 1;
1150 goto DoneEstimating;
1151 } else if (AddrMode == ARMII::AddrMode5) {
1152 Limit = ((1 << 8) - 1) * 4;
1153 goto DoneEstimating;
1158 if (Size >= Limit) {
1159 // If any non-reserved CS register isn't spilled, just spill one or two
1160 // extra. That should take care of it!
1161 unsigned NumExtras = TargetAlign / 4;
1162 SmallVector<unsigned, 2> Extras;
1163 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1164 unsigned Reg = UnspilledCS1GPRs.back();
1165 UnspilledCS1GPRs.pop_back();
1166 if (!isReservedReg(MF, Reg)) {
1167 Extras.push_back(Reg);
1171 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1172 unsigned Reg = UnspilledCS2GPRs.back();
1173 UnspilledCS2GPRs.pop_back();
1174 if (!isReservedReg(MF, Reg)) {
1175 Extras.push_back(Reg);
1179 if (Extras.size() && NumExtras == 0) {
1180 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1181 MF.changePhyRegUsed(Extras[i], true);
1182 AFI->setCSRegisterIsSpilled(Extras[i]);
1185 // Reserve a slot closest to SP or frame pointer.
1186 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1187 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1188 RC->getAlignment()));
1195 MF.changePhyRegUsed(ARM::LR, true);
1196 AFI->setCSRegisterIsSpilled(ARM::LR);
1197 AFI->setLRIsSpilledForFarJump(true);
1201 /// Move iterator pass the next bunch of callee save load / store ops for
1202 /// the particular spill area (1: integer area 1, 2: integer area 2,
1203 /// 3: fp area, 0: don't care).
1204 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1205 MachineBasicBlock::iterator &MBBI,
1206 int Opc, unsigned Area,
1207 const ARMSubtarget &STI) {
1208 while (MBBI != MBB.end() &&
1209 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1212 unsigned Category = 0;
1213 switch (MBBI->getOperand(0).getReg()) {
1214 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1218 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1219 Category = STI.isTargetDarwin() ? 2 : 1;
1221 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1222 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1229 if (Done || Category != Area)
1237 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1238 MachineBasicBlock &MBB = MF.front();
1239 MachineBasicBlock::iterator MBBI = MBB.begin();
1240 MachineFrameInfo *MFI = MF.getFrameInfo();
1241 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1242 bool isThumb = AFI->isThumbFunction();
1243 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1244 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1245 unsigned NumBytes = MFI->getStackSize();
1246 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1249 // Check if R3 is live in. It might have to be used as a scratch register.
1250 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1252 if ((*I).first == ARM::R3) {
1253 AFI->setR3IsLiveIn(true);
1258 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1259 NumBytes = (NumBytes + 3) & ~3;
1260 MFI->setStackSize(NumBytes);
1263 // Determine the sizes of each callee-save spill areas and record which frame
1264 // belongs to which callee-save spill areas.
1265 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1266 int FramePtrSpillFI = 0;
1269 emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
1271 if (!AFI->hasStackFrame()) {
1273 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1277 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1278 unsigned Reg = CSI[i].getReg();
1279 int FI = CSI[i].getFrameIdx();
1286 if (Reg == FramePtr)
1287 FramePtrSpillFI = FI;
1288 AFI->addGPRCalleeSavedArea1Frame(FI);
1295 if (Reg == FramePtr)
1296 FramePtrSpillFI = FI;
1297 if (STI.isTargetDarwin()) {
1298 AFI->addGPRCalleeSavedArea2Frame(FI);
1301 AFI->addGPRCalleeSavedArea1Frame(FI);
1306 AFI->addDPRCalleeSavedAreaFrame(FI);
1311 if (Align == 8 && (GPRCS1Size & 7) != 0)
1312 // Pad CS1 to ensure proper alignment.
1316 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1317 emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
1318 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1319 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1322 // Darwin ABI requires FP to point to the stack slot that contains the
1324 if (STI.isTargetDarwin() || hasFP(MF))
1325 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
1326 .addFrameIndex(FramePtrSpillFI).addImm(0);
1329 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1330 emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
1332 // Build the new SUBri to adjust SP for FP callee-save spill area.
1333 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1334 emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
1337 // Determine starting offsets of spill areas.
1338 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1339 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1340 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1341 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1342 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1343 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1344 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1346 NumBytes = DPRCSOffset;
1348 // Insert it after all the callee-save spills.
1350 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1351 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1354 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1355 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1356 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1359 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1360 for (unsigned i = 0; CSRegs[i]; ++i)
1361 if (Reg == CSRegs[i])
1366 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1367 return ((MI->getOpcode() == ARM::FLDD ||
1368 MI->getOpcode() == ARM::LDR ||
1369 MI->getOpcode() == ARM::tRestore) &&
1370 MI->getOperand(1).isFrameIndex() &&
1371 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1374 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1375 MachineBasicBlock &MBB) const {
1376 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1377 assert((MBBI->getOpcode() == ARM::BX_RET ||
1378 MBBI->getOpcode() == ARM::tBX_RET ||
1379 MBBI->getOpcode() == ARM::tPOP_RET) &&
1380 "Can only insert epilog into returning blocks");
1382 MachineFrameInfo *MFI = MF.getFrameInfo();
1383 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1384 bool isThumb = AFI->isThumbFunction();
1385 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1386 int NumBytes = (int)MFI->getStackSize();
1387 if (!AFI->hasStackFrame()) {
1389 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1391 // Unwind MBBI to point to first LDR / FLDD.
1392 const unsigned *CSRegs = getCalleeSavedRegs();
1393 if (MBBI != MBB.begin()) {
1396 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1397 if (!isCSRestore(MBBI, CSRegs))
1401 // Move SP to start of FP callee save spill area.
1402 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1403 AFI->getGPRCalleeSavedArea2Size() +
1404 AFI->getDPRCalleeSavedAreaSize());
1407 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1408 // Reset SP based on frame pointer only if the stack frame extends beyond
1409 // frame pointer stack slot or target is ELF and the function has FP.
1411 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1413 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1415 if (MBBI->getOpcode() == ARM::tBX_RET &&
1416 &MBB.front() != MBBI &&
1417 prior(MBBI)->getOpcode() == ARM::tPOP) {
1418 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1419 emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
1421 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1424 // Darwin ABI requires FP to point to the stack slot that contains the
1426 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1427 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1428 // Reset SP based on frame pointer only if the stack frame extends beyond
1429 // frame pointer stack slot or target is ELF and the function has FP.
1430 if (AFI->getGPRCalleeSavedArea2Size() ||
1431 AFI->getDPRCalleeSavedAreaSize() ||
1432 AFI->getDPRCalleeSavedAreaOffset()||
1435 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1438 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr);
1439 } else if (NumBytes) {
1440 emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
1443 // Move SP to start of integer callee save spill area 2.
1444 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1445 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
1447 // Move SP to start of integer callee save spill area 1.
1448 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1449 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
1451 // Move SP to SP upon entry to the function.
1452 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1453 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
1457 if (VARegSaveSize) {
1459 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1460 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1461 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1463 emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
1466 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1472 unsigned ARMRegisterInfo::getRARegister() const {
1476 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1477 if (STI.isTargetDarwin() || hasFP(MF))
1478 return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
1483 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1484 assert(0 && "What is the exception register");
1488 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1489 assert(0 && "What is the exception handler register");
1493 #include "ARMGenRegisterInfo.inc"