1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum,
91 assert(0 && "Unknown ARM register!");
93 case R0: case D0: return 0;
94 case R1: case D1: return 1;
95 case R2: case D2: return 2;
96 case R3: case D3: return 3;
97 case R4: case D4: return 4;
98 case R5: case D5: return 5;
99 case R6: case D6: return 6;
100 case R7: case D7: return 7;
101 case R8: case D8: return 8;
102 case R9: case D9: return 9;
103 case R10: case D10: return 10;
104 case R11: case D11: return 11;
105 case R12: case D12: return 12;
106 case SP: case D13: return 13;
107 case LR: case D14: return 14;
108 case PC: case D15: return 15;
110 case S0: case S1: case S2: case S3:
111 case S4: case S5: case S6: case S7:
112 case S8: case S9: case S10: case S11:
113 case S12: case S13: case S14: case S15:
114 case S16: case S17: case S18: case S19:
115 case S20: case S21: case S22: case S23:
116 case S24: case S25: case S26: case S27:
117 case S28: case S29: case S30: case S31: {
120 default: return 0; // Avoid compile time warning.
158 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
159 const ARMSubtarget &sti)
160 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
162 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
166 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
167 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
171 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
172 return MIB.addReg(0);
175 /// emitLoadConstPool - Emits a load from constpool to materialize the
176 /// specified immediate.
177 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator &MBBI,
179 unsigned DestReg, int Val,
180 unsigned Pred, unsigned PredReg,
181 const TargetInstrInfo *TII,
184 MachineFunction &MF = *MBB.getParent();
185 MachineConstantPool *ConstantPool = MF.getConstantPool();
186 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
187 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
189 BuildMI(MBB, MBBI, dl,
190 TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
192 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
193 .addConstantPoolIndex(Idx)
194 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
197 const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
198 return &ARM::GPRRegClass;
201 /// isLowRegister - Returns true if the register is low register r0-r7.
203 bool ARMRegisterInfo::isLowRegister(unsigned Reg) const {
206 case R0: case R1: case R2: case R3:
207 case R4: case R5: case R6: case R7:
215 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
216 static const unsigned CalleeSavedRegs[] = {
217 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
218 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
220 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
221 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
225 static const unsigned DarwinCalleeSavedRegs[] = {
226 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
227 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
229 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
230 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
233 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
236 const TargetRegisterClass* const *
237 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
238 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
239 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
240 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
241 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
243 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
244 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
247 return CalleeSavedRegClasses;
250 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
251 // FIXME: avoid re-calculating this everytime.
252 BitVector Reserved(getNumRegs());
253 Reserved.set(ARM::SP);
254 Reserved.set(ARM::PC);
255 if (STI.isTargetDarwin() || hasFP(MF))
256 Reserved.set(FramePtr);
257 // Some targets reserve R9.
258 if (STI.isR9Reserved())
259 Reserved.set(ARM::R9);
264 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
272 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
276 return STI.isR9Reserved();
283 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
284 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
285 return ThumbRegScavenging || !AFI->isThumbFunction();
288 /// hasFP - Return true if the specified function should have a dedicated frame
289 /// pointer register. This is true if the function has variable sized allocas
290 /// or if frame pointer elimination is disabled.
292 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
293 const MachineFrameInfo *MFI = MF.getFrameInfo();
294 return NoFramePointerElim || MFI->hasVarSizedObjects();
297 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
298 // not required, we reserve argument space for call sites in the function
299 // immediately on entry to the current function. This eliminates the need for
300 // add/sub sp brackets around call sites. Returns true if the call frame is
301 // included as part of the stack frame.
302 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
303 const MachineFrameInfo *FFI = MF.getFrameInfo();
304 unsigned CFSize = FFI->getMaxCallFrameSize();
305 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
306 // It's not always a good idea to include the call frame as part of the
307 // stack frame. ARM (especially Thumb) has small immediate offset to
308 // address the stack frame. So a large call frame can cause poor codegen
309 // and may even makes it impossible to scavenge a register.
310 if (AFI->isThumbFunction()) {
311 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
314 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
317 return !MF.getFrameInfo()->hasVarSizedObjects();
320 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
321 /// a destreg = basereg + immediate in ARM code.
323 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator &MBBI,
325 unsigned DestReg, unsigned BaseReg, int NumBytes,
326 ARMCC::CondCodes Pred, unsigned PredReg,
327 const TargetInstrInfo &TII,
329 bool isSub = NumBytes < 0;
330 if (isSub) NumBytes = -NumBytes;
333 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
334 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
335 assert(ThisVal && "Didn't extract field correctly");
337 // We will handle these bits from offset, clear them.
338 NumBytes &= ~ThisVal;
340 // Get the properly encoded SOImmVal field.
341 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
342 assert(SOImmVal != -1 && "Bit extraction didn't work?");
344 // Build the new ADD / SUB.
345 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
346 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
347 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
352 /// calcNumMI - Returns the number of instructions required to materialize
353 /// the specific add / sub r, c instruction.
354 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
355 unsigned NumBits, unsigned Scale) {
357 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
359 if (Opc == ARM::tADDrSPi) {
360 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
364 Scale = 1; // Followed by a number of tADDi8.
365 Chunk = ((1 << NumBits) - 1) * Scale;
368 NumMIs += Bytes / Chunk;
369 if ((Bytes % Chunk) != 0)
376 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
377 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
378 /// in a register using mov / mvn sequences or load the immediate from a
381 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
382 MachineBasicBlock::iterator &MBBI,
383 unsigned DestReg, unsigned BaseReg,
384 int NumBytes, bool CanChangeCC,
385 const TargetInstrInfo &TII,
386 const ARMRegisterInfo& MRI,
388 bool isHigh = !MRI.isLowRegister(DestReg) ||
389 (BaseReg != 0 && !MRI.isLowRegister(BaseReg));
391 // Subtract doesn't have high register version. Load the negative value
392 // if either base or dest register is a high register. Also, if do not
393 // issue sub as part of the sequence if condition register is to be
395 if (NumBytes < 0 && !isHigh && CanChangeCC) {
397 NumBytes = -NumBytes;
399 unsigned LdReg = DestReg;
400 if (DestReg == ARM::SP) {
401 assert(BaseReg == ARM::SP && "Unexpected!");
403 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R12)
404 .addReg(ARM::R3, false, false, true);
407 if (NumBytes <= 255 && NumBytes >= 0)
408 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
409 else if (NumBytes < 0 && NumBytes >= -255) {
410 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
411 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
412 .addReg(LdReg, false, false, true);
414 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
418 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
419 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
420 TII.get(Opc), DestReg);
421 if (DestReg == ARM::SP || isSub)
422 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
424 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
425 if (DestReg == ARM::SP)
426 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R3)
427 .addReg(ARM::R12, false, false, true);
430 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
431 /// a destreg = basereg + immediate in Thumb code.
433 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
434 MachineBasicBlock::iterator &MBBI,
435 unsigned DestReg, unsigned BaseReg,
436 int NumBytes, const TargetInstrInfo &TII,
437 const ARMRegisterInfo& MRI,
439 bool isSub = NumBytes < 0;
440 unsigned Bytes = (unsigned)NumBytes;
441 if (isSub) Bytes = -NumBytes;
442 bool isMul4 = (Bytes & 3) == 0;
443 bool isTwoAddr = false;
444 bool DstNotEqBase = false;
445 unsigned NumBits = 1;
450 if (DestReg == BaseReg && BaseReg == ARM::SP) {
451 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
454 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
456 } else if (!isSub && BaseReg == ARM::SP) {
459 // r1 = add sp, 100 * 4
463 ExtraOpc = ARM::tADDi3;
472 if (DestReg != BaseReg)
475 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
479 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
480 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
481 if (NumMIs > Threshold) {
482 // This will expand into too many instructions. Load the immediate from a
484 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
490 if (MRI.isLowRegister(DestReg) && MRI.isLowRegister(BaseReg)) {
491 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
492 unsigned Chunk = (1 << 3) - 1;
493 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
495 BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
496 .addReg(BaseReg, false, false, true).addImm(ThisVal);
498 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
499 .addReg(BaseReg, false, false, true);
504 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
506 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
509 // Build the new tADD / tSUB.
511 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
512 .addReg(DestReg).addImm(ThisVal);
514 bool isKill = BaseReg != ARM::SP;
515 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
516 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
519 if (Opc == ARM::tADDrSPi) {
525 Chunk = ((1 << NumBits) - 1) * Scale;
526 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
533 BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
534 .addReg(DestReg, false, false, true)
535 .addImm(((unsigned)NumBytes) & 3);
539 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
540 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
541 bool isThumb, const TargetInstrInfo &TII,
542 const ARMRegisterInfo& MRI,
545 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
548 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
549 Pred, PredReg, TII, dl);
552 void ARMRegisterInfo::
553 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator I) const {
555 if (!hasReservedCallFrame(MF)) {
556 // If we have alloca, convert as follows:
557 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
558 // ADJCALLSTACKUP -> add, sp, sp, amount
559 MachineInstr *Old = I;
560 DebugLoc dl = Old->getDebugLoc();
561 unsigned Amount = Old->getOperand(0).getImm();
563 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
564 // We need to keep the stack aligned properly. To do this, we round the
565 // amount of space needed for the outgoing arguments up to the next
566 // alignment boundary.
567 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
568 Amount = (Amount+Align-1)/Align*Align;
570 // Replace the pseudo instruction with a new instruction...
571 unsigned Opc = Old->getOpcode();
572 bool isThumb = AFI->isThumbFunction();
573 ARMCC::CondCodes Pred = isThumb
574 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
575 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
576 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
577 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
578 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl);
580 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
581 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
582 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
583 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl);
590 /// emitThumbConstant - Emit a series of instructions to materialize a
592 static void emitThumbConstant(MachineBasicBlock &MBB,
593 MachineBasicBlock::iterator &MBBI,
594 unsigned DestReg, int Imm,
595 const TargetInstrInfo &TII,
596 const ARMRegisterInfo& MRI,
598 bool isSub = Imm < 0;
599 if (isSub) Imm = -Imm;
601 int Chunk = (1 << 8) - 1;
602 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
604 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
606 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
608 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
609 .addReg(DestReg, false, false, true);
612 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
613 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
614 /// register first and then a spilled callee-saved register if that fails.
616 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
617 ARMFunctionInfo *AFI) {
618 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
620 // Try a already spilled CS register.
621 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
626 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
627 int SPAdj, RegScavenger *RS) const{
629 MachineInstr &MI = *II;
630 MachineBasicBlock &MBB = *MI.getParent();
631 MachineFunction &MF = *MBB.getParent();
632 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
633 bool isThumb = AFI->isThumbFunction();
634 DebugLoc dl = MI.getDebugLoc();
636 while (!MI.getOperand(i).isFI()) {
638 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
641 unsigned FrameReg = ARM::SP;
642 int FrameIndex = MI.getOperand(i).getIndex();
643 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
644 MF.getFrameInfo()->getStackSize() + SPAdj;
646 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
647 Offset -= AFI->getGPRCalleeSavedArea1Offset();
648 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
649 Offset -= AFI->getGPRCalleeSavedArea2Offset();
650 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
651 Offset -= AFI->getDPRCalleeSavedAreaOffset();
652 else if (hasFP(MF)) {
653 assert(SPAdj == 0 && "Unexpected");
654 // There is alloca()'s in this function, must reference off the frame
656 FrameReg = getFrameRegister(MF);
657 Offset -= AFI->getFramePtrSpillOffset();
660 unsigned Opcode = MI.getOpcode();
661 const TargetInstrDesc &Desc = MI.getDesc();
662 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
665 if (Opcode == ARM::ADDri) {
666 Offset += MI.getOperand(i+1).getImm();
668 // Turn it into a move.
669 MI.setDesc(TII.get(ARM::MOVr));
670 MI.getOperand(i).ChangeToRegister(FrameReg, false);
671 MI.RemoveOperand(i+1);
673 } else if (Offset < 0) {
676 MI.setDesc(TII.get(ARM::SUBri));
679 // Common case: small offset, fits into instruction.
680 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
681 if (ImmedOffset != -1) {
682 // Replace the FrameIndex with sp / fp
683 MI.getOperand(i).ChangeToRegister(FrameReg, false);
684 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
688 // Otherwise, we fallback to common code below to form the imm offset with
689 // a sequence of ADDri instructions. First though, pull as much of the imm
690 // into this ADDri as possible.
691 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
692 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
694 // We will handle these bits from offset, clear them.
695 Offset &= ~ThisImmVal;
697 // Get the properly encoded SOImmVal field.
698 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
699 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
700 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
701 } else if (Opcode == ARM::tADDrSPi) {
702 Offset += MI.getOperand(i+1).getImm();
704 // Can't use tADDrSPi if it's based off the frame pointer.
705 unsigned NumBits = 0;
707 if (FrameReg != ARM::SP) {
708 Opcode = ARM::tADDi3;
709 MI.setDesc(TII.get(ARM::tADDi3));
714 assert((Offset & 3) == 0 &&
715 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
719 // Turn it into a move.
720 MI.setDesc(TII.get(ARM::tMOVr));
721 MI.getOperand(i).ChangeToRegister(FrameReg, false);
722 MI.RemoveOperand(i+1);
726 // Common case: small offset, fits into instruction.
727 unsigned Mask = (1 << NumBits) - 1;
728 if (((Offset / Scale) & ~Mask) == 0) {
729 // Replace the FrameIndex with sp / fp
730 MI.getOperand(i).ChangeToRegister(FrameReg, false);
731 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
735 unsigned DestReg = MI.getOperand(0).getReg();
736 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
737 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
738 // MI would expand into a large number of instructions. Don't try to
739 // simplify the immediate.
741 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
748 // Translate r0 = add sp, imm to
749 // r0 = add sp, 255*4
750 // r0 = add r0, (imm - 255*4)
751 MI.getOperand(i).ChangeToRegister(FrameReg, false);
752 MI.getOperand(i+1).ChangeToImmediate(Mask);
753 Offset = (Offset - Mask * Scale);
754 MachineBasicBlock::iterator NII = next(II);
755 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
758 // Translate r0 = add sp, -imm to
759 // r0 = -imm (this is then translated into a series of instructons)
761 emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
762 MI.setDesc(TII.get(ARM::tADDhirr));
763 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
764 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
770 unsigned NumBits = 0;
773 case ARMII::AddrMode2: {
775 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
776 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
781 case ARMII::AddrMode3: {
783 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
784 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
789 case ARMII::AddrMode5: {
791 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
792 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
798 case ARMII::AddrModeTs: {
800 InstrOffs = MI.getOperand(ImmIdx).getImm();
801 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
806 assert(0 && "Unsupported addressing mode!");
811 Offset += InstrOffs * Scale;
812 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
813 if (Offset < 0 && !isThumb) {
818 // Common case: small offset, fits into instruction.
819 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
820 int ImmedOffset = Offset / Scale;
821 unsigned Mask = (1 << NumBits) - 1;
822 if ((unsigned)Offset <= Mask * Scale) {
823 // Replace the FrameIndex with sp
824 MI.getOperand(i).ChangeToRegister(FrameReg, false);
826 ImmedOffset |= 1 << NumBits;
827 ImmOp.ChangeToImmediate(ImmedOffset);
831 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
832 if (AddrMode == ARMII::AddrModeTs) {
833 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
834 // a different base register.
836 Mask = (1 << NumBits) - 1;
838 // If this is a thumb spill / restore, we will be using a constpool load to
839 // materialize the offset.
840 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
841 ImmOp.ChangeToImmediate(0);
843 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
844 ImmedOffset = ImmedOffset & Mask;
846 ImmedOffset |= 1 << NumBits;
847 ImmOp.ChangeToImmediate(ImmedOffset);
848 Offset &= ~(Mask*Scale);
852 // If we get here, the immediate doesn't fit into the instruction. We folded
853 // as much as possible above, handle the rest, providing a register that is
855 assert(Offset && "This code isn't needed if offset already handled!");
858 if (Desc.mayLoad()) {
859 // Use the destination register to materialize sp + offset.
860 unsigned TmpReg = MI.getOperand(0).getReg();
862 if (Opcode == ARM::tRestore) {
863 if (FrameReg == ARM::SP)
864 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
865 Offset, false, TII, *this, dl);
867 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
872 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
874 MI.setDesc(TII.get(ARM::tLDR));
875 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
877 // Use [reg, reg] addrmode.
878 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
879 else // tLDR has an extra register operand.
880 MI.addOperand(MachineOperand::CreateReg(0, false));
881 } else if (Desc.mayStore()) {
882 // FIXME! This is horrific!!! We need register scavenging.
883 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
884 // also a ABI register so it's possible that is is the register that is
885 // being storing here. If that's the case, we do the following:
887 // Use r2 to materialize sp + offset
890 unsigned ValReg = MI.getOperand(0).getReg();
891 unsigned TmpReg = ARM::R3;
893 if (ValReg == ARM::R3) {
894 BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
895 .addReg(ARM::R2, false, false, true);
898 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
899 BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
900 .addReg(ARM::R3, false, false, true);
901 if (Opcode == ARM::tSpill) {
902 if (FrameReg == ARM::SP)
903 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
904 Offset, false, TII, *this, dl);
906 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
911 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
913 MI.setDesc(TII.get(ARM::tSTR));
914 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
915 if (UseRR) // Use [reg, reg] addrmode.
916 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
917 else // tSTR has an extra register operand.
918 MI.addOperand(MachineOperand::CreateReg(0, false));
920 MachineBasicBlock::iterator NII = next(II);
921 if (ValReg == ARM::R3)
922 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R2)
923 .addReg(ARM::R12, false, false, true);
924 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
925 BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R3)
926 .addReg(ARM::R12, false, false, true);
928 assert(false && "Unexpected opcode!");
930 // Insert a set of r12 with the full address: r12 = sp + offset
931 // If the offset we have is too large to fit into the instruction, we need
932 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
934 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
936 // No register is "free". Scavenge a register.
937 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
938 int PIdx = MI.findFirstPredOperandIdx();
939 ARMCC::CondCodes Pred = (PIdx == -1)
940 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
941 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
942 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
943 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
944 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
948 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
949 const MachineFrameInfo *FFI = MF.getFrameInfo();
951 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
952 int FixedOff = -FFI->getObjectOffset(i);
953 if (FixedOff > Offset) Offset = FixedOff;
955 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
956 if (FFI->isDeadObjectIndex(i))
958 Offset += FFI->getObjectSize(i);
959 unsigned Align = FFI->getObjectAlignment(i);
960 // Adjust to alignment boundary
961 Offset = (Offset+Align-1)/Align*Align;
963 return (unsigned)Offset;
967 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
968 RegScavenger *RS) const {
969 // This tells PEI to spill the FP as if it is any other callee-save register
970 // to take advantage the eliminateFrameIndex machinery. This also ensures it
971 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
972 // to combine multiple loads / stores.
973 bool CanEliminateFrame = true;
974 bool CS1Spilled = false;
975 bool LRSpilled = false;
976 unsigned NumGPRSpills = 0;
977 SmallVector<unsigned, 4> UnspilledCS1GPRs;
978 SmallVector<unsigned, 4> UnspilledCS2GPRs;
979 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
981 // Don't spill FP if the frame can be eliminated. This is determined
982 // by scanning the callee-save registers to see if any is used.
983 const unsigned *CSRegs = getCalleeSavedRegs();
984 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
985 for (unsigned i = 0; CSRegs[i]; ++i) {
986 unsigned Reg = CSRegs[i];
987 bool Spilled = false;
988 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
989 AFI->setCSRegisterIsSpilled(Reg);
991 CanEliminateFrame = false;
993 // Check alias registers too.
994 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
995 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
997 CanEliminateFrame = false;
1002 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1006 if (!STI.isTargetDarwin()) {
1013 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1028 if (!STI.isTargetDarwin()) {
1029 UnspilledCS1GPRs.push_back(Reg);
1039 UnspilledCS1GPRs.push_back(Reg);
1042 UnspilledCS2GPRs.push_back(Reg);
1049 bool ForceLRSpill = false;
1050 if (!LRSpilled && AFI->isThumbFunction()) {
1051 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
1052 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1053 // use of BL to implement far jump. If it turns out that it's not needed
1054 // then the branch fix up path will undo it.
1055 if (FnSize >= (1 << 11)) {
1056 CanEliminateFrame = false;
1057 ForceLRSpill = true;
1061 bool ExtraCSSpill = false;
1062 if (!CanEliminateFrame || hasFP(MF)) {
1063 AFI->setHasStackFrame(true);
1065 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1066 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1067 if (!LRSpilled && CS1Spilled) {
1068 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1069 AFI->setCSRegisterIsSpilled(ARM::LR);
1071 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1072 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1073 ForceLRSpill = false;
1074 ExtraCSSpill = true;
1077 // Darwin ABI requires FP to point to the stack slot that contains the
1079 if (STI.isTargetDarwin() || hasFP(MF)) {
1080 MF.getRegInfo().setPhysRegUsed(FramePtr);
1084 // If stack and double are 8-byte aligned and we are spilling an odd number
1085 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1086 // the integer and double callee save areas.
1087 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1088 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1089 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1090 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1091 unsigned Reg = UnspilledCS1GPRs[i];
1092 // Don't spiil high register if the function is thumb
1093 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1094 MF.getRegInfo().setPhysRegUsed(Reg);
1095 AFI->setCSRegisterIsSpilled(Reg);
1096 if (!isReservedReg(MF, Reg))
1097 ExtraCSSpill = true;
1101 } else if (!UnspilledCS2GPRs.empty() &&
1102 !AFI->isThumbFunction()) {
1103 unsigned Reg = UnspilledCS2GPRs.front();
1104 MF.getRegInfo().setPhysRegUsed(Reg);
1105 AFI->setCSRegisterIsSpilled(Reg);
1106 if (!isReservedReg(MF, Reg))
1107 ExtraCSSpill = true;
1111 // Estimate if we might need to scavenge a register at some point in order
1112 // to materialize a stack offset. If so, either spill one additiona
1113 // callee-saved register or reserve a special spill slot to facilitate
1114 // register scavenging.
1115 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1116 MachineFrameInfo *MFI = MF.getFrameInfo();
1117 unsigned Size = estimateStackSize(MF, MFI);
1118 unsigned Limit = (1 << 12) - 1;
1119 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1120 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1121 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1122 if (I->getOperand(i).isFI()) {
1123 unsigned Opcode = I->getOpcode();
1124 const TargetInstrDesc &Desc = TII.get(Opcode);
1125 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1126 if (AddrMode == ARMII::AddrMode3) {
1127 Limit = (1 << 8) - 1;
1128 goto DoneEstimating;
1129 } else if (AddrMode == ARMII::AddrMode5) {
1130 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1131 if (ThisLimit < Limit)
1137 if (Size >= Limit) {
1138 // If any non-reserved CS register isn't spilled, just spill one or two
1139 // extra. That should take care of it!
1140 unsigned NumExtras = TargetAlign / 4;
1141 SmallVector<unsigned, 2> Extras;
1142 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1143 unsigned Reg = UnspilledCS1GPRs.back();
1144 UnspilledCS1GPRs.pop_back();
1145 if (!isReservedReg(MF, Reg)) {
1146 Extras.push_back(Reg);
1150 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1151 unsigned Reg = UnspilledCS2GPRs.back();
1152 UnspilledCS2GPRs.pop_back();
1153 if (!isReservedReg(MF, Reg)) {
1154 Extras.push_back(Reg);
1158 if (Extras.size() && NumExtras == 0) {
1159 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1160 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1161 AFI->setCSRegisterIsSpilled(Extras[i]);
1164 // Reserve a slot closest to SP or frame pointer.
1165 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1166 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1167 RC->getAlignment()));
1174 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1175 AFI->setCSRegisterIsSpilled(ARM::LR);
1176 AFI->setLRIsSpilledForFarJump(true);
1180 /// Move iterator pass the next bunch of callee save load / store ops for
1181 /// the particular spill area (1: integer area 1, 2: integer area 2,
1182 /// 3: fp area, 0: don't care).
1183 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1184 MachineBasicBlock::iterator &MBBI,
1185 int Opc, unsigned Area,
1186 const ARMSubtarget &STI) {
1187 while (MBBI != MBB.end() &&
1188 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1191 unsigned Category = 0;
1192 switch (MBBI->getOperand(0).getReg()) {
1193 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1197 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1198 Category = STI.isTargetDarwin() ? 2 : 1;
1200 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1201 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1208 if (Done || Category != Area)
1216 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1217 MachineBasicBlock &MBB = MF.front();
1218 MachineBasicBlock::iterator MBBI = MBB.begin();
1219 MachineFrameInfo *MFI = MF.getFrameInfo();
1220 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1221 bool isThumb = AFI->isThumbFunction();
1222 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1223 unsigned NumBytes = MFI->getStackSize();
1224 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1225 DebugLoc dl = (MBBI != MBB.end() ?
1226 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1229 // Check if R3 is live in. It might have to be used as a scratch register.
1230 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1231 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1232 if (I->first == ARM::R3) {
1233 AFI->setR3IsLiveIn(true);
1238 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1239 NumBytes = (NumBytes + 3) & ~3;
1240 MFI->setStackSize(NumBytes);
1243 // Determine the sizes of each callee-save spill areas and record which frame
1244 // belongs to which callee-save spill areas.
1245 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1246 int FramePtrSpillFI = 0;
1249 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1252 if (!AFI->hasStackFrame()) {
1254 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1258 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1259 unsigned Reg = CSI[i].getReg();
1260 int FI = CSI[i].getFrameIdx();
1267 if (Reg == FramePtr)
1268 FramePtrSpillFI = FI;
1269 AFI->addGPRCalleeSavedArea1Frame(FI);
1276 if (Reg == FramePtr)
1277 FramePtrSpillFI = FI;
1278 if (STI.isTargetDarwin()) {
1279 AFI->addGPRCalleeSavedArea2Frame(FI);
1282 AFI->addGPRCalleeSavedArea1Frame(FI);
1287 AFI->addDPRCalleeSavedAreaFrame(FI);
1293 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1294 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl);
1295 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1296 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
1298 if (MBBI != MBB.end())
1299 dl = MBBI->getDebugLoc();
1302 // Darwin ABI requires FP to point to the stack slot that contains the
1304 if (STI.isTargetDarwin() || hasFP(MF)) {
1305 MachineInstrBuilder MIB =
1306 BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),
1308 .addFrameIndex(FramePtrSpillFI).addImm(0);
1309 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1313 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1314 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl);
1316 // Build the new SUBri to adjust SP for FP callee-save spill area.
1317 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1318 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl);
1321 // Determine starting offsets of spill areas.
1322 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1323 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1324 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1325 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1326 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1327 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1328 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1330 NumBytes = DPRCSOffset;
1332 // Insert it after all the callee-save spills.
1334 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1335 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1338 if(STI.isTargetELF() && hasFP(MF)) {
1339 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1340 AFI->getFramePtrSpillOffset());
1343 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1344 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1345 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1348 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1349 for (unsigned i = 0; CSRegs[i]; ++i)
1350 if (Reg == CSRegs[i])
1355 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1356 return ((MI->getOpcode() == ARM::FLDD ||
1357 MI->getOpcode() == ARM::LDR ||
1358 MI->getOpcode() == ARM::tRestore) &&
1359 MI->getOperand(1).isFI() &&
1360 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1363 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1364 MachineBasicBlock &MBB) const {
1365 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1366 assert((MBBI->getOpcode() == ARM::BX_RET ||
1367 MBBI->getOpcode() == ARM::tBX_RET ||
1368 MBBI->getOpcode() == ARM::tPOP_RET) &&
1369 "Can only insert epilog into returning blocks");
1370 DebugLoc dl = MBBI->getDebugLoc();
1371 MachineFrameInfo *MFI = MF.getFrameInfo();
1372 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1373 bool isThumb = AFI->isThumbFunction();
1374 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1375 int NumBytes = (int)MFI->getStackSize();
1377 if (!AFI->hasStackFrame()) {
1379 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
1381 // Unwind MBBI to point to first LDR / FLDD.
1382 const unsigned *CSRegs = getCalleeSavedRegs();
1383 if (MBBI != MBB.begin()) {
1386 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1387 if (!isCSRestore(MBBI, CSRegs))
1391 // Move SP to start of FP callee save spill area.
1392 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1393 AFI->getGPRCalleeSavedArea2Size() +
1394 AFI->getDPRCalleeSavedAreaSize());
1397 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1398 // Reset SP based on frame pointer only if the stack frame extends beyond
1399 // frame pointer stack slot or target is ELF and the function has FP.
1401 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
1404 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1406 if (MBBI->getOpcode() == ARM::tBX_RET &&
1407 &MBB.front() != MBBI &&
1408 prior(MBBI)->getOpcode() == ARM::tPOP) {
1409 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1410 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1413 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
1417 // Darwin ABI requires FP to point to the stack slot that contains the
1419 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1420 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1421 // Reset SP based on frame pointer only if the stack frame extends beyond
1422 // frame pointer stack slot or target is ELF and the function has FP.
1423 if (AFI->getGPRCalleeSavedArea2Size() ||
1424 AFI->getDPRCalleeSavedAreaSize() ||
1425 AFI->getDPRCalleeSavedAreaOffset()||
1428 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1430 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1432 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1433 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1435 } else if (NumBytes) {
1436 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl);
1439 // Move SP to start of integer callee save spill area 2.
1440 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1441 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1442 false, TII, *this, dl);
1444 // Move SP to start of integer callee save spill area 1.
1445 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1446 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1447 false, TII, *this, dl);
1449 // Move SP to SP upon entry to the function.
1450 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1451 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1452 false, TII, *this, dl);
1456 if (VARegSaveSize) {
1458 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1459 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1460 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
1462 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
1466 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1472 unsigned ARMRegisterInfo::getRARegister() const {
1476 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1477 if (STI.isTargetDarwin() || hasFP(MF))
1478 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1483 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1484 assert(0 && "What is the exception register");
1488 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1489 assert(0 && "What is the exception handler register");
1493 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1494 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1497 #include "ARMGenRegisterInfo.inc"