1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Target/TargetFrameInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallVector.h"
37 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
38 const ARMSubtarget &sti)
39 : ARMBaseRegisterInfo(tii, sti) {
43 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
44 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
48 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
52 /// emitLoadConstPool - Emits a load from constpool to materialize the
53 /// specified immediate.
54 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator &MBBI,
56 const TargetInstrInfo *TII, DebugLoc dl,
57 unsigned DestReg, int Val,
58 ARMCC::CondCodes Pred,
59 unsigned PredReg) const {
60 MachineFunction &MF = *MBB.getParent();
61 MachineConstantPool *ConstantPool = MF.getConstantPool();
62 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
63 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
65 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
66 .addConstantPoolIndex(Idx)
67 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
71 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
75 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
76 // not required, we reserve argument space for call sites in the function
77 // immediately on entry to the current function. This eliminates the need for
78 // add/sub sp brackets around call sites. Returns true if the call frame is
79 // included as part of the stack frame.
80 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
81 const MachineFrameInfo *FFI = MF.getFrameInfo();
82 unsigned CFSize = FFI->getMaxCallFrameSize();
83 // It's not always a good idea to include the call frame as part of the
84 // stack frame. ARM (especially Thumb) has small immediate offset to
85 // address the stack frame. So a large call frame can cause poor codegen
86 // and may even makes it impossible to scavenge a register.
87 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
90 return !MF.getFrameInfo()->hasVarSizedObjects();
93 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
94 /// a destreg = basereg + immediate in ARM code.
96 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator &MBBI,
98 unsigned DestReg, unsigned BaseReg, int NumBytes,
99 ARMCC::CondCodes Pred, unsigned PredReg,
100 const TargetInstrInfo &TII,
102 bool isSub = NumBytes < 0;
103 if (isSub) NumBytes = -NumBytes;
106 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
107 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
108 assert(ThisVal && "Didn't extract field correctly");
110 // We will handle these bits from offset, clear them.
111 NumBytes &= ~ThisVal;
113 // Get the properly encoded SOImmVal field.
114 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
115 assert(SOImmVal != -1 && "Bit extraction didn't work?");
117 // Build the new ADD / SUB.
118 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
119 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
120 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
126 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
127 const TargetInstrInfo &TII, DebugLoc dl,
129 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
130 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
131 Pred, PredReg, TII, dl);
134 void ARMRegisterInfo::
135 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
136 MachineBasicBlock::iterator I) const {
137 if (!hasReservedCallFrame(MF)) {
138 // If we have alloca, convert as follows:
139 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
140 // ADJCALLSTACKUP -> add, sp, sp, amount
141 MachineInstr *Old = I;
142 DebugLoc dl = Old->getDebugLoc();
143 unsigned Amount = Old->getOperand(0).getImm();
145 // We need to keep the stack aligned properly. To do this, we round the
146 // amount of space needed for the outgoing arguments up to the next
147 // alignment boundary.
148 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
149 Amount = (Amount+Align-1)/Align*Align;
151 // Replace the pseudo instruction with a new instruction...
152 unsigned Opc = Old->getOpcode();
153 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
154 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
155 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
156 unsigned PredReg = Old->getOperand(2).getReg();
157 emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
159 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
160 unsigned PredReg = Old->getOperand(3).getReg();
161 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
162 emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
169 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
170 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
171 /// register first and then a spilled callee-saved register if that fails.
173 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
174 ARMFunctionInfo *AFI) {
175 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
176 assert (!AFI->isThumbFunction());
178 // Try a already spilled CS register.
179 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
184 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
185 int SPAdj, RegScavenger *RS) const{
187 MachineInstr &MI = *II;
188 MachineBasicBlock &MBB = *MI.getParent();
189 MachineFunction &MF = *MBB.getParent();
190 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
191 DebugLoc dl = MI.getDebugLoc();
193 while (!MI.getOperand(i).isFI()) {
195 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
198 unsigned FrameReg = ARM::SP;
199 int FrameIndex = MI.getOperand(i).getIndex();
200 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
201 MF.getFrameInfo()->getStackSize() + SPAdj;
203 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
204 Offset -= AFI->getGPRCalleeSavedArea1Offset();
205 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
206 Offset -= AFI->getGPRCalleeSavedArea2Offset();
207 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
208 Offset -= AFI->getDPRCalleeSavedAreaOffset();
209 else if (hasFP(MF)) {
210 assert(SPAdj == 0 && "Unexpected");
211 // There is alloca()'s in this function, must reference off the frame
213 FrameReg = getFrameRegister(MF);
214 Offset -= AFI->getFramePtrSpillOffset();
217 unsigned Opcode = MI.getOpcode();
218 const TargetInstrDesc &Desc = MI.getDesc();
219 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
222 // Memory operands in inline assembly always use AddrMode2.
223 if (Opcode == ARM::INLINEASM)
224 AddrMode = ARMII::AddrMode2;
226 if (Opcode == ARM::ADDri) {
227 Offset += MI.getOperand(i+1).getImm();
229 // Turn it into a move.
230 MI.setDesc(TII.get(ARM::MOVr));
231 MI.getOperand(i).ChangeToRegister(FrameReg, false);
232 MI.RemoveOperand(i+1);
234 } else if (Offset < 0) {
237 MI.setDesc(TII.get(ARM::SUBri));
240 // Common case: small offset, fits into instruction.
241 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
242 if (ImmedOffset != -1) {
243 // Replace the FrameIndex with sp / fp
244 MI.getOperand(i).ChangeToRegister(FrameReg, false);
245 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
249 // Otherwise, we fallback to common code below to form the imm offset with
250 // a sequence of ADDri instructions. First though, pull as much of the imm
251 // into this ADDri as possible.
252 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
253 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
255 // We will handle these bits from offset, clear them.
256 Offset &= ~ThisImmVal;
258 // Get the properly encoded SOImmVal field.
259 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
260 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
261 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
265 unsigned NumBits = 0;
268 case ARMII::AddrMode2: {
270 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
271 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
276 case ARMII::AddrMode3: {
278 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
279 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
284 case ARMII::AddrMode5: {
286 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
287 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
294 LLVM_UNREACHABLE("Unsupported addressing mode!");
298 Offset += InstrOffs * Scale;
299 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
305 // Common case: small offset, fits into instruction.
306 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
307 int ImmedOffset = Offset / Scale;
308 unsigned Mask = (1 << NumBits) - 1;
309 if ((unsigned)Offset <= Mask * Scale) {
310 // Replace the FrameIndex with sp
311 MI.getOperand(i).ChangeToRegister(FrameReg, false);
313 ImmedOffset |= 1 << NumBits;
314 ImmOp.ChangeToImmediate(ImmedOffset);
318 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
319 ImmedOffset = ImmedOffset & Mask;
321 ImmedOffset |= 1 << NumBits;
322 ImmOp.ChangeToImmediate(ImmedOffset);
323 Offset &= ~(Mask*Scale);
326 // If we get here, the immediate doesn't fit into the instruction. We folded
327 // as much as possible above, handle the rest, providing a register that is
329 assert(Offset && "This code isn't needed if offset already handled!");
331 // Insert a set of r12 with the full address: r12 = sp + offset
332 // If the offset we have is too large to fit into the instruction, we need
333 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
335 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
337 // No register is "free". Scavenge a register.
338 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
339 int PIdx = MI.findFirstPredOperandIdx();
340 ARMCC::CondCodes Pred = (PIdx == -1)
341 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
342 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
343 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
344 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
345 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
348 /// Move iterator pass the next bunch of callee save load / store ops for
349 /// the particular spill area (1: integer area 1, 2: integer area 2,
350 /// 3: fp area, 0: don't care).
351 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI,
353 int Opc, unsigned Area,
354 const ARMSubtarget &STI) {
355 while (MBBI != MBB.end() &&
356 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
359 unsigned Category = 0;
360 switch (MBBI->getOperand(0).getReg()) {
361 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
365 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
366 Category = STI.isTargetDarwin() ? 2 : 1;
368 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
369 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
376 if (Done || Category != Area)
384 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
385 MachineBasicBlock &MBB = MF.front();
386 MachineBasicBlock::iterator MBBI = MBB.begin();
387 MachineFrameInfo *MFI = MF.getFrameInfo();
388 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
389 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
390 unsigned NumBytes = MFI->getStackSize();
391 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
392 DebugLoc dl = (MBBI != MBB.end() ?
393 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
395 // Determine the sizes of each callee-save spill areas and record which frame
396 // belongs to which callee-save spill areas.
397 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
398 int FramePtrSpillFI = 0;
401 emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
403 if (!AFI->hasStackFrame()) {
405 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
409 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
410 unsigned Reg = CSI[i].getReg();
411 int FI = CSI[i].getFrameIdx();
419 FramePtrSpillFI = FI;
420 AFI->addGPRCalleeSavedArea1Frame(FI);
428 FramePtrSpillFI = FI;
429 if (STI.isTargetDarwin()) {
430 AFI->addGPRCalleeSavedArea2Frame(FI);
433 AFI->addGPRCalleeSavedArea1Frame(FI);
438 AFI->addDPRCalleeSavedAreaFrame(FI);
443 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
444 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
445 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
447 // Darwin ABI requires FP to point to the stack slot that contains the
449 if (STI.isTargetDarwin() || hasFP(MF)) {
450 MachineInstrBuilder MIB =
451 BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
452 .addFrameIndex(FramePtrSpillFI).addImm(0);
453 AddDefaultCC(AddDefaultPred(MIB));
456 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
457 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
459 // Build the new SUBri to adjust SP for FP callee-save spill area.
460 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
461 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
463 // Determine starting offsets of spill areas.
464 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
465 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
466 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
467 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
468 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
469 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
470 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
472 NumBytes = DPRCSOffset;
474 // Insert it after all the callee-save spills.
475 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
476 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
479 if (STI.isTargetELF() && hasFP(MF)) {
480 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
481 AFI->getFramePtrSpillOffset());
484 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
485 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
486 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
489 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
490 for (unsigned i = 0; CSRegs[i]; ++i)
491 if (Reg == CSRegs[i])
496 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
497 return ((MI->getOpcode() == ARM::FLDD ||
498 MI->getOpcode() == ARM::LDR) &&
499 MI->getOperand(1).isFI() &&
500 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
503 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
504 MachineBasicBlock &MBB) const {
505 MachineBasicBlock::iterator MBBI = prior(MBB.end());
506 assert(MBBI->getOpcode() == ARM::BX_RET &&
507 "Can only insert epilog into returning blocks");
508 DebugLoc dl = MBBI->getDebugLoc();
509 MachineFrameInfo *MFI = MF.getFrameInfo();
510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
511 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
512 int NumBytes = (int)MFI->getStackSize();
514 if (!AFI->hasStackFrame()) {
516 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
518 // Unwind MBBI to point to first LDR / FLDD.
519 const unsigned *CSRegs = getCalleeSavedRegs();
520 if (MBBI != MBB.begin()) {
523 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
524 if (!isCSRestore(MBBI, CSRegs))
528 // Move SP to start of FP callee save spill area.
529 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
530 AFI->getGPRCalleeSavedArea2Size() +
531 AFI->getDPRCalleeSavedAreaSize());
533 // Darwin ABI requires FP to point to the stack slot that contains the
535 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
536 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
537 // Reset SP based on frame pointer only if the stack frame extends beyond
538 // frame pointer stack slot or target is ELF and the function has FP.
539 if (AFI->getGPRCalleeSavedArea2Size() ||
540 AFI->getDPRCalleeSavedAreaSize() ||
541 AFI->getDPRCalleeSavedAreaOffset()||
544 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
546 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
548 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
549 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
551 } else if (NumBytes) {
552 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
555 // Move SP to start of integer callee save spill area 2.
556 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
557 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
559 // Move SP to start of integer callee save spill area 1.
560 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
561 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
563 // Move SP to SP upon entry to the function.
564 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
565 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
569 emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);