1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addRegOperand(Reg, true);
135 void ARMRegisterInfo::
136 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
137 unsigned SrcReg, int FI,
138 const TargetRegisterClass *RC) const {
139 if (RC == ARM::GPRRegisterClass) {
140 MachineFunction &MF = *MBB.getParent();
141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
142 if (AFI->isThumbFunction())
143 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
144 .addFrameIndex(FI).addImm(0);
146 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
147 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
149 } else if (RC == ARM::DPRRegisterClass) {
150 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
151 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
153 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
154 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
155 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
159 void ARMRegisterInfo::
160 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
161 unsigned DestReg, int FI,
162 const TargetRegisterClass *RC) const {
163 if (RC == ARM::GPRRegisterClass) {
164 MachineFunction &MF = *MBB.getParent();
165 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
166 if (AFI->isThumbFunction())
167 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
168 .addFrameIndex(FI).addImm(0);
170 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
171 .addFrameIndex(FI).addReg(0).addImm(0).addImm((int64_t)ARMCC::AL)
173 } else if (RC == ARM::DPRRegisterClass) {
174 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
175 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
177 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
178 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
179 .addFrameIndex(FI).addImm(0).addImm((int64_t)ARMCC::AL).addReg(0);
183 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator I,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *DestRC,
187 const TargetRegisterClass *SrcRC) const {
188 if (DestRC != SrcRC) {
189 cerr << "Not yet supported!";
193 if (DestRC == ARM::GPRRegisterClass) {
194 MachineFunction &MF = *MBB.getParent();
195 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
196 if (AFI->isThumbFunction())
197 BuildMI(MBB, I, TII.get(ARM::tMOVr), DestReg).addReg(SrcReg);
199 BuildMI(MBB, I, TII.get(ARM::MOVr), DestReg).addReg(SrcReg)
200 .addImm((int64_t)ARMCC::AL).addReg(0).addReg(0);
201 } else if (DestRC == ARM::SPRRegisterClass)
202 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg)
203 .addImm((int64_t)ARMCC::AL).addReg(0);
204 else if (DestRC == ARM::DPRRegisterClass)
205 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg)
206 .addImm((int64_t)ARMCC::AL).addReg(0);
211 /// emitLoadConstPool - Emits a load from constpool to materialize the
212 /// specified immediate.
213 static void emitLoadConstPool(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator &MBBI,
215 unsigned DestReg, int Val,
216 ARMCC::CondCodes Pred, unsigned PredReg,
217 const TargetInstrInfo &TII, bool isThumb) {
218 MachineFunction &MF = *MBB.getParent();
219 MachineConstantPool *ConstantPool = MF.getConstantPool();
220 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
221 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
223 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
225 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
226 .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
229 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator I,
232 const MachineInstr *Orig) const {
233 if (Orig->getOpcode() == ARM::MOVi2pieces) {
234 emitLoadConstPool(MBB, I, DestReg,
235 Orig->getOperand(1).getImmedValue(),
236 (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
237 Orig->getOperand(3).getReg(),
242 MachineInstr *MI = Orig->clone();
243 MI->getOperand(0).setReg(DestReg);
247 /// isLowRegister - Returns true if the register is low register r0-r7.
249 static bool isLowRegister(unsigned Reg) {
252 case R0: case R1: case R2: case R3:
253 case R4: case R5: case R6: case R7:
260 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
261 unsigned OpNum, int FI) const {
262 unsigned Opc = MI->getOpcode();
263 MachineInstr *NewMI = NULL;
267 if (MI->getOperand(4).getReg() == ARM::CPSR)
268 // If it is updating CPSR, then it cannot be foled.
270 unsigned Pred = MI->getOperand(2).getImmedValue();
271 unsigned PredReg = MI->getOperand(3).getReg();
272 if (OpNum == 0) { // move -> store
273 unsigned SrcReg = MI->getOperand(1).getReg();
274 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
275 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
276 } else { // move -> load
277 unsigned DstReg = MI->getOperand(0).getReg();
278 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
279 .addImm(0).addImm(Pred).addReg(PredReg);
284 if (OpNum == 0) { // move -> store
285 unsigned SrcReg = MI->getOperand(1).getReg();
286 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
287 // tSpill cannot take a high register operand.
289 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
291 } else { // move -> load
292 unsigned DstReg = MI->getOperand(0).getReg();
293 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
294 // tRestore cannot target a high register operand.
296 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
302 unsigned Pred = MI->getOperand(2).getImmedValue();
303 unsigned PredReg = MI->getOperand(3).getReg();
304 if (OpNum == 0) { // move -> store
305 unsigned SrcReg = MI->getOperand(1).getReg();
306 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
307 .addImm(0).addImm(Pred).addReg(PredReg);
308 } else { // move -> load
309 unsigned DstReg = MI->getOperand(0).getReg();
310 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
311 .addImm(0).addImm(Pred).addReg(PredReg);
316 unsigned Pred = MI->getOperand(2).getImmedValue();
317 unsigned PredReg = MI->getOperand(3).getReg();
318 if (OpNum == 0) { // move -> store
319 unsigned SrcReg = MI->getOperand(1).getReg();
320 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
321 .addImm(0).addImm(Pred).addReg(PredReg);
322 } else { // move -> load
323 unsigned DstReg = MI->getOperand(0).getReg();
324 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
325 .addImm(0).addImm(Pred).addReg(PredReg);
332 NewMI->copyKillDeadInfo(MI);
337 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
338 static const unsigned CalleeSavedRegs[] = {
339 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
340 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
342 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
343 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
347 static const unsigned DarwinCalleeSavedRegs[] = {
348 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
349 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
351 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
352 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
355 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
358 const TargetRegisterClass* const *
359 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
360 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
361 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
362 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
363 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
365 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
366 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
369 return CalleeSavedRegClasses;
372 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
373 // FIXME: avoid re-calculating this everytime.
374 BitVector Reserved(getNumRegs());
375 Reserved.set(ARM::SP);
376 Reserved.set(ARM::PC);
377 if (STI.isTargetDarwin() || hasFP(MF))
378 Reserved.set(FramePtr);
379 // Some targets reserve R9.
380 if (STI.isR9Reserved())
381 Reserved.set(ARM::R9);
386 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
394 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
398 return STI.isR9Reserved();
405 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
406 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
407 return ThumbRegScavenging || !AFI->isThumbFunction();
410 /// hasFP - Return true if the specified function should have a dedicated frame
411 /// pointer register. This is true if the function has variable sized allocas
412 /// or if frame pointer elimination is disabled.
414 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
415 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
418 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
419 // not required, we reserve argument space for call sites in the function
420 // immediately on entry to the current function. This eliminates the need for
421 // add/sub sp brackets around call sites. Returns true if the call frame is
422 // included as part of the stack frame.
423 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
424 const MachineFrameInfo *FFI = MF.getFrameInfo();
425 unsigned CFSize = FFI->getMaxCallFrameSize();
426 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
427 // It's not always a good idea to include the call frame as part of the
428 // stack frame. ARM (especially Thumb) has small immediate offset to
429 // address the stack frame. So a large call frame can cause poor codegen
430 // and may even makes it impossible to scavenge a register.
431 if (AFI->isThumbFunction()) {
432 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
435 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
438 return !MF.getFrameInfo()->hasVarSizedObjects();
441 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
442 /// a destreg = basereg + immediate in ARM code.
444 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
445 MachineBasicBlock::iterator &MBBI,
446 unsigned DestReg, unsigned BaseReg, int NumBytes,
447 ARMCC::CondCodes Pred, unsigned PredReg,
448 const TargetInstrInfo &TII) {
449 bool isSub = NumBytes < 0;
450 if (isSub) NumBytes = -NumBytes;
453 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
454 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
455 assert(ThisVal && "Didn't extract field correctly");
457 // We will handle these bits from offset, clear them.
458 NumBytes &= ~ThisVal;
460 // Get the properly encoded SOImmVal field.
461 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
462 assert(SOImmVal != -1 && "Bit extraction didn't work?");
464 // Build the new ADD / SUB.
465 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
466 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
467 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
472 /// calcNumMI - Returns the number of instructions required to materialize
473 /// the specific add / sub r, c instruction.
474 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
475 unsigned NumBits, unsigned Scale) {
477 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
479 if (Opc == ARM::tADDrSPi) {
480 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
484 Scale = 1; // Followed by a number of tADDi8.
485 Chunk = ((1 << NumBits) - 1) * Scale;
488 NumMIs += Bytes / Chunk;
489 if ((Bytes % Chunk) != 0)
496 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
497 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
498 /// in a register using mov / mvn sequences or load the immediate from a
501 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
502 MachineBasicBlock::iterator &MBBI,
503 unsigned DestReg, unsigned BaseReg,
504 int NumBytes, bool CanChangeCC,
505 const TargetInstrInfo &TII) {
506 bool isHigh = !isLowRegister(DestReg) ||
507 (BaseReg != 0 && !isLowRegister(BaseReg));
509 // Subtract doesn't have high register version. Load the negative value
510 // if either base or dest register is a high register. Also, if do not
511 // issue sub as part of the sequence if condition register is to be
513 if (NumBytes < 0 && !isHigh && CanChangeCC) {
515 NumBytes = -NumBytes;
517 unsigned LdReg = DestReg;
518 if (DestReg == ARM::SP) {
519 assert(BaseReg == ARM::SP && "Unexpected!");
521 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
522 .addReg(ARM::R3, false, false, true);
525 if (NumBytes <= 255 && NumBytes >= 0)
526 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
527 else if (NumBytes < 0 && NumBytes >= -255) {
528 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
529 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
530 .addReg(LdReg, false, false, true);
532 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
535 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
536 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
537 if (DestReg == ARM::SP || isSub)
538 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
540 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
541 if (DestReg == ARM::SP)
542 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
543 .addReg(ARM::R12, false, false, true);
546 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
547 /// a destreg = basereg + immediate in Thumb code.
549 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
550 MachineBasicBlock::iterator &MBBI,
551 unsigned DestReg, unsigned BaseReg,
552 int NumBytes, const TargetInstrInfo &TII) {
553 bool isSub = NumBytes < 0;
554 unsigned Bytes = (unsigned)NumBytes;
555 if (isSub) Bytes = -NumBytes;
556 bool isMul4 = (Bytes & 3) == 0;
557 bool isTwoAddr = false;
558 bool DstNotEqBase = false;
559 unsigned NumBits = 1;
564 if (DestReg == BaseReg && BaseReg == ARM::SP) {
565 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
568 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
570 } else if (!isSub && BaseReg == ARM::SP) {
573 // r1 = add sp, 100 * 4
577 ExtraOpc = ARM::tADDi3;
586 if (DestReg != BaseReg)
589 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
593 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
594 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
595 if (NumMIs > Threshold) {
596 // This will expand into too many instructions. Load the immediate from a
598 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
603 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
604 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
605 unsigned Chunk = (1 << 3) - 1;
606 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
608 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
609 .addReg(BaseReg, false, false, true).addImm(ThisVal);
611 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
612 .addReg(BaseReg, false, false, true);
617 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
619 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
622 // Build the new tADD / tSUB.
624 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
626 bool isKill = BaseReg != ARM::SP;
627 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
628 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
631 if (Opc == ARM::tADDrSPi) {
637 Chunk = ((1 << NumBits) - 1) * Scale;
638 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
645 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
646 .addReg(DestReg, false, false, true)
647 .addImm(((unsigned)NumBytes) & 3);
651 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
652 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
653 bool isThumb, const TargetInstrInfo &TII) {
655 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
657 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
661 void ARMRegisterInfo::
662 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
663 MachineBasicBlock::iterator I) const {
664 if (!hasReservedCallFrame(MF)) {
665 // If we have alloca, convert as follows:
666 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
667 // ADJCALLSTACKUP -> add, sp, sp, amount
668 MachineInstr *Old = I;
669 unsigned Amount = Old->getOperand(0).getImmedValue();
671 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
672 // We need to keep the stack aligned properly. To do this, we round the
673 // amount of space needed for the outgoing arguments up to the next
674 // alignment boundary.
675 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
676 Amount = (Amount+Align-1)/Align*Align;
678 // Replace the pseudo instruction with a new instruction...
679 unsigned Opc = Old->getOpcode();
680 bool isThumb = AFI->isThumbFunction();
681 ARMCC::CondCodes Pred = isThumb
682 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
683 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
684 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
685 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
687 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
688 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
695 /// emitThumbConstant - Emit a series of instructions to materialize a
697 static void emitThumbConstant(MachineBasicBlock &MBB,
698 MachineBasicBlock::iterator &MBBI,
699 unsigned DestReg, int Imm,
700 const TargetInstrInfo &TII) {
701 bool isSub = Imm < 0;
702 if (isSub) Imm = -Imm;
704 int Chunk = (1 << 8) - 1;
705 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
707 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
709 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
711 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
712 .addReg(DestReg, false, false, true);
715 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
716 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
717 /// register first and then a spilled callee-saved register if that fails.
719 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
720 ARMFunctionInfo *AFI) {
721 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
723 // Try a already spilled CS register.
724 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
729 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
730 int SPAdj, RegScavenger *RS) const{
732 MachineInstr &MI = *II;
733 MachineBasicBlock &MBB = *MI.getParent();
734 MachineFunction &MF = *MBB.getParent();
735 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
736 bool isThumb = AFI->isThumbFunction();
738 while (!MI.getOperand(i).isFrameIndex()) {
740 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
743 unsigned FrameReg = ARM::SP;
744 int FrameIndex = MI.getOperand(i).getFrameIndex();
745 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
746 MF.getFrameInfo()->getStackSize() + SPAdj;
748 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
749 Offset -= AFI->getGPRCalleeSavedArea1Offset();
750 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
751 Offset -= AFI->getGPRCalleeSavedArea2Offset();
752 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
753 Offset -= AFI->getDPRCalleeSavedAreaOffset();
754 else if (hasFP(MF)) {
755 assert(SPAdj == 0 && "Unexpected");
756 // There is alloca()'s in this function, must reference off the frame
758 FrameReg = getFrameRegister(MF);
759 Offset -= AFI->getFramePtrSpillOffset();
762 unsigned Opcode = MI.getOpcode();
763 const TargetInstrDescriptor &Desc = TII.get(Opcode);
764 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
767 if (Opcode == ARM::ADDri) {
768 Offset += MI.getOperand(i+1).getImm();
770 // Turn it into a move.
771 MI.setInstrDescriptor(TII.get(ARM::MOVr));
772 MI.getOperand(i).ChangeToRegister(FrameReg, false);
773 MI.RemoveOperand(i+1);
775 } else if (Offset < 0) {
778 MI.setInstrDescriptor(TII.get(ARM::SUBri));
781 // Common case: small offset, fits into instruction.
782 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
783 if (ImmedOffset != -1) {
784 // Replace the FrameIndex with sp / fp
785 MI.getOperand(i).ChangeToRegister(FrameReg, false);
786 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
790 // Otherwise, we fallback to common code below to form the imm offset with
791 // a sequence of ADDri instructions. First though, pull as much of the imm
792 // into this ADDri as possible.
793 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
794 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
796 // We will handle these bits from offset, clear them.
797 Offset &= ~ThisImmVal;
799 // Get the properly encoded SOImmVal field.
800 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
801 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
802 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
803 } else if (Opcode == ARM::tADDrSPi) {
804 Offset += MI.getOperand(i+1).getImm();
806 // Can't use tADDrSPi if it's based off the frame pointer.
807 unsigned NumBits = 0;
809 if (FrameReg != ARM::SP) {
810 Opcode = ARM::tADDi3;
811 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
816 assert((Offset & 3) == 0 &&
817 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
821 // Turn it into a move.
822 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
823 MI.getOperand(i).ChangeToRegister(FrameReg, false);
824 MI.RemoveOperand(i+1);
828 // Common case: small offset, fits into instruction.
829 unsigned Mask = (1 << NumBits) - 1;
830 if (((Offset / Scale) & ~Mask) == 0) {
831 // Replace the FrameIndex with sp / fp
832 MI.getOperand(i).ChangeToRegister(FrameReg, false);
833 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
837 unsigned DestReg = MI.getOperand(0).getReg();
838 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
839 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
840 // MI would expand into a large number of instructions. Don't try to
841 // simplify the immediate.
843 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
849 // Translate r0 = add sp, imm to
850 // r0 = add sp, 255*4
851 // r0 = add r0, (imm - 255*4)
852 MI.getOperand(i).ChangeToRegister(FrameReg, false);
853 MI.getOperand(i+1).ChangeToImmediate(Mask);
854 Offset = (Offset - Mask * Scale);
855 MachineBasicBlock::iterator NII = next(II);
856 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
858 // Translate r0 = add sp, -imm to
859 // r0 = -imm (this is then translated into a series of instructons)
861 emitThumbConstant(MBB, II, DestReg, Offset, TII);
862 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
863 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
864 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
870 unsigned NumBits = 0;
873 case ARMII::AddrMode2: {
875 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
876 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
881 case ARMII::AddrMode3: {
883 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
884 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
889 case ARMII::AddrMode5: {
891 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
892 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
898 case ARMII::AddrModeTs: {
900 InstrOffs = MI.getOperand(ImmIdx).getImm();
901 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
906 assert(0 && "Unsupported addressing mode!");
911 Offset += InstrOffs * Scale;
912 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
913 if (Offset < 0 && !isThumb) {
918 // Common case: small offset, fits into instruction.
919 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
920 int ImmedOffset = Offset / Scale;
921 unsigned Mask = (1 << NumBits) - 1;
922 if ((unsigned)Offset <= Mask * Scale) {
923 // Replace the FrameIndex with sp
924 MI.getOperand(i).ChangeToRegister(FrameReg, false);
926 ImmedOffset |= 1 << NumBits;
927 ImmOp.ChangeToImmediate(ImmedOffset);
931 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
932 if (AddrMode == ARMII::AddrModeTs) {
933 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
934 // a different base register.
936 Mask = (1 << NumBits) - 1;
938 // If this is a thumb spill / restore, we will be using a constpool load to
939 // materialize the offset.
940 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
941 ImmOp.ChangeToImmediate(0);
943 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
944 ImmedOffset = ImmedOffset & Mask;
946 ImmedOffset |= 1 << NumBits;
947 ImmOp.ChangeToImmediate(ImmedOffset);
948 Offset &= ~(Mask*Scale);
952 // If we get here, the immediate doesn't fit into the instruction. We folded
953 // as much as possible above, handle the rest, providing a register that is
955 assert(Offset && "This code isn't needed if offset already handled!");
958 if (TII.isLoad(Opcode)) {
959 // Use the destination register to materialize sp + offset.
960 unsigned TmpReg = MI.getOperand(0).getReg();
962 if (Opcode == ARM::tRestore) {
963 if (FrameReg == ARM::SP)
964 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
966 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
970 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
971 MI.setInstrDescriptor(TII.get(ARM::tLDR));
972 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
974 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
976 MI.addRegOperand(0, false); // tLDR has an extra register operand.
977 } else if (TII.isStore(Opcode)) {
978 // FIXME! This is horrific!!! We need register scavenging.
979 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
980 // also a ABI register so it's possible that is is the register that is
981 // being storing here. If that's the case, we do the following:
983 // Use r2 to materialize sp + offset
986 unsigned ValReg = MI.getOperand(0).getReg();
987 unsigned TmpReg = ARM::R3;
989 if (ValReg == ARM::R3) {
990 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
991 .addReg(ARM::R2, false, false, true);
994 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
995 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
996 .addReg(ARM::R3, false, false, true);
997 if (Opcode == ARM::tSpill) {
998 if (FrameReg == ARM::SP)
999 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
1001 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
1005 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
1006 MI.setInstrDescriptor(TII.get(ARM::tSTR));
1007 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
1009 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
1011 MI.addRegOperand(0, false); // tSTR has an extra register operand.
1013 MachineBasicBlock::iterator NII = next(II);
1014 if (ValReg == ARM::R3)
1015 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
1016 .addReg(ARM::R12, false, false, true);
1017 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
1018 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
1019 .addReg(ARM::R12, false, false, true);
1021 assert(false && "Unexpected opcode!");
1023 // Insert a set of r12 with the full address: r12 = sp + offset
1024 // If the offset we have is too large to fit into the instruction, we need
1025 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1027 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1028 if (ScratchReg == 0)
1029 // No register is "free". Scavenge a register.
1030 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1031 int PIdx = MI.findFirstPredOperandIdx();
1032 ARMCC::CondCodes Pred = (PIdx == -1)
1033 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
1034 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1035 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1036 isSub ? -Offset : Offset, Pred, PredReg, TII);
1037 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1041 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1042 const MachineFrameInfo *FFI = MF.getFrameInfo();
1044 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1045 int FixedOff = -FFI->getObjectOffset(i);
1046 if (FixedOff > Offset) Offset = FixedOff;
1048 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1049 Offset += FFI->getObjectSize(i);
1050 unsigned Align = FFI->getObjectAlignment(i);
1051 // Adjust to alignment boundary
1052 Offset = (Offset+Align-1)/Align*Align;
1054 return (unsigned)Offset;
1058 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1059 RegScavenger *RS) const {
1060 // This tells PEI to spill the FP as if it is any other callee-save register
1061 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1062 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1063 // to combine multiple loads / stores.
1064 bool CanEliminateFrame = true;
1065 bool CS1Spilled = false;
1066 bool LRSpilled = false;
1067 unsigned NumGPRSpills = 0;
1068 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1069 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1070 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1072 // Don't spill FP if the frame can be eliminated. This is determined
1073 // by scanning the callee-save registers to see if any is used.
1074 const unsigned *CSRegs = getCalleeSavedRegs();
1075 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1076 for (unsigned i = 0; CSRegs[i]; ++i) {
1077 unsigned Reg = CSRegs[i];
1078 bool Spilled = false;
1079 if (MF.isPhysRegUsed(Reg)) {
1080 AFI->setCSRegisterIsSpilled(Reg);
1082 CanEliminateFrame = false;
1084 // Check alias registers too.
1085 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1086 if (MF.isPhysRegUsed(*Aliases)) {
1088 CanEliminateFrame = false;
1093 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1097 if (!STI.isTargetDarwin()) {
1104 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1119 if (!STI.isTargetDarwin()) {
1120 UnspilledCS1GPRs.push_back(Reg);
1130 UnspilledCS1GPRs.push_back(Reg);
1133 UnspilledCS2GPRs.push_back(Reg);
1140 bool ForceLRSpill = false;
1141 if (!LRSpilled && AFI->isThumbFunction()) {
1142 unsigned FnSize = ARM::GetFunctionSize(MF);
1143 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1144 // use of BL to implement far jump. If it turns out that it's not needed
1145 // then the branch fix up path will undo it.
1146 if (FnSize >= (1 << 11)) {
1147 CanEliminateFrame = false;
1148 ForceLRSpill = true;
1152 bool ExtraCSSpill = false;
1153 if (!CanEliminateFrame || hasFP(MF)) {
1154 AFI->setHasStackFrame(true);
1156 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1157 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1158 if (!LRSpilled && CS1Spilled) {
1159 MF.setPhysRegUsed(ARM::LR);
1160 AFI->setCSRegisterIsSpilled(ARM::LR);
1162 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1163 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1164 ForceLRSpill = false;
1165 ExtraCSSpill = true;
1168 // Darwin ABI requires FP to point to the stack slot that contains the
1170 if (STI.isTargetDarwin() || hasFP(MF)) {
1171 MF.setPhysRegUsed(FramePtr);
1175 // If stack and double are 8-byte aligned and we are spilling an odd number
1176 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1177 // the integer and double callee save areas.
1178 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1179 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1180 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1181 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1182 unsigned Reg = UnspilledCS1GPRs[i];
1183 // Don't spiil high register if the function is thumb
1184 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1185 MF.setPhysRegUsed(Reg);
1186 AFI->setCSRegisterIsSpilled(Reg);
1187 if (!isReservedReg(MF, Reg))
1188 ExtraCSSpill = true;
1192 } else if (!UnspilledCS2GPRs.empty() &&
1193 !AFI->isThumbFunction()) {
1194 unsigned Reg = UnspilledCS2GPRs.front();
1195 MF.setPhysRegUsed(Reg);
1196 AFI->setCSRegisterIsSpilled(Reg);
1197 if (!isReservedReg(MF, Reg))
1198 ExtraCSSpill = true;
1202 // Estimate if we might need to scavenge a register at some point in order
1203 // to materialize a stack offset. If so, either spill one additiona
1204 // callee-saved register or reserve a special spill slot to facilitate
1205 // register scavenging.
1206 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1207 MachineFrameInfo *MFI = MF.getFrameInfo();
1208 unsigned Size = estimateStackSize(MF, MFI);
1209 unsigned Limit = (1 << 12) - 1;
1210 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1211 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1212 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1213 if (I->getOperand(i).isFrameIndex()) {
1214 unsigned Opcode = I->getOpcode();
1215 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1216 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1217 if (AddrMode == ARMII::AddrMode3) {
1218 Limit = (1 << 8) - 1;
1219 goto DoneEstimating;
1220 } else if (AddrMode == ARMII::AddrMode5) {
1221 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1222 if (ThisLimit < Limit)
1228 if (Size >= Limit) {
1229 // If any non-reserved CS register isn't spilled, just spill one or two
1230 // extra. That should take care of it!
1231 unsigned NumExtras = TargetAlign / 4;
1232 SmallVector<unsigned, 2> Extras;
1233 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1234 unsigned Reg = UnspilledCS1GPRs.back();
1235 UnspilledCS1GPRs.pop_back();
1236 if (!isReservedReg(MF, Reg)) {
1237 Extras.push_back(Reg);
1241 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1242 unsigned Reg = UnspilledCS2GPRs.back();
1243 UnspilledCS2GPRs.pop_back();
1244 if (!isReservedReg(MF, Reg)) {
1245 Extras.push_back(Reg);
1249 if (Extras.size() && NumExtras == 0) {
1250 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1251 MF.setPhysRegUsed(Extras[i]);
1252 AFI->setCSRegisterIsSpilled(Extras[i]);
1255 // Reserve a slot closest to SP or frame pointer.
1256 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1257 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1258 RC->getAlignment()));
1265 MF.setPhysRegUsed(ARM::LR);
1266 AFI->setCSRegisterIsSpilled(ARM::LR);
1267 AFI->setLRIsSpilledForFarJump(true);
1271 /// Move iterator pass the next bunch of callee save load / store ops for
1272 /// the particular spill area (1: integer area 1, 2: integer area 2,
1273 /// 3: fp area, 0: don't care).
1274 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1275 MachineBasicBlock::iterator &MBBI,
1276 int Opc, unsigned Area,
1277 const ARMSubtarget &STI) {
1278 while (MBBI != MBB.end() &&
1279 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1282 unsigned Category = 0;
1283 switch (MBBI->getOperand(0).getReg()) {
1284 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1288 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1289 Category = STI.isTargetDarwin() ? 2 : 1;
1291 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1292 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1299 if (Done || Category != Area)
1307 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1308 MachineBasicBlock &MBB = MF.front();
1309 MachineBasicBlock::iterator MBBI = MBB.begin();
1310 MachineFrameInfo *MFI = MF.getFrameInfo();
1311 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1312 bool isThumb = AFI->isThumbFunction();
1313 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1314 unsigned NumBytes = MFI->getStackSize();
1315 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1318 // Check if R3 is live in. It might have to be used as a scratch register.
1319 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1321 if ((*I).first == ARM::R3) {
1322 AFI->setR3IsLiveIn(true);
1327 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1328 NumBytes = (NumBytes + 3) & ~3;
1329 MFI->setStackSize(NumBytes);
1332 // Determine the sizes of each callee-save spill areas and record which frame
1333 // belongs to which callee-save spill areas.
1334 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1335 int FramePtrSpillFI = 0;
1338 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1340 if (!AFI->hasStackFrame()) {
1342 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1346 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1347 unsigned Reg = CSI[i].getReg();
1348 int FI = CSI[i].getFrameIdx();
1355 if (Reg == FramePtr)
1356 FramePtrSpillFI = FI;
1357 AFI->addGPRCalleeSavedArea1Frame(FI);
1364 if (Reg == FramePtr)
1365 FramePtrSpillFI = FI;
1366 if (STI.isTargetDarwin()) {
1367 AFI->addGPRCalleeSavedArea2Frame(FI);
1370 AFI->addGPRCalleeSavedArea1Frame(FI);
1375 AFI->addDPRCalleeSavedAreaFrame(FI);
1381 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1382 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
1383 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1384 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1387 // Darwin ABI requires FP to point to the stack slot that contains the
1389 if (STI.isTargetDarwin() || hasFP(MF)) {
1390 MachineInstrBuilder MIB =
1391 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1392 .addFrameIndex(FramePtrSpillFI).addImm(0);
1393 if (!isThumb) MIB.addImm(ARMCC::AL).addReg(0).addReg(0);
1397 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1398 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
1400 // Build the new SUBri to adjust SP for FP callee-save spill area.
1401 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1402 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
1405 // Determine starting offsets of spill areas.
1406 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1407 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1408 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1409 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1410 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1411 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1412 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1414 NumBytes = DPRCSOffset;
1416 // Insert it after all the callee-save spills.
1418 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1419 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1422 if(STI.isTargetELF() && hasFP(MF)) {
1423 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1424 AFI->getFramePtrSpillOffset());
1427 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1428 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1429 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1432 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1433 for (unsigned i = 0; CSRegs[i]; ++i)
1434 if (Reg == CSRegs[i])
1439 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1440 return ((MI->getOpcode() == ARM::FLDD ||
1441 MI->getOpcode() == ARM::LDR ||
1442 MI->getOpcode() == ARM::tRestore) &&
1443 MI->getOperand(1).isFrameIndex() &&
1444 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1447 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1448 MachineBasicBlock &MBB) const {
1449 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1450 assert((MBBI->getOpcode() == ARM::BX_RET ||
1451 MBBI->getOpcode() == ARM::tBX_RET ||
1452 MBBI->getOpcode() == ARM::tPOP_RET) &&
1453 "Can only insert epilog into returning blocks");
1455 MachineFrameInfo *MFI = MF.getFrameInfo();
1456 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1457 bool isThumb = AFI->isThumbFunction();
1458 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1459 int NumBytes = (int)MFI->getStackSize();
1460 if (!AFI->hasStackFrame()) {
1462 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1464 // Unwind MBBI to point to first LDR / FLDD.
1465 const unsigned *CSRegs = getCalleeSavedRegs();
1466 if (MBBI != MBB.begin()) {
1469 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1470 if (!isCSRestore(MBBI, CSRegs))
1474 // Move SP to start of FP callee save spill area.
1475 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1476 AFI->getGPRCalleeSavedArea2Size() +
1477 AFI->getDPRCalleeSavedAreaSize());
1480 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1481 // Reset SP based on frame pointer only if the stack frame extends beyond
1482 // frame pointer stack slot or target is ELF and the function has FP.
1484 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1486 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1488 if (MBBI->getOpcode() == ARM::tBX_RET &&
1489 &MBB.front() != MBBI &&
1490 prior(MBBI)->getOpcode() == ARM::tPOP) {
1491 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1492 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1494 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1497 // Darwin ABI requires FP to point to the stack slot that contains the
1499 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1500 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1501 // Reset SP based on frame pointer only if the stack frame extends beyond
1502 // frame pointer stack slot or target is ELF and the function has FP.
1503 if (AFI->getGPRCalleeSavedArea2Size() ||
1504 AFI->getDPRCalleeSavedAreaSize() ||
1505 AFI->getDPRCalleeSavedAreaOffset()||
1508 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1510 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1512 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1513 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1514 } else if (NumBytes) {
1515 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
1518 // Move SP to start of integer callee save spill area 2.
1519 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1520 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1523 // Move SP to start of integer callee save spill area 1.
1524 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1525 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1528 // Move SP to SP upon entry to the function.
1529 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1530 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1535 if (VARegSaveSize) {
1537 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1538 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1539 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1541 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1544 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1550 unsigned ARMRegisterInfo::getRARegister() const {
1554 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1555 if (STI.isTargetDarwin() || hasFP(MF))
1556 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1561 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1562 assert(0 && "What is the exception register");
1566 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1567 assert(0 && "What is the exception handler register");
1571 #include "ARMGenRegisterInfo.inc"