1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMRegisterInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/STLExtras.h"
26 ARMRegisterInfo::ARMRegisterInfo()
27 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
30 void ARMRegisterInfo::
31 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
32 unsigned SrcReg, int FI,
33 const TargetRegisterClass *RC) const {
34 assert (RC == ARM::IntRegsRegisterClass);
35 BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
38 void ARMRegisterInfo::
39 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
40 unsigned DestReg, int FI,
41 const TargetRegisterClass *RC) const {
42 assert (RC == ARM::IntRegsRegisterClass);
43 BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
46 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I,
48 unsigned DestReg, unsigned SrcReg,
49 const TargetRegisterClass *RC) const {
50 assert (RC == ARM::IntRegsRegisterClass);
51 BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
52 .addImm(ARMShift::LSL);
55 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
61 const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
62 static const unsigned CalleeSaveRegs[] = {
63 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
64 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
67 return CalleeSaveRegs;
70 const TargetRegisterClass* const *
71 ARMRegisterInfo::getCalleeSaveRegClasses() const {
72 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
73 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
74 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
75 &ARM::IntRegsRegClass, 0
77 return CalleeSaveRegClasses;
80 void ARMRegisterInfo::
81 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I) const {
87 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
88 MachineInstr &MI = *II;
89 MachineBasicBlock &MBB = *MI.getParent();
90 MachineFunction &MF = *MBB.getParent();
92 assert (MI.getOpcode() == ARM::ldr ||
93 MI.getOpcode() == ARM::str ||
94 MI.getOpcode() == ARM::lea_addri);
96 unsigned FrameIdx = 2;
99 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
102 assert (MI.getOperand(OffIdx).getImmedValue() == 0);
104 unsigned StackSize = MF.getFrameInfo()->getStackSize();
108 assert (Offset >= 0);
110 // Replace the FrameIndex with r13
111 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
112 // Replace the ldr offset with Offset
113 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
115 // Insert a set of r12 with the full address
116 // r12 = r13 + offset
117 MachineBasicBlock *MBB2 = MI.getParent();
118 BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
119 .addImm(0).addImm(ARMShift::LSL);
121 // Replace the FrameIndex with r12
122 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
126 void ARMRegisterInfo::
127 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
129 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
130 MachineBasicBlock &MBB = MF.front();
131 MachineBasicBlock::iterator MBBI = MBB.begin();
132 MachineFrameInfo *MFI = MF.getFrameInfo();
133 int NumBytes = (int) MFI->getStackSize();
135 if (MFI->hasCalls()) {
136 // We reserve argument space for call sites in the function immediately on
137 // entry to the current function. This eliminates the need for add/sub
138 // brackets around call sites.
139 NumBytes += MFI->getMaxCallFrameSize();
142 MFI->setStackSize(NumBytes);
144 //sub sp, sp, #NumBytes
145 BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
146 .addImm(0).addImm(ARMShift::LSL);
149 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
150 MachineBasicBlock &MBB) const {
151 MachineBasicBlock::iterator MBBI = prior(MBB.end());
152 assert(MBBI->getOpcode() == ARM::bx &&
153 "Can only insert epilog into returning blocks");
155 MachineFrameInfo *MFI = MF.getFrameInfo();
156 int NumBytes = (int) MFI->getStackSize();
158 //add sp, sp, #NumBytes
159 BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
160 .addImm(0).addImm(ARMShift::LSL);
163 unsigned ARMRegisterInfo::getRARegister() const {
167 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
171 #include "ARMGenRegisterInfo.inc"