1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
37 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
40 case R0: case S0: case D0: return 0;
41 case R1: case S1: case D1: return 1;
42 case R2: case S2: case D2: return 2;
43 case R3: case S3: case D3: return 3;
44 case R4: case S4: case D4: return 4;
45 case R5: case S5: case D5: return 5;
46 case R6: case S6: case D6: return 6;
47 case R7: case S7: case D7: return 7;
48 case R8: case S8: case D8: return 8;
49 case R9: case S9: case D9: return 9;
50 case R10: case S10: case D10: return 10;
51 case R11: case S11: case D11: return 11;
52 case R12: case S12: case D12: return 12;
53 case SP: case S13: case D13: return 13;
54 case LR: case S14: case D14: return 14;
55 case PC: case S15: case D15: return 15;
73 assert(0 && "Unknown ARM register!");
78 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
79 const ARMSubtarget &sti)
80 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
82 FramePtr(STI.useThumbBacktraces() ? ARM::R7 : ARM::R11) {
85 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MI,
87 const std::vector<CalleeSavedInfo> &CSI) const {
88 MachineFunction &MF = *MBB.getParent();
89 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
90 if (!AFI->isThumbFunction() || CSI.empty())
93 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
94 for (unsigned i = CSI.size(); i != 0; --i)
95 MIB.addReg(CSI[i-1].getReg());
99 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 const std::vector<CalleeSavedInfo> &CSI) const {
102 MachineFunction &MF = *MBB.getParent();
103 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
104 if (!AFI->isThumbFunction() || CSI.empty())
107 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
108 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
109 MBB.insert(MI, PopMI);
110 for (unsigned i = CSI.size(); i != 0; --i) {
111 unsigned Reg = CSI[i-1].getReg();
112 if (Reg == ARM::LR) {
113 // Special epilogue for vararg functions. See emitEpilogue
117 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
120 PopMI->addRegOperand(Reg, true);
125 void ARMRegisterInfo::
126 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
127 unsigned SrcReg, int FI,
128 const TargetRegisterClass *RC) const {
129 if (RC == ARM::GPRRegisterClass) {
130 MachineFunction &MF = *MBB.getParent();
131 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
132 if (AFI->isThumbFunction())
133 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
134 .addFrameIndex(FI).addImm(0);
136 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
137 .addFrameIndex(FI).addReg(0).addImm(0);
138 } else if (RC == ARM::DPRRegisterClass) {
139 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
140 .addFrameIndex(FI).addImm(0);
142 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
143 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
144 .addFrameIndex(FI).addImm(0);
148 void ARMRegisterInfo::
149 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
150 unsigned DestReg, int FI,
151 const TargetRegisterClass *RC) const {
152 if (RC == ARM::GPRRegisterClass) {
153 MachineFunction &MF = *MBB.getParent();
154 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
155 if (AFI->isThumbFunction())
156 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
157 .addFrameIndex(FI).addImm(0);
159 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
160 .addFrameIndex(FI).addReg(0).addImm(0);
161 } else if (RC == ARM::DPRRegisterClass) {
162 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
163 .addFrameIndex(FI).addImm(0);
165 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
166 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
167 .addFrameIndex(FI).addImm(0);
171 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator I,
173 unsigned DestReg, unsigned SrcReg,
174 const TargetRegisterClass *RC) const {
175 if (RC == ARM::GPRRegisterClass) {
176 MachineFunction &MF = *MBB.getParent();
177 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
178 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr),
179 DestReg).addReg(SrcReg);
180 } else if (RC == ARM::SPRRegisterClass)
181 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
182 else if (RC == ARM::DPRRegisterClass)
183 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
188 /// isLowRegister - Returns true if the register is low register r0-r7.
190 static bool isLowRegister(unsigned Reg) {
193 case R0: case R1: case R2: case R3:
194 case R4: case R5: case R6: case R7:
201 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
202 unsigned OpNum, int FI) const {
203 unsigned Opc = MI->getOpcode();
204 MachineInstr *NewMI = NULL;
208 if (OpNum == 0) { // move -> store
209 unsigned SrcReg = MI->getOperand(1).getReg();
210 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
211 .addReg(0).addImm(0);
212 } else { // move -> load
213 unsigned DstReg = MI->getOperand(0).getReg();
214 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
220 if (OpNum == 0) { // move -> store
221 unsigned SrcReg = MI->getOperand(1).getReg();
222 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
223 // tSpill cannot take a high register operand.
225 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
227 } else { // move -> load
228 unsigned DstReg = MI->getOperand(0).getReg();
229 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
230 // tRestore cannot target a high register operand.
232 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
238 if (OpNum == 0) { // move -> store
239 unsigned SrcReg = MI->getOperand(1).getReg();
240 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
242 } else { // move -> load
243 unsigned DstReg = MI->getOperand(0).getReg();
244 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
249 if (OpNum == 0) { // move -> store
250 unsigned SrcReg = MI->getOperand(1).getReg();
251 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
253 } else { // move -> load
254 unsigned DstReg = MI->getOperand(0).getReg();
255 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
262 NewMI->copyKillDeadInfo(MI);
266 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
267 static const unsigned CalleeSavedRegs[] = {
268 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
269 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
271 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
272 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
276 static const unsigned DarwinCalleeSavedRegs[] = {
277 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
278 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
280 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
281 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
284 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
287 const TargetRegisterClass* const *
288 ARMRegisterInfo::getCalleeSavedRegClasses() const {
289 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
290 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
291 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
292 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
294 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
295 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
298 return CalleeSavedRegClasses;
301 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
302 BitVector Reserved(getNumRegs());
303 Reserved.set(ARM::SP);
304 if (STI.isTargetDarwin() || hasFP(MF))
305 Reserved.set(FramePtr);
306 // Some targets reserve R9.
307 if (STI.isR9Reserved())
308 Reserved.set(ARM::R9);
309 // At PEI time, if LR is used, it will be spilled upon entry.
310 if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
311 Reserved.set(ARM::LR);
315 /// hasFP - Return true if the specified function should have a dedicated frame
316 /// pointer register. This is true if the function has variable sized allocas
317 /// or if frame pointer elimination is disabled.
319 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
320 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
323 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
324 /// a destreg = basereg + immediate in ARM code.
326 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator &MBBI,
328 unsigned DestReg, unsigned BaseReg,
329 int NumBytes, const TargetInstrInfo &TII) {
330 bool isSub = NumBytes < 0;
331 if (isSub) NumBytes = -NumBytes;
334 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
335 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
336 assert(ThisVal && "Didn't extract field correctly");
338 // We will handle these bits from offset, clear them.
339 NumBytes &= ~ThisVal;
341 // Get the properly encoded SOImmVal field.
342 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
343 assert(SOImmVal != -1 && "Bit extraction didn't work?");
345 // Build the new ADD / SUB.
346 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
347 .addReg(BaseReg).addImm(SOImmVal);
352 /// calcNumMI - Returns the number of instructions required to materialize
353 /// the specific add / sub r, c instruction.
354 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
355 unsigned NumBits, unsigned Scale) {
357 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
359 if (Opc == ARM::tADDrSPi) {
360 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
365 Chunk = ((1 << NumBits) - 1) * Scale;
368 NumMIs += Bytes / Chunk;
369 if ((Bytes % Chunk) != 0)
376 /// emitLoadConstPool - Emits a load from constpool to materialize NumBytes
378 static void emitLoadConstPool(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator &MBBI,
380 unsigned DestReg, int NumBytes,
381 const TargetInstrInfo &TII) {
382 MachineFunction &MF = *MBB.getParent();
383 MachineConstantPool *ConstantPool = MF.getConstantPool();
384 Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes);
385 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
386 BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
389 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
390 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
391 /// in a register using mov / mvn sequences or load the immediate from a
394 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
395 MachineBasicBlock::iterator &MBBI,
396 unsigned DestReg, unsigned BaseReg,
397 int NumBytes, bool CanChangeCC,
398 const TargetInstrInfo &TII) {
399 bool isHigh = !isLowRegister(DestReg) ||
400 (BaseReg != 0 && !isLowRegister(BaseReg));
402 // Subtract doesn't have high register version. Load the negative value
403 // if either base or dest register is a high register. Also, if do not
404 // issue sub as part of the sequence if condition register is to be
406 if (NumBytes < 0 && !isHigh && CanChangeCC) {
408 NumBytes = -NumBytes;
410 unsigned LdReg = DestReg;
411 if (DestReg == ARM::SP) {
412 assert(BaseReg == ARM::SP && "Unexpected!");
414 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
417 if (NumBytes <= 255 && NumBytes >= 0)
418 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
419 else if (NumBytes < 0 && NumBytes >= -255) {
420 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
421 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg).addReg(LdReg);
423 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII);
426 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
427 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
428 if (DestReg == ARM::SP)
429 MIB.addReg(BaseReg).addReg(LdReg);
431 MIB.addReg(BaseReg).addReg(LdReg);
433 MIB.addReg(LdReg).addReg(BaseReg);
434 if (DestReg == ARM::SP)
435 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
438 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
439 /// a destreg = basereg + immediate in Thumb code.
441 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
442 MachineBasicBlock::iterator &MBBI,
443 unsigned DestReg, unsigned BaseReg,
444 int NumBytes, const TargetInstrInfo &TII) {
445 bool isSub = NumBytes < 0;
446 unsigned Bytes = (unsigned)NumBytes;
447 if (isSub) Bytes = -NumBytes;
448 bool isMul4 = (Bytes & 3) == 0;
449 bool isTwoAddr = false;
450 bool DstNotEqBase = false;
451 unsigned NumBits = 1;
456 if (DestReg == BaseReg && BaseReg == ARM::SP) {
457 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
460 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
462 } else if (!isSub && BaseReg == ARM::SP) {
465 // r1 = add sp, 100 * 4
469 ExtraOpc = ARM::tADDi3;
478 if (DestReg != BaseReg)
481 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
485 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
486 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
487 if (NumMIs > Threshold) {
488 // This will expand into too many instructions. Load the immediate from a
490 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
495 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
496 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
497 unsigned Chunk = (1 << 3) - 1;
498 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
500 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
501 .addReg(BaseReg).addImm(ThisVal);
503 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg).addReg(BaseReg);
508 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
510 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
513 // Build the new tADD / tSUB.
515 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
517 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
520 if (Opc == ARM::tADDrSPi) {
526 Chunk = ((1 << NumBits) - 1) * Scale;
527 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
534 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg).addReg(DestReg)
535 .addImm(((unsigned)NumBytes) & 3);
539 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
540 int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
542 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
544 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
547 void ARMRegisterInfo::
548 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
549 MachineBasicBlock::iterator I) const {
551 // If we have alloca, convert as follows:
552 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
553 // ADJCALLSTACKUP -> add, sp, sp, amount
554 MachineInstr *Old = I;
555 unsigned Amount = Old->getOperand(0).getImmedValue();
557 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
558 // We need to keep the stack aligned properly. To do this, we round the
559 // amount of space needed for the outgoing arguments up to the next
560 // alignment boundary.
561 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
562 Amount = (Amount+Align-1)/Align*Align;
564 // Replace the pseudo instruction with a new instruction...
565 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
566 emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
568 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
569 emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
576 /// emitThumbConstant - Emit a series of instructions to materialize a
578 static void emitThumbConstant(MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator &MBBI,
580 unsigned DestReg, int Imm,
581 const TargetInstrInfo &TII) {
582 bool isSub = Imm < 0;
583 if (isSub) Imm = -Imm;
585 int Chunk = (1 << 8) - 1;
586 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
588 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal);
590 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
592 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg).addReg(DestReg);
595 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
597 MachineInstr &MI = *II;
598 MachineBasicBlock &MBB = *MI.getParent();
599 MachineFunction &MF = *MBB.getParent();
600 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
601 bool isThumb = AFI->isThumbFunction();
603 while (!MI.getOperand(i).isFrameIndex()) {
605 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
608 unsigned FrameReg = ARM::SP;
609 int FrameIndex = MI.getOperand(i).getFrameIndex();
610 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
611 MF.getFrameInfo()->getStackSize();
613 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
614 Offset -= AFI->getGPRCalleeSavedArea1Offset();
615 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
616 Offset -= AFI->getGPRCalleeSavedArea2Offset();
617 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
618 Offset -= AFI->getDPRCalleeSavedAreaOffset();
619 else if (hasFP(MF)) {
620 // There is alloca()'s in this function, must reference off the frame
622 FrameReg = getFrameRegister(MF);
623 Offset -= AFI->getFramePtrSpillOffset();
626 unsigned Opcode = MI.getOpcode();
627 const TargetInstrDescriptor &Desc = TII.get(Opcode);
628 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
631 if (Opcode == ARM::ADDri) {
632 Offset += MI.getOperand(i+1).getImm();
634 // Turn it into a move.
635 MI.setInstrDescriptor(TII.get(ARM::MOVrr));
636 MI.getOperand(i).ChangeToRegister(FrameReg, false);
637 MI.RemoveOperand(i+1);
639 } else if (Offset < 0) {
642 MI.setInstrDescriptor(TII.get(ARM::SUBri));
645 // Common case: small offset, fits into instruction.
646 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
647 if (ImmedOffset != -1) {
648 // Replace the FrameIndex with sp / fp
649 MI.getOperand(i).ChangeToRegister(FrameReg, false);
650 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
654 // Otherwise, we fallback to common code below to form the imm offset with
655 // a sequence of ADDri instructions. First though, pull as much of the imm
656 // into this ADDri as possible.
657 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
658 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, (32-RotAmt) & 31);
660 // We will handle these bits from offset, clear them.
661 Offset &= ~ThisImmVal;
663 // Get the properly encoded SOImmVal field.
664 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
665 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
666 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
667 } else if (Opcode == ARM::tADDrSPi) {
668 Offset += MI.getOperand(i+1).getImm();
669 assert((Offset & 3) == 0 &&
670 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
672 // Turn it into a move.
673 MI.setInstrDescriptor(TII.get(ARM::tMOVrr));
674 MI.getOperand(i).ChangeToRegister(FrameReg, false);
675 MI.RemoveOperand(i+1);
679 // Common case: small offset, fits into instruction.
680 if (((Offset >> 2) & ~255U) == 0) {
681 // Replace the FrameIndex with sp / fp
682 MI.getOperand(i).ChangeToRegister(FrameReg, false);
683 MI.getOperand(i+1).ChangeToImmediate(Offset >> 2);
687 unsigned DestReg = MI.getOperand(0).getReg();
688 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
689 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, 8, 1);
690 // MI would expand into a large number of instructions. Don't try to
691 // simplify the immediate.
693 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
699 // Translate r0 = add sp, imm to
700 // r0 = add sp, 255*4
701 // r0 = add r0, (imm - 255*4)
702 MI.getOperand(i).ChangeToRegister(FrameReg, false);
703 MI.getOperand(i+1).ChangeToImmediate(255);
704 Offset = (Offset - 255 * 4);
705 MachineBasicBlock::iterator NII = next(II);
706 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
708 // Translate r0 = add sp, -imm to
709 // r0 = -imm (this is then translated into a series of instructons)
711 emitThumbConstant(MBB, II, DestReg, Offset, TII);
712 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
713 MI.getOperand(i).ChangeToRegister(DestReg, false);
714 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
720 unsigned NumBits = 0;
723 case ARMII::AddrMode2: {
725 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
726 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
731 case ARMII::AddrMode3: {
733 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
734 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
739 case ARMII::AddrMode5: {
741 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
742 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
748 case ARMII::AddrModeTs: {
750 InstrOffs = MI.getOperand(ImmIdx).getImm();
751 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
756 assert(0 && "Unsupported addressing mode!");
761 Offset += InstrOffs * Scale;
762 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
763 if (Offset < 0 && !isThumb) {
768 // Common case: small offset, fits into instruction.
769 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
770 int ImmedOffset = Offset / Scale;
771 unsigned Mask = (1 << NumBits) - 1;
772 if ((unsigned)Offset <= Mask * Scale) {
773 // Replace the FrameIndex with sp
774 MI.getOperand(i).ChangeToRegister(FrameReg, false);
776 ImmedOffset |= 1 << NumBits;
777 ImmOp.ChangeToImmediate(ImmedOffset);
781 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
782 if (AddrMode == ARMII::AddrModeTs) {
783 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
784 // a different base register.
786 Mask = (1 << NumBits) - 1;
788 // If this is a thumb spill / restore, we will be using a constpool load to
789 // materialize the offset.
790 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
791 ImmOp.ChangeToImmediate(0);
793 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
794 ImmedOffset = ImmedOffset & Mask;
796 ImmedOffset |= 1 << NumBits;
797 ImmOp.ChangeToImmediate(ImmedOffset);
798 Offset &= ~(Mask*Scale);
802 // If we get here, the immediate doesn't fit into the instruction. We folded
803 // as much as possible above, handle the rest, providing a register that is
805 assert(Offset && "This code isn't needed if offset already handled!");
808 if (TII.isLoad(Opcode)) {
809 // Use the destination register to materialize sp + offset.
810 unsigned TmpReg = MI.getOperand(0).getReg();
812 if (Opcode == ARM::tRestore) {
813 if (FrameReg == ARM::SP)
814 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
816 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
820 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
821 MI.setInstrDescriptor(TII.get(ARM::tLDR));
822 MI.getOperand(i).ChangeToRegister(TmpReg, false);
824 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
826 MI.addRegOperand(0, false); // tLDR has an extra register operand.
827 } else if (TII.isStore(Opcode)) {
828 // FIXME! This is horrific!!! We need register scavenging.
829 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
830 // also a ABI register so it's possible that is is the register that is
831 // being storing here. If that's the case, we do the following:
833 // Use r2 to materialize sp + offset
836 unsigned ValReg = MI.getOperand(0).getReg();
837 unsigned TmpReg = ARM::R3;
839 if (ValReg == ARM::R3) {
840 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
843 if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn())
844 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
845 if (Opcode == ARM::tSpill) {
846 if (FrameReg == ARM::SP)
847 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
849 emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
853 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
854 MI.setInstrDescriptor(TII.get(ARM::tSTR));
855 MI.getOperand(i).ChangeToRegister(TmpReg, false);
857 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
859 MI.addRegOperand(0, false); // tSTR has an extra register operand.
861 MachineBasicBlock::iterator NII = next(II);
862 if (ValReg == ARM::R3)
863 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2).addReg(ARM::R12);
864 if (TmpReg == ARM::R3 && AFI->isR3IsLiveIn())
865 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3).addReg(ARM::R12);
867 assert(false && "Unexpected opcode!");
869 // Insert a set of r12 with the full address: r12 = sp + offset
870 // If the offset we have is too large to fit into the instruction, we need
871 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
873 emitARMRegPlusImmediate(MBB, II, ARM::R12, FrameReg,
874 isSub ? -Offset : Offset, TII);
875 MI.getOperand(i).ChangeToRegister(ARM::R12, false);
879 void ARMRegisterInfo::
880 processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
881 // This tells PEI to spill the FP as if it is any other callee-save register
882 // to take advantage the eliminateFrameIndex machinery. This also ensures it
883 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
884 // to combine multiple loads / stores.
885 bool CanEliminateFrame = true;
886 bool CS1Spilled = false;
887 bool LRSpilled = false;
888 unsigned NumGPRSpills = 0;
889 SmallVector<unsigned, 4> UnspilledCS1GPRs;
890 SmallVector<unsigned, 4> UnspilledCS2GPRs;
892 // Don't spill FP if the frame can be eliminated. This is determined
893 // by scanning the callee-save registers to see if any is used.
894 const unsigned *CSRegs = getCalleeSavedRegs();
895 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
896 for (unsigned i = 0; CSRegs[i]; ++i) {
897 unsigned Reg = CSRegs[i];
898 bool Spilled = false;
899 if (MF.isPhysRegUsed(Reg)) {
901 CanEliminateFrame = false;
903 // Check alias registers too.
904 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
905 if (MF.isPhysRegUsed(*Aliases)) {
907 CanEliminateFrame = false;
912 if (CSRegClasses[i] == &ARM::GPRRegClass) {
916 if (!STI.isTargetDarwin()) {
924 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
939 if (!STI.isTargetDarwin()) {
940 UnspilledCS1GPRs.push_back(Reg);
950 UnspilledCS1GPRs.push_back(Reg);
953 UnspilledCS2GPRs.push_back(Reg);
960 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
961 bool ForceLRSpill = false;
962 if (!LRSpilled && AFI->isThumbFunction()) {
963 unsigned FnSize = ARM::GetFunctionSize(MF);
964 // Force LR spill if the Thumb function size is > 2048. This enables the
965 // use of BL to implement far jump. If it turns out that it's not needed
966 // the branch fix up path will undo it.
967 if (FnSize >= (1 << 11)) {
968 CanEliminateFrame = false;
973 if (!CanEliminateFrame || hasFP(MF)) {
974 AFI->setHasStackFrame(true);
976 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
977 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
978 if (!LRSpilled && CS1Spilled) {
979 MF.changePhyRegUsed(ARM::LR, true);
981 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
982 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
983 ForceLRSpill = false;
986 // Darwin ABI requires FP to point to the stack slot that contains the
988 if (STI.isTargetDarwin() || hasFP(MF)) {
989 MF.changePhyRegUsed(FramePtr, true);
993 // If stack and double are 8-byte aligned and we are spilling an odd number
994 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
995 // the integer and double callee save areas.
996 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
997 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
998 if (CS1Spilled && !UnspilledCS1GPRs.empty())
999 MF.changePhyRegUsed(UnspilledCS1GPRs.front(), true);
1000 else if (!UnspilledCS2GPRs.empty())
1001 MF.changePhyRegUsed(UnspilledCS2GPRs.front(), true);
1006 MF.changePhyRegUsed(ARM::LR, true);
1007 AFI->setLRIsForceSpilled(true);
1011 /// Move iterator pass the next bunch of callee save load / store ops for
1012 /// the particular spill area (1: integer area 1, 2: integer area 2,
1013 /// 3: fp area, 0: don't care).
1014 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1015 MachineBasicBlock::iterator &MBBI,
1016 int Opc, unsigned Area,
1017 const ARMSubtarget &STI) {
1018 while (MBBI != MBB.end() &&
1019 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1022 unsigned Category = 0;
1023 switch (MBBI->getOperand(0).getReg()) {
1024 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1028 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1029 Category = STI.isTargetDarwin() ? 2 : 1;
1031 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1032 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1039 if (Done || Category != Area)
1047 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1048 MachineBasicBlock &MBB = MF.front();
1049 MachineBasicBlock::iterator MBBI = MBB.begin();
1050 MachineFrameInfo *MFI = MF.getFrameInfo();
1051 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1052 bool isThumb = AFI->isThumbFunction();
1053 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1054 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1055 unsigned NumBytes = MFI->getStackSize();
1056 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1059 // Check if R3 is live in. It might have to be used as a scratch register.
1060 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1062 if ((*I).first == ARM::R3) {
1063 AFI->setR3IsLiveIn(true);
1068 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1069 NumBytes = (NumBytes + 3) & ~3;
1070 MFI->setStackSize(NumBytes);
1073 // Determine the sizes of each callee-save spill areas and record which frame
1074 // belongs to which callee-save spill areas.
1075 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1076 int FramePtrSpillFI = 0;
1077 if (!AFI->hasStackFrame()) {
1079 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1084 emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
1086 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1087 unsigned Reg = CSI[i].getReg();
1088 int FI = CSI[i].getFrameIdx();
1095 if (Reg == FramePtr)
1096 FramePtrSpillFI = FI;
1097 AFI->addGPRCalleeSavedArea1Frame(FI);
1104 if (Reg == FramePtr)
1105 FramePtrSpillFI = FI;
1106 if (STI.isTargetDarwin()) {
1107 AFI->addGPRCalleeSavedArea2Frame(FI);
1110 AFI->addGPRCalleeSavedArea1Frame(FI);
1115 AFI->addDPRCalleeSavedAreaFrame(FI);
1120 if (Align == 8 && (GPRCS1Size & 7) != 0)
1121 // Pad CS1 to ensure proper alignment.
1125 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1126 emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
1127 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1128 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1131 // Darwin ABI requires FP to point to the stack slot that contains the
1133 if (STI.isTargetDarwin() || hasFP(MF))
1134 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
1135 .addFrameIndex(FramePtrSpillFI).addImm(0);
1138 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1139 emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
1141 // Build the new SUBri to adjust SP for FP callee-save spill area.
1142 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1143 emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
1146 // Determine starting offsets of spill areas.
1147 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1148 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1149 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1150 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1151 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1152 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1153 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1155 NumBytes = DPRCSOffset;
1157 // Insert it after all the callee-save spills.
1159 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1160 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1163 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1164 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1165 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1168 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1169 for (unsigned i = 0; CSRegs[i]; ++i)
1170 if (Reg == CSRegs[i])
1175 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1176 return ((MI->getOpcode() == ARM::FLDD ||
1177 MI->getOpcode() == ARM::LDR ||
1178 MI->getOpcode() == ARM::tRestore) &&
1179 MI->getOperand(1).isFrameIndex() &&
1180 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1183 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1184 MachineBasicBlock &MBB) const {
1185 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1186 assert((MBBI->getOpcode() == ARM::BX_RET ||
1187 MBBI->getOpcode() == ARM::tBX_RET ||
1188 MBBI->getOpcode() == ARM::tPOP_RET) &&
1189 "Can only insert epilog into returning blocks");
1191 MachineFrameInfo *MFI = MF.getFrameInfo();
1192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1193 bool isThumb = AFI->isThumbFunction();
1194 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1195 int NumBytes = (int)MFI->getStackSize();
1196 if (!AFI->hasStackFrame()) {
1198 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1202 // Unwind MBBI to point to first LDR / FLDD.
1203 const unsigned *CSRegs = getCalleeSavedRegs();
1204 if (MBBI != MBB.begin()) {
1207 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1208 if (!isCSRestore(MBBI, CSRegs))
1212 // Move SP to start of FP callee save spill area.
1213 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1214 AFI->getGPRCalleeSavedArea2Size() +
1215 AFI->getDPRCalleeSavedAreaSize());
1218 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1219 // Reset SP based on frame pointer only if the stack frame extends beyond
1220 // frame pointer stack slot or target is ELF and the function has FP.
1222 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1224 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr);
1226 if (MBBI->getOpcode() == ARM::tBX_RET &&
1227 &MBB.front() != MBBI &&
1228 prior(MBBI)->getOpcode() == ARM::tPOP) {
1229 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1230 emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
1232 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1235 // Darwin ABI requires FP to point to the stack slot that contains the
1237 if (STI.isTargetDarwin() || hasFP(MF)) {
1238 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1239 // Reset SP based on frame pointer only if the stack frame extends beyond
1240 // frame pointer stack slot or target is ELF and the function has FP.
1241 if (AFI->getGPRCalleeSavedArea2Size() ||
1242 AFI->getDPRCalleeSavedAreaSize() ||
1243 AFI->getDPRCalleeSavedAreaOffset()||
1246 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1249 BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr);
1250 } else if (NumBytes) {
1251 emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
1254 // Move SP to start of integer callee save spill area 2.
1255 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1256 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
1258 // Move SP to start of integer callee save spill area 1.
1259 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1260 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
1262 // Move SP to SP upon entry to the function.
1263 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1264 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
1267 if (VARegSaveSize) {
1269 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1270 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1271 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1273 emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
1276 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1282 unsigned ARMRegisterInfo::getRARegister() const {
1286 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1287 return STI.useThumbBacktraces() ? ARM::R7 : ARM::R11;
1290 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1291 assert(0 && "What is the exception register");
1295 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1296 assert(0 && "What is the exception handler register");
1300 #include "ARMGenRegisterInfo.inc"