1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMRegisterInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/STLExtras.h"
26 ARMRegisterInfo::ARMRegisterInfo()
27 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
30 void ARMRegisterInfo::
31 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
32 unsigned SrcReg, int FI,
33 const TargetRegisterClass *RC) const {
34 assert (RC == ARM::IntRegsRegisterClass);
35 BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
38 void ARMRegisterInfo::
39 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
40 unsigned DestReg, int FI,
41 const TargetRegisterClass *RC) const {
42 assert (RC == ARM::IntRegsRegisterClass);
43 BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
46 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I,
48 unsigned DestReg, unsigned SrcReg,
49 const TargetRegisterClass *RC) const {
50 assert (RC == ARM::IntRegsRegisterClass);
51 BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
54 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
60 const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
61 static const unsigned CalleeSaveRegs[] = {
62 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
63 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
66 return CalleeSaveRegs;
69 const TargetRegisterClass* const *
70 ARMRegisterInfo::getCalleeSaveRegClasses() const {
71 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
72 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
73 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
74 &ARM::IntRegsRegClass, 0
76 return CalleeSaveRegClasses;
79 void ARMRegisterInfo::
80 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I) const {
86 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
87 MachineInstr &MI = *II;
88 MachineBasicBlock &MBB = *MI.getParent();
89 MachineFunction &MF = *MBB.getParent();
91 assert (MI.getOpcode() == ARM::ldr ||
92 MI.getOpcode() == ARM::str);
94 unsigned FrameIdx = 2;
97 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
99 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
100 assert (MI.getOperand(OffIdx).getImmedValue() == 0);
102 unsigned StackSize = MF.getFrameInfo()->getStackSize();
106 assert (Offset >= 0);
108 // Replace the FrameIndex with r13
109 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
110 // Replace the ldr offset with Offset
111 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
113 // Insert a set of r12 with the full address
114 // r12 = r13 + offset
115 MachineBasicBlock *MBB2 = MI.getParent();
116 BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
118 // Replace the FrameIndex with r12
119 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
123 void ARMRegisterInfo::
124 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
126 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
127 MachineBasicBlock &MBB = MF.front();
128 MachineBasicBlock::iterator MBBI = MBB.begin();
129 MachineFrameInfo *MFI = MF.getFrameInfo();
130 int NumBytes = (int) MFI->getStackSize();
132 if (MFI->hasCalls()) {
133 // We reserve argument space for call sites in the function immediately on
134 // entry to the current function. This eliminates the need for add/sub
135 // brackets around call sites.
136 NumBytes += MFI->getMaxCallFrameSize();
139 MFI->setStackSize(NumBytes);
141 //sub sp, sp, #NumBytes
142 BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
145 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
146 MachineBasicBlock &MBB) const {
147 MachineBasicBlock::iterator MBBI = prior(MBB.end());
148 assert(MBBI->getOpcode() == ARM::bx &&
149 "Can only insert epilog into returning blocks");
151 MachineFrameInfo *MFI = MF.getFrameInfo();
152 int NumBytes = (int) MFI->getStackSize();
154 //add sp, sp, #NumBytes
155 BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
158 unsigned ARMRegisterInfo::getRARegister() const {
162 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
166 #include "ARMGenRegisterInfo.inc"