1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMRegisterInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/ADT/STLExtras.h"
29 // hasFP - Return true if the specified function should have a dedicated frame
30 // pointer register. This is true if the function has variable sized allocas or
31 // if frame pointer elimination is disabled.
33 static bool hasFP(const MachineFunction &MF) {
34 const MachineFrameInfo *MFI = MF.getFrameInfo();
35 return NoFramePointerElim || MFI->hasVarSizedObjects();
38 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
39 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
43 void ARMRegisterInfo::
44 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
45 unsigned SrcReg, int FI,
46 const TargetRegisterClass *RC) const {
47 assert (RC == ARM::IntRegsRegisterClass);
48 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
51 void ARMRegisterInfo::
52 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53 unsigned DestReg, int FI,
54 const TargetRegisterClass *RC) const {
55 assert (RC == ARM::IntRegsRegisterClass);
56 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
59 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I,
61 unsigned DestReg, unsigned SrcReg,
62 const TargetRegisterClass *RC) const {
63 assert(RC == ARM::IntRegsRegisterClass ||
64 RC == ARM::FPRegsRegisterClass ||
65 RC == ARM::DFPRegsRegisterClass);
67 if (RC == ARM::IntRegsRegisterClass)
68 BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
69 .addImm(ARMShift::LSL);
70 else if (RC == ARM::FPRegsRegisterClass)
71 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
73 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
76 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
82 const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
83 static const unsigned CalleeSaveRegs[] = {
84 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
85 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
88 return CalleeSaveRegs;
91 const TargetRegisterClass* const *
92 ARMRegisterInfo::getCalleeSaveRegClasses() const {
93 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
94 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
95 &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
96 &ARM::IntRegsRegClass, 0
98 return CalleeSaveRegClasses;
101 void ARMRegisterInfo::
102 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I) const {
105 MachineInstr *Old = I;
106 unsigned Amount = Old->getOperand(0).getImmedValue();
108 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
109 Amount = (Amount+Align-1)/Align*Align;
111 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
112 // sub sp, sp, amount
113 BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
114 .addImm(0).addImm(ARMShift::LSL);
116 // add sp, sp, amount
117 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
118 BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
119 .addImm(0).addImm(ARMShift::LSL);
127 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
128 MachineInstr &MI = *II;
129 MachineBasicBlock &MBB = *MI.getParent();
130 MachineFunction &MF = *MBB.getParent();
132 assert (MI.getOpcode() == ARM::LDR ||
133 MI.getOpcode() == ARM::STR ||
134 MI.getOpcode() == ARM::ADD);
136 unsigned FrameIdx = 1;
139 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
141 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
142 MI.getOperand(OffIdx).getImmedValue();
144 unsigned StackSize = MF.getFrameInfo()->getStackSize();
148 assert (Offset >= 0);
149 unsigned BaseRegister = hasFP(MF) ? ARM::R11 : ARM::R13;
151 // Replace the FrameIndex with r13
152 MI.getOperand(FrameIdx).ChangeToRegister(BaseRegister, false);
153 // Replace the ldr offset with Offset
154 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
156 // Insert a set of r12 with the full address
157 // r12 = r13 + offset
158 MachineBasicBlock *MBB2 = MI.getParent();
159 BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
160 .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
162 // Replace the FrameIndex with r12
163 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
167 void ARMRegisterInfo::
168 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
170 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
171 MachineBasicBlock &MBB = MF.front();
172 MachineBasicBlock::iterator MBBI = MBB.begin();
173 MachineFrameInfo *MFI = MF.getFrameInfo();
174 int NumBytes = (int) MFI->getStackSize();
176 bool HasFP = hasFP(MF);
178 if (MFI->hasCalls()) {
179 // We reserve argument space for call sites in the function immediately on
180 // entry to the current function. This eliminates the need for add/sub
181 // brackets around call sites.
182 NumBytes += MFI->getMaxCallFrameSize();
186 // Add space for storing the FP
190 NumBytes = ((NumBytes + 7) / 8) * 8;
192 MFI->setStackSize(NumBytes);
194 //sub sp, sp, #NumBytes
195 BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
196 .addImm(0).addImm(ARMShift::LSL);
199 BuildMI(MBB, MBBI, TII.get(ARM::STR))
200 .addReg(ARM::R11).addReg(ARM::R13).addImm(0);
201 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
202 addImm(ARMShift::LSL);
206 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
207 MachineBasicBlock &MBB) const {
208 MachineBasicBlock::iterator MBBI = prior(MBB.end());
209 assert(MBBI->getOpcode() == ARM::bx &&
210 "Can only insert epilog into returning blocks");
212 MachineFrameInfo *MFI = MF.getFrameInfo();
213 int NumBytes = (int) MFI->getStackSize();
216 BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
217 addImm(ARMShift::LSL);
218 BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
221 //add sp, sp, #NumBytes
222 BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
223 .addImm(0).addImm(ARMShift::LSL);
226 unsigned ARMRegisterInfo::getRARegister() const {
230 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
231 return hasFP(MF) ? ARM::R11 : ARM::R13;
234 #include "ARMGenRegisterInfo.inc"