1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMSubtarget.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLocation.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
136 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
137 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
141 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
142 return MIB.addReg(0);
145 /// emitLoadConstPool - Emits a load from constpool to materialize the
146 /// specified immediate.
147 static void emitLoadConstPool(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator &MBBI,
149 unsigned DestReg, int Val,
150 ARMCC::CondCodes Pred, unsigned PredReg,
151 const TargetInstrInfo &TII, bool isThumb) {
152 MachineFunction &MF = *MBB.getParent();
153 MachineConstantPool *ConstantPool = MF.getConstantPool();
154 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
155 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
157 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
159 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
160 .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
163 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator I,
166 const MachineInstr *Orig) const {
167 if (Orig->getOpcode() == ARM::MOVi2pieces) {
168 emitLoadConstPool(MBB, I, DestReg,
169 Orig->getOperand(1).getImm(),
170 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
171 Orig->getOperand(3).getReg(),
176 MachineInstr *MI = Orig->clone();
177 MI->getOperand(0).setReg(DestReg);
181 /// isLowRegister - Returns true if the register is low register r0-r7.
183 static bool isLowRegister(unsigned Reg) {
186 case R0: case R1: case R2: case R3:
187 case R4: case R5: case R6: case R7:
194 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
195 SmallVectorImpl<unsigned> &Ops,
197 if (Ops.size() != 1) return NULL;
199 unsigned OpNum = Ops[0];
200 unsigned Opc = MI->getOpcode();
201 MachineInstr *NewMI = NULL;
205 if (MI->getOperand(4).getReg() == ARM::CPSR)
206 // If it is updating CPSR, then it cannot be foled.
208 unsigned Pred = MI->getOperand(2).getImm();
209 unsigned PredReg = MI->getOperand(3).getReg();
210 if (OpNum == 0) { // move -> store
211 unsigned SrcReg = MI->getOperand(1).getReg();
212 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
213 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
214 } else { // move -> load
215 unsigned DstReg = MI->getOperand(0).getReg();
216 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
217 .addImm(0).addImm(Pred).addReg(PredReg);
222 if (OpNum == 0) { // move -> store
223 unsigned SrcReg = MI->getOperand(1).getReg();
224 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
225 // tSpill cannot take a high register operand.
227 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
229 } else { // move -> load
230 unsigned DstReg = MI->getOperand(0).getReg();
231 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
232 // tRestore cannot target a high register operand.
234 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
240 unsigned Pred = MI->getOperand(2).getImm();
241 unsigned PredReg = MI->getOperand(3).getReg();
242 if (OpNum == 0) { // move -> store
243 unsigned SrcReg = MI->getOperand(1).getReg();
244 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
245 .addImm(0).addImm(Pred).addReg(PredReg);
246 } else { // move -> load
247 unsigned DstReg = MI->getOperand(0).getReg();
248 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI)
249 .addImm(0).addImm(Pred).addReg(PredReg);
254 unsigned Pred = MI->getOperand(2).getImm();
255 unsigned PredReg = MI->getOperand(3).getReg();
256 if (OpNum == 0) { // move -> store
257 unsigned SrcReg = MI->getOperand(1).getReg();
258 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
259 .addImm(0).addImm(Pred).addReg(PredReg);
260 } else { // move -> load
261 unsigned DstReg = MI->getOperand(0).getReg();
262 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI)
263 .addImm(0).addImm(Pred).addReg(PredReg);
270 NewMI->copyKillDeadInfo(MI);
274 bool ARMRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
275 SmallVectorImpl<unsigned> &Ops) const {
276 if (Ops.size() != 1) return false;
278 unsigned OpNum = Ops[0];
279 unsigned Opc = MI->getOpcode();
283 // If it is updating CPSR, then it cannot be foled.
284 return MI->getOperand(4).getReg() != ARM::CPSR;
286 if (OpNum == 0) { // move -> store
287 unsigned SrcReg = MI->getOperand(1).getReg();
288 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
289 // tSpill cannot take a high register operand.
291 } else { // move -> load
292 unsigned DstReg = MI->getOperand(0).getReg();
293 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
294 // tRestore cannot target a high register operand.
308 ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
309 static const unsigned CalleeSavedRegs[] = {
310 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
311 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
313 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
314 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
318 static const unsigned DarwinCalleeSavedRegs[] = {
319 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
320 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
322 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
323 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
326 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
329 const TargetRegisterClass* const *
330 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
331 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
332 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
333 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
334 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
336 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
337 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
340 return CalleeSavedRegClasses;
343 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344 // FIXME: avoid re-calculating this everytime.
345 BitVector Reserved(getNumRegs());
346 Reserved.set(ARM::SP);
347 Reserved.set(ARM::PC);
348 if (STI.isTargetDarwin() || hasFP(MF))
349 Reserved.set(FramePtr);
350 // Some targets reserve R9.
351 if (STI.isR9Reserved())
352 Reserved.set(ARM::R9);
357 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
365 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
369 return STI.isR9Reserved();
376 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
377 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
378 return ThumbRegScavenging || !AFI->isThumbFunction();
381 /// hasFP - Return true if the specified function should have a dedicated frame
382 /// pointer register. This is true if the function has variable sized allocas
383 /// or if frame pointer elimination is disabled.
385 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
386 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
389 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
390 // not required, we reserve argument space for call sites in the function
391 // immediately on entry to the current function. This eliminates the need for
392 // add/sub sp brackets around call sites. Returns true if the call frame is
393 // included as part of the stack frame.
394 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
395 const MachineFrameInfo *FFI = MF.getFrameInfo();
396 unsigned CFSize = FFI->getMaxCallFrameSize();
397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
398 // It's not always a good idea to include the call frame as part of the
399 // stack frame. ARM (especially Thumb) has small immediate offset to
400 // address the stack frame. So a large call frame can cause poor codegen
401 // and may even makes it impossible to scavenge a register.
402 if (AFI->isThumbFunction()) {
403 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
406 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
409 return !MF.getFrameInfo()->hasVarSizedObjects();
412 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
413 /// a destreg = basereg + immediate in ARM code.
415 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator &MBBI,
417 unsigned DestReg, unsigned BaseReg, int NumBytes,
418 ARMCC::CondCodes Pred, unsigned PredReg,
419 const TargetInstrInfo &TII) {
420 bool isSub = NumBytes < 0;
421 if (isSub) NumBytes = -NumBytes;
424 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
425 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
426 assert(ThisVal && "Didn't extract field correctly");
428 // We will handle these bits from offset, clear them.
429 NumBytes &= ~ThisVal;
431 // Get the properly encoded SOImmVal field.
432 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
433 assert(SOImmVal != -1 && "Bit extraction didn't work?");
435 // Build the new ADD / SUB.
436 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
437 .addReg(BaseReg, false, false, true).addImm(SOImmVal)
438 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
443 /// calcNumMI - Returns the number of instructions required to materialize
444 /// the specific add / sub r, c instruction.
445 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
446 unsigned NumBits, unsigned Scale) {
448 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
450 if (Opc == ARM::tADDrSPi) {
451 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
455 Scale = 1; // Followed by a number of tADDi8.
456 Chunk = ((1 << NumBits) - 1) * Scale;
459 NumMIs += Bytes / Chunk;
460 if ((Bytes % Chunk) != 0)
467 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
468 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
469 /// in a register using mov / mvn sequences or load the immediate from a
472 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
473 MachineBasicBlock::iterator &MBBI,
474 unsigned DestReg, unsigned BaseReg,
475 int NumBytes, bool CanChangeCC,
476 const TargetInstrInfo &TII) {
477 bool isHigh = !isLowRegister(DestReg) ||
478 (BaseReg != 0 && !isLowRegister(BaseReg));
480 // Subtract doesn't have high register version. Load the negative value
481 // if either base or dest register is a high register. Also, if do not
482 // issue sub as part of the sequence if condition register is to be
484 if (NumBytes < 0 && !isHigh && CanChangeCC) {
486 NumBytes = -NumBytes;
488 unsigned LdReg = DestReg;
489 if (DestReg == ARM::SP) {
490 assert(BaseReg == ARM::SP && "Unexpected!");
492 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
493 .addReg(ARM::R3, false, false, true);
496 if (NumBytes <= 255 && NumBytes >= 0)
497 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
498 else if (NumBytes < 0 && NumBytes >= -255) {
499 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
500 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
501 .addReg(LdReg, false, false, true);
503 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
506 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
507 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
508 if (DestReg == ARM::SP || isSub)
509 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
511 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
512 if (DestReg == ARM::SP)
513 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
514 .addReg(ARM::R12, false, false, true);
517 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
518 /// a destreg = basereg + immediate in Thumb code.
520 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
521 MachineBasicBlock::iterator &MBBI,
522 unsigned DestReg, unsigned BaseReg,
523 int NumBytes, const TargetInstrInfo &TII) {
524 bool isSub = NumBytes < 0;
525 unsigned Bytes = (unsigned)NumBytes;
526 if (isSub) Bytes = -NumBytes;
527 bool isMul4 = (Bytes & 3) == 0;
528 bool isTwoAddr = false;
529 bool DstNotEqBase = false;
530 unsigned NumBits = 1;
535 if (DestReg == BaseReg && BaseReg == ARM::SP) {
536 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
539 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
541 } else if (!isSub && BaseReg == ARM::SP) {
544 // r1 = add sp, 100 * 4
548 ExtraOpc = ARM::tADDi3;
557 if (DestReg != BaseReg)
560 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
564 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
565 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
566 if (NumMIs > Threshold) {
567 // This will expand into too many instructions. Load the immediate from a
569 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
574 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
575 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
576 unsigned Chunk = (1 << 3) - 1;
577 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
579 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
580 .addReg(BaseReg, false, false, true).addImm(ThisVal);
582 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
583 .addReg(BaseReg, false, false, true);
588 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
590 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
593 // Build the new tADD / tSUB.
595 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
597 bool isKill = BaseReg != ARM::SP;
598 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
599 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
602 if (Opc == ARM::tADDrSPi) {
608 Chunk = ((1 << NumBits) - 1) * Scale;
609 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
616 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
617 .addReg(DestReg, false, false, true)
618 .addImm(((unsigned)NumBytes) & 3);
622 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
623 int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
624 bool isThumb, const TargetInstrInfo &TII) {
626 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
628 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
632 void ARMRegisterInfo::
633 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
634 MachineBasicBlock::iterator I) const {
635 if (!hasReservedCallFrame(MF)) {
636 // If we have alloca, convert as follows:
637 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
638 // ADJCALLSTACKUP -> add, sp, sp, amount
639 MachineInstr *Old = I;
640 unsigned Amount = Old->getOperand(0).getImm();
642 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
643 // We need to keep the stack aligned properly. To do this, we round the
644 // amount of space needed for the outgoing arguments up to the next
645 // alignment boundary.
646 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
647 Amount = (Amount+Align-1)/Align*Align;
649 // Replace the pseudo instruction with a new instruction...
650 unsigned Opc = Old->getOpcode();
651 bool isThumb = AFI->isThumbFunction();
652 ARMCC::CondCodes Pred = isThumb
653 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
654 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
655 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
656 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
657 emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
659 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
660 unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
661 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
662 emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
669 /// emitThumbConstant - Emit a series of instructions to materialize a
671 static void emitThumbConstant(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator &MBBI,
673 unsigned DestReg, int Imm,
674 const TargetInstrInfo &TII) {
675 bool isSub = Imm < 0;
676 if (isSub) Imm = -Imm;
678 int Chunk = (1 << 8) - 1;
679 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
681 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
683 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
685 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
686 .addReg(DestReg, false, false, true);
689 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
690 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
691 /// register first and then a spilled callee-saved register if that fails.
693 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
694 ARMFunctionInfo *AFI) {
695 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
697 // Try a already spilled CS register.
698 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
703 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
704 int SPAdj, RegScavenger *RS) const{
706 MachineInstr &MI = *II;
707 MachineBasicBlock &MBB = *MI.getParent();
708 MachineFunction &MF = *MBB.getParent();
709 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
710 bool isThumb = AFI->isThumbFunction();
712 while (!MI.getOperand(i).isFrameIndex()) {
714 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
717 unsigned FrameReg = ARM::SP;
718 int FrameIndex = MI.getOperand(i).getIndex();
719 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
720 MF.getFrameInfo()->getStackSize() + SPAdj;
722 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
723 Offset -= AFI->getGPRCalleeSavedArea1Offset();
724 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
725 Offset -= AFI->getGPRCalleeSavedArea2Offset();
726 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
727 Offset -= AFI->getDPRCalleeSavedAreaOffset();
728 else if (hasFP(MF)) {
729 assert(SPAdj == 0 && "Unexpected");
730 // There is alloca()'s in this function, must reference off the frame
732 FrameReg = getFrameRegister(MF);
733 Offset -= AFI->getFramePtrSpillOffset();
736 unsigned Opcode = MI.getOpcode();
737 const TargetInstrDescriptor &Desc = TII.get(Opcode);
738 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
741 if (Opcode == ARM::ADDri) {
742 Offset += MI.getOperand(i+1).getImm();
744 // Turn it into a move.
745 MI.setInstrDescriptor(TII.get(ARM::MOVr));
746 MI.getOperand(i).ChangeToRegister(FrameReg, false);
747 MI.RemoveOperand(i+1);
749 } else if (Offset < 0) {
752 MI.setInstrDescriptor(TII.get(ARM::SUBri));
755 // Common case: small offset, fits into instruction.
756 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
757 if (ImmedOffset != -1) {
758 // Replace the FrameIndex with sp / fp
759 MI.getOperand(i).ChangeToRegister(FrameReg, false);
760 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
764 // Otherwise, we fallback to common code below to form the imm offset with
765 // a sequence of ADDri instructions. First though, pull as much of the imm
766 // into this ADDri as possible.
767 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
768 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
770 // We will handle these bits from offset, clear them.
771 Offset &= ~ThisImmVal;
773 // Get the properly encoded SOImmVal field.
774 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
775 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
776 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
777 } else if (Opcode == ARM::tADDrSPi) {
778 Offset += MI.getOperand(i+1).getImm();
780 // Can't use tADDrSPi if it's based off the frame pointer.
781 unsigned NumBits = 0;
783 if (FrameReg != ARM::SP) {
784 Opcode = ARM::tADDi3;
785 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
790 assert((Offset & 3) == 0 &&
791 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
795 // Turn it into a move.
796 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
797 MI.getOperand(i).ChangeToRegister(FrameReg, false);
798 MI.RemoveOperand(i+1);
802 // Common case: small offset, fits into instruction.
803 unsigned Mask = (1 << NumBits) - 1;
804 if (((Offset / Scale) & ~Mask) == 0) {
805 // Replace the FrameIndex with sp / fp
806 MI.getOperand(i).ChangeToRegister(FrameReg, false);
807 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
811 unsigned DestReg = MI.getOperand(0).getReg();
812 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
813 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
814 // MI would expand into a large number of instructions. Don't try to
815 // simplify the immediate.
817 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
823 // Translate r0 = add sp, imm to
824 // r0 = add sp, 255*4
825 // r0 = add r0, (imm - 255*4)
826 MI.getOperand(i).ChangeToRegister(FrameReg, false);
827 MI.getOperand(i+1).ChangeToImmediate(Mask);
828 Offset = (Offset - Mask * Scale);
829 MachineBasicBlock::iterator NII = next(II);
830 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
832 // Translate r0 = add sp, -imm to
833 // r0 = -imm (this is then translated into a series of instructons)
835 emitThumbConstant(MBB, II, DestReg, Offset, TII);
836 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
837 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
838 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
844 unsigned NumBits = 0;
847 case ARMII::AddrMode2: {
849 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
850 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
855 case ARMII::AddrMode3: {
857 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
858 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
863 case ARMII::AddrMode5: {
865 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
866 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
872 case ARMII::AddrModeTs: {
874 InstrOffs = MI.getOperand(ImmIdx).getImm();
875 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
880 assert(0 && "Unsupported addressing mode!");
885 Offset += InstrOffs * Scale;
886 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
887 if (Offset < 0 && !isThumb) {
892 // Common case: small offset, fits into instruction.
893 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
894 int ImmedOffset = Offset / Scale;
895 unsigned Mask = (1 << NumBits) - 1;
896 if ((unsigned)Offset <= Mask * Scale) {
897 // Replace the FrameIndex with sp
898 MI.getOperand(i).ChangeToRegister(FrameReg, false);
900 ImmedOffset |= 1 << NumBits;
901 ImmOp.ChangeToImmediate(ImmedOffset);
905 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
906 if (AddrMode == ARMII::AddrModeTs) {
907 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
908 // a different base register.
910 Mask = (1 << NumBits) - 1;
912 // If this is a thumb spill / restore, we will be using a constpool load to
913 // materialize the offset.
914 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
915 ImmOp.ChangeToImmediate(0);
917 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
918 ImmedOffset = ImmedOffset & Mask;
920 ImmedOffset |= 1 << NumBits;
921 ImmOp.ChangeToImmediate(ImmedOffset);
922 Offset &= ~(Mask*Scale);
926 // If we get here, the immediate doesn't fit into the instruction. We folded
927 // as much as possible above, handle the rest, providing a register that is
929 assert(Offset && "This code isn't needed if offset already handled!");
932 if (TII.isLoad(Opcode)) {
933 // Use the destination register to materialize sp + offset.
934 unsigned TmpReg = MI.getOperand(0).getReg();
936 if (Opcode == ARM::tRestore) {
937 if (FrameReg == ARM::SP)
938 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
940 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
944 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
945 MI.setInstrDescriptor(TII.get(ARM::tLDR));
946 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
948 // Use [reg, reg] addrmode.
949 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
950 else // tLDR has an extra register operand.
951 MI.addOperand(MachineOperand::CreateReg(0, false));
952 } else if (TII.isStore(Opcode)) {
953 // FIXME! This is horrific!!! We need register scavenging.
954 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
955 // also a ABI register so it's possible that is is the register that is
956 // being storing here. If that's the case, we do the following:
958 // Use r2 to materialize sp + offset
961 unsigned ValReg = MI.getOperand(0).getReg();
962 unsigned TmpReg = ARM::R3;
964 if (ValReg == ARM::R3) {
965 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
966 .addReg(ARM::R2, false, false, true);
969 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
970 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
971 .addReg(ARM::R3, false, false, true);
972 if (Opcode == ARM::tSpill) {
973 if (FrameReg == ARM::SP)
974 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
976 emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
980 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
981 MI.setInstrDescriptor(TII.get(ARM::tSTR));
982 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
983 if (UseRR) // Use [reg, reg] addrmode.
984 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
985 else // tSTR has an extra register operand.
986 MI.addOperand(MachineOperand::CreateReg(0, false));
988 MachineBasicBlock::iterator NII = next(II);
989 if (ValReg == ARM::R3)
990 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
991 .addReg(ARM::R12, false, false, true);
992 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
993 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
994 .addReg(ARM::R12, false, false, true);
996 assert(false && "Unexpected opcode!");
998 // Insert a set of r12 with the full address: r12 = sp + offset
999 // If the offset we have is too large to fit into the instruction, we need
1000 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1002 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1003 if (ScratchReg == 0)
1004 // No register is "free". Scavenge a register.
1005 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1006 int PIdx = MI.findFirstPredOperandIdx();
1007 ARMCC::CondCodes Pred = (PIdx == -1)
1008 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1009 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1010 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1011 isSub ? -Offset : Offset, Pred, PredReg, TII);
1012 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1016 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1017 const MachineFrameInfo *FFI = MF.getFrameInfo();
1019 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1020 int FixedOff = -FFI->getObjectOffset(i);
1021 if (FixedOff > Offset) Offset = FixedOff;
1023 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1024 Offset += FFI->getObjectSize(i);
1025 unsigned Align = FFI->getObjectAlignment(i);
1026 // Adjust to alignment boundary
1027 Offset = (Offset+Align-1)/Align*Align;
1029 return (unsigned)Offset;
1033 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1034 RegScavenger *RS) const {
1035 // This tells PEI to spill the FP as if it is any other callee-save register
1036 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1037 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1038 // to combine multiple loads / stores.
1039 bool CanEliminateFrame = true;
1040 bool CS1Spilled = false;
1041 bool LRSpilled = false;
1042 unsigned NumGPRSpills = 0;
1043 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1044 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1045 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1047 // Don't spill FP if the frame can be eliminated. This is determined
1048 // by scanning the callee-save registers to see if any is used.
1049 const unsigned *CSRegs = getCalleeSavedRegs();
1050 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1051 for (unsigned i = 0; CSRegs[i]; ++i) {
1052 unsigned Reg = CSRegs[i];
1053 bool Spilled = false;
1054 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
1055 AFI->setCSRegisterIsSpilled(Reg);
1057 CanEliminateFrame = false;
1059 // Check alias registers too.
1060 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1061 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
1063 CanEliminateFrame = false;
1068 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1072 if (!STI.isTargetDarwin()) {
1079 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1094 if (!STI.isTargetDarwin()) {
1095 UnspilledCS1GPRs.push_back(Reg);
1105 UnspilledCS1GPRs.push_back(Reg);
1108 UnspilledCS2GPRs.push_back(Reg);
1115 bool ForceLRSpill = false;
1116 if (!LRSpilled && AFI->isThumbFunction()) {
1117 unsigned FnSize = ARM::GetFunctionSize(MF);
1118 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1119 // use of BL to implement far jump. If it turns out that it's not needed
1120 // then the branch fix up path will undo it.
1121 if (FnSize >= (1 << 11)) {
1122 CanEliminateFrame = false;
1123 ForceLRSpill = true;
1127 bool ExtraCSSpill = false;
1128 if (!CanEliminateFrame || hasFP(MF)) {
1129 AFI->setHasStackFrame(true);
1131 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1132 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1133 if (!LRSpilled && CS1Spilled) {
1134 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1135 AFI->setCSRegisterIsSpilled(ARM::LR);
1137 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1138 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1139 ForceLRSpill = false;
1140 ExtraCSSpill = true;
1143 // Darwin ABI requires FP to point to the stack slot that contains the
1145 if (STI.isTargetDarwin() || hasFP(MF)) {
1146 MF.getRegInfo().setPhysRegUsed(FramePtr);
1150 // If stack and double are 8-byte aligned and we are spilling an odd number
1151 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1152 // the integer and double callee save areas.
1153 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1154 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1155 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1156 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1157 unsigned Reg = UnspilledCS1GPRs[i];
1158 // Don't spiil high register if the function is thumb
1159 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1160 MF.getRegInfo().setPhysRegUsed(Reg);
1161 AFI->setCSRegisterIsSpilled(Reg);
1162 if (!isReservedReg(MF, Reg))
1163 ExtraCSSpill = true;
1167 } else if (!UnspilledCS2GPRs.empty() &&
1168 !AFI->isThumbFunction()) {
1169 unsigned Reg = UnspilledCS2GPRs.front();
1170 MF.getRegInfo().setPhysRegUsed(Reg);
1171 AFI->setCSRegisterIsSpilled(Reg);
1172 if (!isReservedReg(MF, Reg))
1173 ExtraCSSpill = true;
1177 // Estimate if we might need to scavenge a register at some point in order
1178 // to materialize a stack offset. If so, either spill one additiona
1179 // callee-saved register or reserve a special spill slot to facilitate
1180 // register scavenging.
1181 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1182 MachineFrameInfo *MFI = MF.getFrameInfo();
1183 unsigned Size = estimateStackSize(MF, MFI);
1184 unsigned Limit = (1 << 12) - 1;
1185 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1186 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1187 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1188 if (I->getOperand(i).isFrameIndex()) {
1189 unsigned Opcode = I->getOpcode();
1190 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1191 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1192 if (AddrMode == ARMII::AddrMode3) {
1193 Limit = (1 << 8) - 1;
1194 goto DoneEstimating;
1195 } else if (AddrMode == ARMII::AddrMode5) {
1196 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1197 if (ThisLimit < Limit)
1203 if (Size >= Limit) {
1204 // If any non-reserved CS register isn't spilled, just spill one or two
1205 // extra. That should take care of it!
1206 unsigned NumExtras = TargetAlign / 4;
1207 SmallVector<unsigned, 2> Extras;
1208 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1209 unsigned Reg = UnspilledCS1GPRs.back();
1210 UnspilledCS1GPRs.pop_back();
1211 if (!isReservedReg(MF, Reg)) {
1212 Extras.push_back(Reg);
1216 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1217 unsigned Reg = UnspilledCS2GPRs.back();
1218 UnspilledCS2GPRs.pop_back();
1219 if (!isReservedReg(MF, Reg)) {
1220 Extras.push_back(Reg);
1224 if (Extras.size() && NumExtras == 0) {
1225 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1226 MF.getRegInfo().setPhysRegUsed(Extras[i]);
1227 AFI->setCSRegisterIsSpilled(Extras[i]);
1230 // Reserve a slot closest to SP or frame pointer.
1231 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1232 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1233 RC->getAlignment()));
1240 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1241 AFI->setCSRegisterIsSpilled(ARM::LR);
1242 AFI->setLRIsSpilledForFarJump(true);
1246 /// Move iterator pass the next bunch of callee save load / store ops for
1247 /// the particular spill area (1: integer area 1, 2: integer area 2,
1248 /// 3: fp area, 0: don't care).
1249 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1250 MachineBasicBlock::iterator &MBBI,
1251 int Opc, unsigned Area,
1252 const ARMSubtarget &STI) {
1253 while (MBBI != MBB.end() &&
1254 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1257 unsigned Category = 0;
1258 switch (MBBI->getOperand(0).getReg()) {
1259 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1263 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1264 Category = STI.isTargetDarwin() ? 2 : 1;
1266 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1267 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1274 if (Done || Category != Area)
1282 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1283 MachineBasicBlock &MBB = MF.front();
1284 MachineBasicBlock::iterator MBBI = MBB.begin();
1285 MachineFrameInfo *MFI = MF.getFrameInfo();
1286 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1287 bool isThumb = AFI->isThumbFunction();
1288 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1289 unsigned NumBytes = MFI->getStackSize();
1290 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1293 // Check if R3 is live in. It might have to be used as a scratch register.
1294 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1295 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1296 if (I->first == ARM::R3) {
1297 AFI->setR3IsLiveIn(true);
1302 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1303 NumBytes = (NumBytes + 3) & ~3;
1304 MFI->setStackSize(NumBytes);
1307 // Determine the sizes of each callee-save spill areas and record which frame
1308 // belongs to which callee-save spill areas.
1309 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1310 int FramePtrSpillFI = 0;
1313 emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1315 if (!AFI->hasStackFrame()) {
1317 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1321 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1322 unsigned Reg = CSI[i].getReg();
1323 int FI = CSI[i].getFrameIdx();
1330 if (Reg == FramePtr)
1331 FramePtrSpillFI = FI;
1332 AFI->addGPRCalleeSavedArea1Frame(FI);
1339 if (Reg == FramePtr)
1340 FramePtrSpillFI = FI;
1341 if (STI.isTargetDarwin()) {
1342 AFI->addGPRCalleeSavedArea2Frame(FI);
1345 AFI->addGPRCalleeSavedArea1Frame(FI);
1350 AFI->addDPRCalleeSavedAreaFrame(FI);
1356 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1357 emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII);
1358 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1359 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1362 // Darwin ABI requires FP to point to the stack slot that contains the
1364 if (STI.isTargetDarwin() || hasFP(MF)) {
1365 MachineInstrBuilder MIB =
1366 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
1367 .addFrameIndex(FramePtrSpillFI).addImm(0);
1368 if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
1372 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1373 emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII);
1375 // Build the new SUBri to adjust SP for FP callee-save spill area.
1376 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1377 emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII);
1380 // Determine starting offsets of spill areas.
1381 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1382 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1383 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1384 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1385 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1386 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1387 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1389 NumBytes = DPRCSOffset;
1391 // Insert it after all the callee-save spills.
1393 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1394 emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII);
1397 if(STI.isTargetELF() && hasFP(MF)) {
1398 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1399 AFI->getFramePtrSpillOffset());
1402 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1403 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1404 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1407 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1408 for (unsigned i = 0; CSRegs[i]; ++i)
1409 if (Reg == CSRegs[i])
1414 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1415 return ((MI->getOpcode() == ARM::FLDD ||
1416 MI->getOpcode() == ARM::LDR ||
1417 MI->getOpcode() == ARM::tRestore) &&
1418 MI->getOperand(1).isFrameIndex() &&
1419 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1422 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1423 MachineBasicBlock &MBB) const {
1424 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1425 assert((MBBI->getOpcode() == ARM::BX_RET ||
1426 MBBI->getOpcode() == ARM::tBX_RET ||
1427 MBBI->getOpcode() == ARM::tPOP_RET) &&
1428 "Can only insert epilog into returning blocks");
1430 MachineFrameInfo *MFI = MF.getFrameInfo();
1431 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1432 bool isThumb = AFI->isThumbFunction();
1433 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1434 int NumBytes = (int)MFI->getStackSize();
1435 if (!AFI->hasStackFrame()) {
1437 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1439 // Unwind MBBI to point to first LDR / FLDD.
1440 const unsigned *CSRegs = getCalleeSavedRegs();
1441 if (MBBI != MBB.begin()) {
1444 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1445 if (!isCSRestore(MBBI, CSRegs))
1449 // Move SP to start of FP callee save spill area.
1450 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1451 AFI->getGPRCalleeSavedArea2Size() +
1452 AFI->getDPRCalleeSavedAreaSize());
1455 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1456 // Reset SP based on frame pointer only if the stack frame extends beyond
1457 // frame pointer stack slot or target is ELF and the function has FP.
1459 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1461 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1463 if (MBBI->getOpcode() == ARM::tBX_RET &&
1464 &MBB.front() != MBBI &&
1465 prior(MBBI)->getOpcode() == ARM::tPOP) {
1466 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1467 emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1469 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII);
1472 // Darwin ABI requires FP to point to the stack slot that contains the
1474 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1475 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1476 // Reset SP based on frame pointer only if the stack frame extends beyond
1477 // frame pointer stack slot or target is ELF and the function has FP.
1478 if (AFI->getGPRCalleeSavedArea2Size() ||
1479 AFI->getDPRCalleeSavedAreaSize() ||
1480 AFI->getDPRCalleeSavedAreaOffset()||
1483 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1485 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1487 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1488 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1489 } else if (NumBytes) {
1490 emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII);
1493 // Move SP to start of integer callee save spill area 2.
1494 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1495 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
1498 // Move SP to start of integer callee save spill area 1.
1499 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1500 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
1503 // Move SP to SP upon entry to the function.
1504 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1505 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
1510 if (VARegSaveSize) {
1512 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1513 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1514 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1516 emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII);
1519 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1525 unsigned ARMRegisterInfo::getRARegister() const {
1529 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1530 if (STI.isTargetDarwin() || hasFP(MF))
1531 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1536 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1537 assert(0 && "What is the exception register");
1541 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1542 assert(0 && "What is the exception handler register");
1546 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1547 assert(0 && "What is the dwarf register number");
1551 #include "ARMGenRegisterInfo.inc"