1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMREGISTERINFO_H
16 #define ARMREGISTERINFO_H
18 #include "llvm/Target/MRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class TargetInstrInfo;
26 struct ARMRegisterInfo : public ARMGenRegisterInfo {
27 const TargetInstrInfo &TII;
28 const ARMSubtarget &STI;
30 /// FramePtr - ARM physical register used as frame ptr.
34 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
36 /// getRegisterNumbering - Given the enum value for some register, e.g.
37 /// ARM::LR, return the number that it corresponds to (e.g. 14).
38 static unsigned getRegisterNumbering(unsigned RegEnum);
40 /// Code Generation virtual methods...
41 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator MI,
43 const std::vector<CalleeSavedInfo> &CSI) const;
45 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI,
47 const std::vector<CalleeSavedInfo> &CSI) const;
49 void storeRegToStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI,
51 unsigned SrcReg, int FrameIndex,
52 const TargetRegisterClass *RC) const;
54 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
55 SmallVectorImpl<MachineOperand> &Addr,
56 const TargetRegisterClass *RC,
57 SmallVectorImpl<MachineInstr*> &NewMIs) const;
59 void loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI,
61 unsigned DestReg, int FrameIndex,
62 const TargetRegisterClass *RC) const;
64 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
65 SmallVectorImpl<MachineOperand> &Addr,
66 const TargetRegisterClass *RC,
67 SmallVectorImpl<MachineInstr*> &NewMIs) const;
69 void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
70 unsigned DestReg, unsigned SrcReg,
71 const TargetRegisterClass *DestRC,
72 const TargetRegisterClass *SrcRC) const;
74 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
75 unsigned DestReg, const MachineInstr *Orig) const;
77 MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
78 int FrameIndex) const;
80 MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
81 MachineInstr* LoadMI) const {
85 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
87 const TargetRegisterClass* const*
88 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
90 BitVector getReservedRegs(const MachineFunction &MF) const;
92 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
94 bool requiresRegisterScavenging(const MachineFunction &MF) const;
96 bool hasFP(const MachineFunction &MF) const;
98 bool hasReservedCallFrame(MachineFunction &MF) const;
100 void eliminateCallFramePseudoInstr(MachineFunction &MF,
101 MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator I) const;
104 void eliminateFrameIndex(MachineBasicBlock::iterator II,
105 int SPAdj, RegScavenger *RS = NULL) const;
107 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
108 RegScavenger *RS = NULL) const;
110 void emitPrologue(MachineFunction &MF) const;
111 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
113 // Debug information queries.
114 unsigned getRARegister() const;
115 unsigned getFrameRegister(MachineFunction &MF) const;
117 // Exception handling queries.
118 unsigned getEHExceptionRegister() const;
119 unsigned getEHHandlerRegister() const;
121 int getDwarfRegNum(unsigned RegNum) const;
124 } // end namespace llvm