1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
22 class TargetInstrInfo;
25 struct ARMRegisterInfo : public ARMGenRegisterInfo {
26 const TargetInstrInfo &TII;
27 const ARMSubtarget &STI;
29 /// FramePtr - ARM physical register used as frame ptr.
33 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
35 /// emitLoadConstPool - Emits a load from constpool to materialize the
36 /// specified immediate.
37 void emitLoadConstPool(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator &MBBI,
39 unsigned DestReg, int Val,
40 unsigned Pred, unsigned PredReg,
41 const TargetInstrInfo *TII, bool isThumb,
44 /// getRegisterNumbering - Given the enum value for some register, e.g.
45 /// ARM::LR, return the number that it corresponds to (e.g. 14).
46 static unsigned getRegisterNumbering(unsigned RegEnum);
48 /// Same as previous getRegisterNumbering except it returns true in isSPVFP
49 /// if the register is a single precision VFP register.
50 static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
52 /// getPointerRegClass - Return the register class to use to hold pointers.
53 /// This is used for addressing modes.
54 const TargetRegisterClass *getPointerRegClass() const;
56 /// Code Generation virtual methods...
57 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
59 const TargetRegisterClass* const*
60 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
62 BitVector getReservedRegs(const MachineFunction &MF) const;
64 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
66 bool requiresRegisterScavenging(const MachineFunction &MF) const;
68 bool hasFP(const MachineFunction &MF) const;
70 bool hasReservedCallFrame(MachineFunction &MF) const;
72 void eliminateCallFramePseudoInstr(MachineFunction &MF,
73 MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator I) const;
76 void eliminateFrameIndex(MachineBasicBlock::iterator II,
77 int SPAdj, RegScavenger *RS = NULL) const;
79 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
80 RegScavenger *RS = NULL) const;
82 void emitPrologue(MachineFunction &MF) const;
83 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
85 // Debug information queries.
86 unsigned getRARegister() const;
87 unsigned getFrameRegister(MachineFunction &MF) const;
89 // Exception handling queries.
90 unsigned getEHExceptionRegister() const;
91 unsigned getEHHandlerRegister() const;
93 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
95 bool isLowRegister(unsigned Reg) const;
98 } // end namespace llvm