1 //===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
17 let Namespace = "ARM";
18 let SubRegs = subregs;
21 class ARMFReg<bits<6> num, string n> : Register<n> {
23 let Namespace = "ARM";
27 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
28 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
29 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
30 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
31 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
32 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
33 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
34 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
35 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
36 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
37 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
38 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
39 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
40 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
41 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
42 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
45 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
46 def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
47 def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
48 def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
49 def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
50 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
51 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
52 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
53 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
54 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
55 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
56 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
57 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
58 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
59 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
60 def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
61 def SDummy : ARMFReg<63, "sINVALID">;
63 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
64 def D0 : ARMReg< 0, "d0", [S0, S1]>;
65 def D1 : ARMReg< 1, "d1", [S2, S3]>;
66 def D2 : ARMReg< 2, "d2", [S4, S5]>;
67 def D3 : ARMReg< 3, "d3", [S6, S7]>;
68 def D4 : ARMReg< 4, "d4", [S8, S9]>;
69 def D5 : ARMReg< 5, "d5", [S10, S11]>;
70 def D6 : ARMReg< 6, "d6", [S12, S13]>;
71 def D7 : ARMReg< 7, "d7", [S14, S15]>;
72 def D8 : ARMReg< 8, "d8", [S16, S17]>;
73 def D9 : ARMReg< 9, "d9", [S18, S19]>;
74 def D10 : ARMReg<10, "d10", [S20, S21]>;
75 def D11 : ARMReg<11, "d11", [S22, S23]>;
76 def D12 : ARMReg<12, "d12", [S24, S25]>;
77 def D13 : ARMReg<13, "d13", [S26, S27]>;
78 def D14 : ARMReg<14, "d14", [S28, S29]>;
79 def D15 : ARMReg<15, "d15", [S30, S31]>;
81 // VFP3 defines 16 additional double registers
82 def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">;
83 def D18 : ARMFReg<18, "d18">; def D19 : ARMFReg<19, "d19">;
84 def D20 : ARMFReg<20, "d20">; def D21 : ARMFReg<21, "d21">;
85 def D22 : ARMFReg<22, "d22">; def D23 : ARMFReg<23, "d23">;
86 def D24 : ARMFReg<24, "d24">; def D25 : ARMFReg<25, "d25">;
87 def D26 : ARMFReg<26, "d26">; def D27 : ARMFReg<27, "d27">;
88 def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">;
89 def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">;
91 // Advanced SIMD (NEON) defines 16 quad-word aliases
92 def Q0 : ARMReg< 0, "q0", [D0, D1]>;
93 def Q1 : ARMReg< 1, "q1", [D2, D3]>;
94 def Q2 : ARMReg< 2, "q2", [D4, D5]>;
95 def Q3 : ARMReg< 3, "q3", [D6, D7]>;
96 def Q4 : ARMReg< 4, "q4", [D8, D9]>;
97 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
98 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
99 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
100 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
101 def Q9 : ARMReg< 9, "q9", [D18, D19]>;
102 def Q10 : ARMReg<10, "q10", [D20, D21]>;
103 def Q11 : ARMReg<11, "q11", [D22, D23]>;
104 def Q12 : ARMReg<12, "q12", [D24, D25]>;
105 def Q13 : ARMReg<13, "q13", [D26, D27]>;
106 def Q14 : ARMReg<14, "q14", [D28, D29]>;
107 def Q15 : ARMReg<15, "q15", [D30, D31]>;
109 // Current Program Status Register.
110 def CPSR : ARMReg<0, "cpsr">;
112 def FPSCR : ARMReg<1, "fpscr">;
116 // pc == Program Counter
117 // lr == Link Register
118 // sp == Stack Pointer
119 // r12 == ip (scratch)
120 // r7 == Frame Pointer (thumb-style backtraces)
121 // r9 == May be reserved as Thread Register
122 // r11 == Frame Pointer (arm-style backtraces)
123 // r10 == Stack Limit
125 def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
126 R7, R8, R9, R10, R11, R12,
128 let MethodProtos = [{
129 iterator allocation_order_begin(const MachineFunction &MF) const;
130 iterator allocation_order_end(const MachineFunction &MF) const;
132 let MethodBodies = [{
133 // FP is R11, R9 is available.
134 static const unsigned ARM_GPR_AO_1[] = {
135 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
137 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
138 ARM::R8, ARM::R9, ARM::R10,
140 // FP is R11, R9 is not available.
141 static const unsigned ARM_GPR_AO_2[] = {
142 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
144 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
147 // FP is R7, R9 is available as non-callee-saved register.
148 // This is used by Darwin.
149 static const unsigned ARM_GPR_AO_3[] = {
150 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
151 ARM::R9, ARM::R12,ARM::LR,
152 ARM::R4, ARM::R5, ARM::R6,
153 ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
154 // FP is R7, R9 is not available.
155 static const unsigned ARM_GPR_AO_4[] = {
156 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
158 ARM::R4, ARM::R5, ARM::R6,
159 ARM::R8, ARM::R10,ARM::R11,
161 // FP is R7, R9 is available as callee-saved register.
162 // This is used by non-Darwin platform in Thumb mode.
163 static const unsigned ARM_GPR_AO_5[] = {
164 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
166 ARM::R4, ARM::R5, ARM::R6,
167 ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
169 // For Thumb1 mode, we don't want to allocate hi regs at all, as we
170 // don't know how to spill them. If we make our prologue/epilogue code
171 // smarter at some point, we can go back to using the above allocation
172 // orders for the Thumb1 instructions that know how to use hi regs.
173 static const unsigned THUMB_GPR_AO[] = {
174 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
175 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
178 GPRClass::allocation_order_begin(const MachineFunction &MF) const {
179 const TargetMachine &TM = MF.getTarget();
180 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
181 if (Subtarget.isThumb1Only())
183 if (Subtarget.isTargetDarwin()) {
184 if (Subtarget.isR9Reserved())
189 if (Subtarget.isR9Reserved())
191 else if (Subtarget.isThumb())
199 GPRClass::allocation_order_end(const MachineFunction &MF) const {
200 const TargetMachine &TM = MF.getTarget();
201 const TargetRegisterInfo *RI = TM.getRegisterInfo();
202 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
203 GPRClass::iterator I;
205 if (Subtarget.isThumb1Only()) {
206 I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
207 // Mac OS X requires FP not to be clobbered for backtracing purpose.
208 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
211 if (Subtarget.isTargetDarwin()) {
212 if (Subtarget.isR9Reserved())
213 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
215 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
217 if (Subtarget.isR9Reserved())
218 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
219 else if (Subtarget.isThumb())
220 I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
222 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
225 // Mac OS X requires FP not to be clobbered for backtracing purpose.
226 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
231 // Thumb registers are R0-R7 normally. Some instructions can still use
232 // the general GPR register class above (MOV, e.g.)
233 def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
234 let MethodProtos = [{
235 iterator allocation_order_begin(const MachineFunction &MF) const;
236 iterator allocation_order_end(const MachineFunction &MF) const;
238 let MethodBodies = [{
239 static const unsigned THUMB_tGPR_AO[] = {
240 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
241 ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
243 // FP is R7, only low registers available.
245 tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
246 return THUMB_tGPR_AO;
250 tGPRClass::allocation_order_end(const MachineFunction &MF) const {
251 const TargetMachine &TM = MF.getTarget();
252 const TargetRegisterInfo *RI = TM.getRegisterInfo();
253 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
254 tGPRClass::iterator I =
255 THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
256 // Mac OS X requires FP not to be clobbered for backtracing purpose.
257 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
262 // Scalar single precision floating point register class..
263 def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
264 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
265 S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
267 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
269 def SPR_8 : RegisterClass<"ARM", [f32], 32,
270 [S0, S1, S2, S3, S4, S5, S6, S7,
271 S8, S9, S10, S11, S12, S13, S14, S15]>;
273 // Dummy f32 regclass to represent impossible subreg indices.
274 def SPR_INVALID : RegisterClass<"ARM", [f32], 32, [SDummy]> {
278 // Scalar double precision floating point / generic 64-bit vector register
280 // ARM requires only word alignment for double. It's more performant if it
281 // is double-word alignment though.
282 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
283 [D0, D1, D2, D3, D4, D5, D6, D7,
284 D8, D9, D10, D11, D12, D13, D14, D15,
285 D16, D17, D18, D19, D20, D21, D22, D23,
286 D24, D25, D26, D27, D28, D29, D30, D31]> {
287 let SubRegClassList = [SPR_INVALID, SPR_INVALID];
288 let MethodProtos = [{
289 iterator allocation_order_begin(const MachineFunction &MF) const;
290 iterator allocation_order_end(const MachineFunction &MF) const;
292 let MethodBodies = [{
294 static const unsigned ARM_DPR_VFP2[] = {
295 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
296 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
297 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
298 ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
300 static const unsigned ARM_DPR_VFP3[] = {
301 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
302 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
303 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
304 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
305 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
306 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
307 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
308 ARM::D28, ARM::D29, ARM::D30, ARM::D31 };
310 DPRClass::allocation_order_begin(const MachineFunction &MF) const {
311 const TargetMachine &TM = MF.getTarget();
312 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
313 if (Subtarget.hasVFP3())
319 DPRClass::allocation_order_end(const MachineFunction &MF) const {
320 const TargetMachine &TM = MF.getTarget();
321 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
322 if (Subtarget.hasVFP3())
323 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
325 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
330 // Subset of DPR that are accessible with VFP2 (and so that also have
331 // 32-bit SPR subregs).
332 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
333 [D0, D1, D2, D3, D4, D5, D6, D7,
334 D8, D9, D10, D11, D12, D13, D14, D15]> {
335 let SubRegClassList = [SPR, SPR];
338 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
340 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
341 [D0, D1, D2, D3, D4, D5, D6, D7]> {
342 let SubRegClassList = [SPR_8, SPR_8];
345 // Generic 128-bit vector register class.
346 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
347 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
348 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> {
349 let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
353 // Subset of QPR that have 32-bit SPR subregs.
354 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
356 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> {
357 let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
360 // Subset of QPR that have DPR_8 and SPR_8 subregs.
361 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
364 let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8, DPR_8, DPR_8];
367 // Condition code registers.
368 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
370 //===----------------------------------------------------------------------===//
371 // Subregister Set Definitions... now that we have all of the pieces, define the
372 // sub registers for each register.
375 def arm_ssubreg_0 : PatLeaf<(i32 1)>;
376 def arm_ssubreg_1 : PatLeaf<(i32 2)>;
377 def arm_ssubreg_2 : PatLeaf<(i32 3)>;
378 def arm_ssubreg_3 : PatLeaf<(i32 4)>;
379 def arm_dsubreg_0 : PatLeaf<(i32 5)>;
380 def arm_dsubreg_1 : PatLeaf<(i32 6)>;
382 // S sub-registers of D registers.
383 def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
384 D8, D9, D10, D11, D12, D13, D14, D15],
385 [S0, S2, S4, S6, S8, S10, S12, S14,
386 S16, S18, S20, S22, S24, S26, S28, S30]>;
387 def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
388 D8, D9, D10, D11, D12, D13, D14, D15],
389 [S1, S3, S5, S7, S9, S11, S13, S15,
390 S17, S19, S21, S23, S25, S27, S29, S31]>;
392 // S sub-registers of Q registers.
393 def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
394 [S0, S4, S8, S12, S16, S20, S24, S28]>;
395 def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
396 [S1, S5, S9, S13, S17, S21, S25, S29]>;
397 def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
398 [S2, S6, S10, S14, S18, S22, S26, S30]>;
399 def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7],
400 [S3, S7, S11, S15, S19, S23, S27, S31]>;
402 // D sub-registers of Q registers.
403 def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
404 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
405 [D0, D2, D4, D6, D8, D10, D12, D14,
406 D16, D18, D20, D22, D24, D26, D28, D30]>;
407 def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
408 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
409 [D1, D3, D5, D7, D9, D11, D13, D15,
410 D17, D19, D21, D23, D25, D27, D29, D31]>;